JPH01293656A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily find out a memory cell by a method wherein a width of parts which are parts of lines of a gate electrode, where the memory cell is not formed and which are used as wiring parts is made a width which is different from that of other parts at intervals of definite numbers of the lines of the gate electrode. CONSTITUTION:A memory cell is not formed under a source line 21; parts of word lines 10 which overlap with the source line 21 are used only as wiring parts. A width of the parts used as the wiring parts of the word lines 10 is made wider at intervals of prescribed numbers of the word lines 10; wide-width parts 11 are formed. The wide-width parts 11 used as marks are formed at definite intervals in the central parts of a memory array region; accordingly, even when the number of memory cells is increased, it is possible to immediately and accurately find out a memory cell situated near the center.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device in which insulated gate type semiconductor memory cells are arranged in a matrix.

[Prior Art] Conventionally, in order to find a predetermined memory cell within a memory array in which semiconductor memory cells are arranged in a matrix, a mark has been placed at the end of the memory array. Third
The figure is a plan view showing such a conventional semiconductor memory device. In FIG. 3, in a memory array region 1 in which semiconductor memory cells are arranged in a matrix, a plurality of word lines 10 are provided, which are gate electrode lines formed of a gate electrode material. This word line 10
Marks 15 are provided at the ends of the word lines 10 at intervals of a fixed number of marks. When finding a predetermined memory cell in the memory array area 1, one word line 10 is selected one by one.
Counting books takes time and causes errors in counting. Markers 15 are formed on every other word line 10 in order to quickly and accurately locate a given memory cell. This landmark 15
is conventionally made of gate electrode material, metal wiring material, etc. In the conventional semiconductor memory device shown in FIG. 3, marks 15 are formed every three word lines.

[Problems to be Solved by the Invention] However, when the capacity of memory is increased and the memory array area is expanded, the conventional marks are formed at the edges of the memory array area. A problem arises in that it is difficult to find a memory cell located in a certain area. In other words, in order to find a memory cell in the center, you must first find the corresponding word line using a landmark, and then count the memory cells along that word line, which takes time and can lead to errors in counting. There is a high possibility that this will occur.

SUMMARY OF THE INVENTION It is an object of the present invention to solve such conventional problems and to provide a semiconductor memory device in which a predetermined memory cell can be easily found even when the number of memory cells increases.

[Means for Solving the Problems] A semiconductor memory device of the present invention has a plurality of gate electrode lines in the row direction or column direction, insulated gate type semiconductor memory cells are arranged in a matrix, and the gate electrode lines are arranged in a matrix. It is characterized in that, at intervals of a certain number of gate electrodes, the width of the part of the line of the gate electrode where no memory cell is formed and is used as wiring is made different from the width of the other parts. .

[Function] In the semiconductor memory device of the present invention, the width of the portion of the gate electrode line where no memory cell is formed and is used as a wiring line is set at intervals of a certain number of gate electrode lines. The width is different from the width of other parts. Therefore, the portions having different widths used as wirings serve as marks for finding a predetermined memory cell.

Marks with different widths provided on the gate electrode lines are formed inside the memory array, so even if the number of memory cells increases, the memory cells in the center of the memory array can be easily found. .

In addition, the areas marked with different widths are areas where memory cells are not formed and are used as wiring, so changing the width will not affect the electrical characteristics of the memory cells. do not have.

[Embodiment] FIG. 2 is a plan view showing the entire memory array area of an embodiment of the present invention. Within the memory array region 1, a word line 10, which is a line of a plurality of gate electrodes, is provided. A portion 2 of this memory array area is shown in a partially enlarged plan view in FIG. In FIG. 1, a bit line 20 is provided perpendicularly to the word line 10, and this bit line 20 is connected to a contact hole 30.
It is electrically connected to the memory cell by. 3 is 1
One memory cell is shown. A line for taking the reference potential of the memory cell is provided every few bit lines 20, and this line is referred to as a source line 21 here.
It is called. The source line 21 is electrically connected to the memory cell through a contact hole 31.

No memory cells are formed under this source line 21, so the portion of the word line 10 that overlaps this source line 21 is used only as a wiring. The width of the portion of the word line 10 used as wiring is widened at every predetermined number of word lines 10 to form a wide portion 11. In the embodiment shown in FIG.
It is formed every other book.

As already mentioned, the source line 21 is the bit line 2
Since they are provided every few zeros, the wide portions 11 serving as marks are also formed at regular intervals in the center of the memory array area. Therefore, even if the number of memory cells increases,
Since the wide portion 11 as a mark exists in the center of the memory array area, memory cells located near the center can also be found immediately and accurately.

Note that since no memory cells are formed under the source line 21, even if the width of the word line 10 in this portion is widened, the electrical characteristics of the memory cell are not affected.

In this embodiment, an example was shown in which the width of the part used as the wiring of the word line 10 was widened, but conversely, the width of the part used as the wiring of the word line 10 was made narrower than the other parts. You can.

In this case, this narrowed part serves as a landmark.

In addition, the gate electrode line whose width is narrowed in this way is
It may be in the row direction or in the column direction.

[Effects of the Invention] As explained above, according to the present invention, a marking portion is formed near the center of the memory array area, so even if the number of memory cells increases and the memory capacity increases, It becomes possible to find the memory cell easily and without error.

[Brief explanation of the drawing]

FIG. 1 is a partially enlarged plan view showing an embodiment of the present invention. FIG. 2 is a plan view showing the entire memory array area of the embodiment shown in FIG. FIG. 3 is a plan view showing a conventional semiconductor memory device. In the figure, 1 is a memory array area, 2 is a part of the memory array area, 3 is a memory cell, 10 is a word line, 1
1 is a wide part of a word line, 15 is a mark formed in a conventional semiconductor memory device, 20 is a bit line, 21
Reference numeral 30 indicates a source line, 30 - a contact hole connecting the bit line and memory cell, and 31 a contact hole connecting the source line and memory cell. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor memory device in which a plurality of gate electrode lines are provided in the row or column direction and insulated gate semiconductor memory cells are arranged in a matrix, the gate electrode lines are arranged at intervals of a certain number of gate electrode lines. What is claimed is: 1. A semiconductor memory device characterized in that a width of a portion where no memory cells are formed and is used as wiring is different from the width of other portions.