JPH01292533A - Pipeline circuit - Google Patents

Abstract

PURPOSE:To attain the output of the valid data only even in case the data input timing is irregular or the valid and invalid states coexist by using the signal showing the valid or invalid state of the input data to control the production of the selection signal which decides the data holding time in a pipeline circuit. CONSTITUTION:A selection signal generating circuit 101 produces the selection signal to decide the data holding time of a data holding circuit 102. The circuit 101 is controlled by the input instruction signals T1-Tn which show the valid or invalid states of input signals A1-An respectively. When the signals T1-Tn show continuously the valid states, the selection signal holds the value of the data received first. While the selection signal is changed when a signal Tj showing an invalid state is received halfway. In such a way, only the valid data to be subsequently processed are delivered in the proper timing. Therefore both circuits 101 and 102 are set into a pipeline circuit 1000 which receives the input instruction signals T and A. Thus the valid data is delivered from a Z register 103.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and more particularly to a pipeline circuit for adjusting data timing.

[Conventional technology]

Generally, this type of pipeline circuit is used for timing adjustment of data transfer between processing devices, particularly for timing adjustment of data transfer from another processing device to an incremental type processing device.

Here, the interleave type processing device is typically a memory device that is configured with a plurality of banks and uses each bank in a time-sharing manner. Further, an arithmetic device that has a plurality of arithmetic units that perform low-speed processing arranged in a row and uses them in a time-sharing manner to collectively perform high-speed arithmetic operations is also an example of an incremental type processing device.

Figure 8 shows a series of data A-1:al+22+"・1a1
) ) ' and a series of data B = (bl, bz,...
, b, ] into four banks BANKI, BAN'. B
This is an example of a block diagram of a memory peripheral circuit of a data processing device that can write to a memory 904 composed of ANK3°BANK4, and FIG.
This is a time chart 1 showing the operation of 03.

8 and 9, each bank BANKI to BANK4 of memory 904 requires two timing cycles to write data, and data A-(
al, a2. The input register PTA which receives the signal (rap) as input is one of the reference timing cycles for crossbar control.
data B-[bl, b2. ...,b
, ] is assigned the reference timing cycle 3 to the input register RIB.

The output register ROR1 has a decoder D1 that decodes the selection signal SLI and a selection circuit SE1 that selects and outputs an input according to the output of the decoder D1.
When the reference timing cycle is 1, the LI selects and stores the output data of the input register RIA, and when the reference timing cycle is 3, the output data of the input register RIB is selected and stored, and the LI selects and stores the output data of the input register RIA when the reference timing cycle is 3. When cycles are 2 and 4, the previous data is retained.

Output registers ROR2, ROR3, ROR4 receive selection signals SL2. SL3. Decoder D2 that decodes SL4
．． D3. D4 and this decoder D2゜D3. A selection circuit SE2. selects and outputs an input according to the output of D4. S.B.
3. SE4, and select signals SL2 . SL3
．． SL4 operates similarly to output register ROR1.

In FIG. 9, the output register ROR1 is set to the input register R by the value 1 of the selection signal SLI at timing t1.
IA output data al is selected, stored at timing t2, and held until timing t3. At timing t3, the value 3 of the selection signal SLI causes the output data b of the input register RIB.

is selected, so it is stored at timing t4 and held until timing t5. In this way, the 4 X k +1st (k
is a natural number) data al+b1, "S+bS+a9+b
9+... are sequentially stored in the output register ROR1 and become the input data of the bank B'ANKI of the memory 904.

Similarly, 4. of two sets of data A and B. X k →
-2nd data a2+b2+a6+b6+alo+b
IO+... is connected to bank B through output register ROR2.
Input to ANK2, 4 x k -1-3rd data a3+ b 3+a7+ ')'1, a ll+
') I1, "' is input to bank BANK3, and 4
xl(+4th data a 4+ b4+ a B+
b[1+a, □=b+2+ ... BANK
4.

The operation explained in FIG. 9 is that when the reference timing cycle of input crossbar 903 is 1,
x, 1,000th data aI+ aS+ a, +...
is input to the input register RIA, and 4 of the series of data B
xl(+3rd data bff+b?+bI1,...
is input to the input register RIB, and when the reference timing cycle is 2, the 4x 1002nd data a
2+ ab+ a lo+ ”・is input register RIA
Then, 4×k+4th data l) of data B 4+b8+
b1□,... are input to the input register RIB, and when the reference timing cycle is 3, 4×k''-3 of data A
The 3'th data "3'+ a?+ all+..." is input to the manual register RIA, and the 4×k-F1st data b'1, b, b 7... of data B is input to the input register RIB. , when the reference timing cycle is 4, the 1004th data a B+ a B is added to 4× of data A.
+ a 12+ "' is input to the input register RIA, 4×k of data B+2nd data b 2+ b 6+ b
,. , . . . are manually input to the input register RIB.

However, in an actual data processing device, some kind of timing adjustment is generally required in order for the data to be written into the memory to match the above timing. There are two timing adjustment methods: one is to adjust the start timing of the data processing command so that the data after processing reaches the input crossbar 903 at the timing, and the other is to adjust the startup timing of the data processing command so that the data after processing reaches the input crossbar 903 at the above timing. A possible method is to include a timing adjustment circuit such as a circuit.

The former method does not require a timing adjustment circuit, but the control of the instruction startup timing is complicated, and it also affects the processing start time of other processing devices other than the memory, and the entire data processing device is The latter method is usually adopted because it is also a factor that deteriorates the performance.

In FIG. 8, pipeline circuits 901 and 902 are
This circuit is for adjusting the timing of data transfer as described above, and FIG. 10 is a block diagram of a conventional configuration of the pipeline circuit 901 or 902 shown in FIG. The figure is a time chart showing the operation.

In FIG. 10, a pipeline circuit 8000 inputs a selection information sent signal ST, selection information SO, and a series of data A - (a I+ 221 ''.lam), and inputs a series of data Y - [yl, y2..., y1
] is output.

The selection signal register 801 stores the selection information SO in response to the selection information sent signal ST, and outputs it as the selection signal S.

The data holding circuit 802 converts the selection signal S to a decoder DCD.
By decoding with
1, R2, R3, R4 selection signal S I+ 52+
"3+34" is generated and the input data A is stored in any one of the four stages of data holding means R1, R2, R3, R4. For example, the selection signal "l+SZ+S:ll
When the selection signal s3 of S4 is valid (logic "1"), data A is stored in the data holding means R3. The data A stored in the data holding means R3 is stored in the data holding means R4 after one timing cycle, and the output data of the data holding circuit 802, that is, the pipeline circuit 8
It is output as output data Y of 000.

The data holding means R2 is realized, for example, by a register RG2 having a two-man power one output selection circuit 5E12 and a gate G12 that selects the first stage or second stage of the selection circuit 5EL2 according to the selection signal s2. possible, selection signal S
When selection signal S2 is valid, data A is selected, and when selection signal S2 is invalid (logic "0°'), output data of data holding means R1 is selected and stored.

Similarly to the data holding means R2, the data holding means R3 and R4 also select the first stage or the second stage of the selection circuits 5E13 and 5E14 according to the selection circuits 5E13 and 5E14 of two-man power and one output and the selection signal S3+34. Gate G13.
Register RG3.G14. It can be achieved with RG4,
The data holding means R1 has a selection circuit 5EII that outputs an input when the selection signal sl is valid, and at that time, the data A
This can be realized by register RG1 that stores .

The registers in the data holding means R1, R2, R3, R4 are respectively set to the first . Second. Third. A Z register 803 is a fourth register that inputs and stores the output data Y of the pipeline circuit 8000 and outputs it as data Z.
The operation of the pipeline circuit 8000 is shown in FIG. 1) as follows.
This will be explained below with reference to the time charts of FIGS. 12 and 13.

FIG. 1) is a time chart showing a case where the data holding time for timing adjustment of data A is the shortest (Hest case) in the pipeline circuit 8000.

In Figure 1), input data A - (a 1) a
21 a 3+...+all) input timing, assuming the lowest case, data A is input to the pipeline circuit 8.
The signal is directly input to the fourth register RG4, which is also the output register of 000, is stored at the next timing, and is output as output data Y of the pipeline circuit 8000. Data Y output from the fourth register RG4 of the pipeline circuit 8000 is stored in the Z register 803 at the next timing.

Here, if this pipeline circuit 8000 is used as the pipeline circuit 901 in FIG. 8, the Z register 803 corresponds to the input register RIA.

The input register RIA is connected to the input crossbar 9 as described above.
Since 1 of the reference timing cycle 03 is assigned, timing t5 (series of data A - (a l + a Z'l...) in Fig. 1) is assigned.

At the timing when the first data a1 of am) is stored in the Z register 803, that is, the input register RIA, the crossbar reference timing cycle should be 1,
Assuming that timing t3 (the timing at which a is input as input data to the pipeline circuit 8000) is 1 of the reference timing cycle of the input section of the pipeline circuit 8000, the timings of the crossbar reference timing cycle and the pipeline input section reference timing cycle are as follows: is as shown in Figure 1). The reference timing cycles shown here do not mean that each has hardware such as a cycle counter, but are virtual timing cycles for designing or verifying a circuit for controlling data transfer. It is sufficient that the timing of each part within the device is relatively consistent.

In Figure 1), when the reference timing cycle of the pipeline input section is 1, a series of data A=(a I+
When the first data a1 of a 2+...+2m) is input, it is determined that the input timing is the best case, the selection signal S=4 is set, and the series of data A
-(a j+ 221 ”・I a m ) is the fourth
It is input to Z register 803 (ie, input register RIA) only via register RG4.

FIG. 12 is a time chart showing the operation of the pipeline circuit shown in FIG. 10 when the data a is input when the reference timing cycle of the pipeline input section is 2 (worst case).

In FIG. 12, when data a1 is input when the reference timing cycle of the pipeline input section is 2, it is determined that the input timing is the worst case, the selection signal S=1 is sent, and - series of data A= (a1,
a2.・-, a, ) is all of the first to fourth registers (4
The signal is input to the Z register 803 via the register of the second stage).

Similar to FIG. 12, FIG. 13 is a time chart of an example in which the selection signal S is generated using a different method for the worst case of the input timing of data a1.

When data a1 is input at timing t4 when the reference timing cycle of the pipeline input section is 2, the selection signal S
Since it indicates 4 as in the best case, it is stored in the fourth register RG4, and since the reference timing cycle of the pipeline input section is not 1, the selection signal S is set to 3. Subsequently, when data a2 is input at timing t5 when the reference timing cycle of the pipeline input section is 3, it is stored in the third register RG3 by the selection signal S=3.
The reference timing cycle of the pipeline input section is still 1.
Therefore, the selection signal S is set to 2.

The same operation is performed for data a3, and the selection signal S is set to 1. When data a4 is input at timing t7 when the reference timing cycle of the pipeline input section is 1, it is stored in the second register RG2 by the selection signal S=1, and the reference timing cycle of the pipeline input section is now 1. , the selection signal S has the same timing cycle value (S=
1), release the data holding state from the first to fourth registers, and sequentially store a series of data A − (a I+ a 2+ . . . , a1) in the Z register 803 after timing t8.
is input.

Although the system explained in FIG. 13 has the same effect as that in FIG. 12, the control of the selection signal S is more complicated than that in FIG. The fourth register RG4 is required to have a function of holding the stored data for a period of multiple timing cycles. For this reason, the method shown in FIG.
The method explained in the figure is adopted. In addition to the best case shown in Figure 1) and the worst case shown in Figure 12 or 13, cases in between (that is, the reference timing cycle of the pipeline input section is 3 or 4)
The case where data a1 is input at the time of ) can be easily considered from the best case and the worst case, so the explanation will be omitted.

[Problem that the invention seeks to solve]

The conventional pipeline circuit described above stores a series of data A-
(al+aZ+"'+ all) is input, the output timing of the first data a is adjusted by the selection signal S, and the data a and subsequent data a2+a3+... maintain the selection signal S when outputting data a1. As a result, the input data to the interleaving processing device is controlled to match the interleaving timing.
When the input timing of each data is irregular (for example, output data of a processing device whose processing time varies depending on the data value, etc.), or when a series of data includes invalid data that is not processed by an interleaved processing device. (For example, data for Masky 1 vector processing) has the disadvantage that it cannot be used.

An object of the present invention is to send only valid data for subsequent processing at appropriate timing even when the manual timing of each data is irregular or when input data includes invalid data. Our goal is to provide a pipeline circuit that can.

[Means for solving problems]

In order to achieve the above object, the pipeline circuit of the present invention provides a series of m input data Aj, A2 . . . , Aj, when the manually inputted input instruction signal Tj corresponding to one data Aj indicates invalidity, n periodic values 1, 2, .
..., 'n, 1, 2. . . . outputs a selection signal Sj indicating the next value of the value indicated by the previous selection signal Sj-1, and when the input instruction signal Tj indicates validity, the selection signal Sj-1 is output.
A selection signal generation circuit outputs a selection signal Sj indicating the same value as the value indicated by 1, and a selection signal Sj generated by the selection signal generation circuit in response to the input data Aj in response to the input data Aj. When the value indicated by signal Sj is i,
Data A1 is input to the first stage data holding means Ri of the n stages of data holding means R1, R2, . . .
..., n-i+1 from data Aj's human power via Rn
and a data holding circuit that outputs after a timing cycle, and the m data A1,Az+"'+Aj+"
・+ Am and the m input instruction signals TzTz, ・・
・+Tj+...+T e is input, and valid data among m data is n'×k+1 (k is an integer).
It has a configuration in which output is performed sequentially at intervals of timing cycles.

[Operation] The selection signal generation circuit that generates the selection signal for determining the data retention time in the data retention circuit is configured to input data Aj
, Aj...+Aj+..., validity of AjI.

Manual instruction signals T + , T 2 , . . . indicating invalidity
, T1. ....

Tj, and input instruction signals Tj, T2 .・・・
・.

Tj+..., when T1 continuously indicates valid, the selection signal retains the value of the first input data, but if an input instruction signal Tj indicating invalidity is input midway, the selection signal is Change to the following value. Through such an operation, even if the data input timing is irregular or the data includes valid data and invalid data, the input instruction signals T + , T z , . . .
..., T4. ... + By preparing Tm,
Only valid data to be processed subsequently can be sent out at appropriate timing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

First, the data format targeted by the present invention and the description method for the data format will be described below.

+1) One type of data targeted by the present invention is a series of data X = (X l+ x2+ 1, 1,
This is a case where the intervals between element data XI+X2, . . . of X m ) are irregular.

An example of this is output data from a processing device that requires different processing times depending on the data value or the like. Between the series of operand data Y-0't, Yz,..., yi] and the series of data W-(w1, w,..., W1), the control signal V= corresponding to the data is (v1, v2...., vlI)
Data R= (rI+r2
+”' +rth) is an example of the case where the intervals of the element data mentioned above are irregular. For example, the first data r
1 is output, the second data r2 is output five timing cycles after that, and the third data r is output three timing cycles after that.

When data is output sequentially and irregularly, such as when data is output, if the arithmetic device is of a type that retains the previous data until the next data is output, then
D = (r
1, r1, r'1, r1, 1'1, rz+r2+r 2
+ r 3+..., r1], and if invalid data is output between valid data, E = (r l
+ -.

+ + +r21, '+r3+ +ra]. As an output of such an arithmetic unit, a signal indicating the timing of valid data is necessary for data correspondence, and if valid is expressed as "1" and invalid as "0", the above or E data The signal F indicating valid data is F=(1,0°0,O,0,1,0,
0, 1, ..., 1], and has a one-to-one correspondence with the data G = (g1, gz+ ... 5g,] representing D and E. In the above example, g+ = r+,
gb = r2 1 gq ° r3 I ”
'+ gt-r□, and other element data g21
g81g4゜g 5+ g 7+ g ll+ . . . is invalid data and its value is not concerned.

Another example where the intervals between element data of a series of data are irregular is data read from a memory where the access time varies depending on the address. In addition, the data transfer rate varies depending on the operation mode and the status of the equipment (for example, the number of processing equipment at that time, such as the number of processing equipment at that time, where processing is normally performed using three processing equipment, and if one fails, the remaining two processing equipment continue processing). If the data from the processing system is to be operated under the same control regardless of its operating form or the state of the device, it will be a series of data containing valid and invalid data as described above.

A combination of data and a signal corresponding to the data and indicating whether each element data is valid or invalid is required, and the data and instruction signal can be expressed as the data G and instruction signal F described above.

(2) Another type of data to which the present invention applies is a type in which the validity or invalidity of individual data in a series of data is indicated by separate data on software (in other words, on a program). For example, in vector data processing devices, a concept of mask bits is introduced to indicate valid element data and invalid element data in mask data. Mask bits indicate valid data in the operand vector data and only valid data are operated on, or operations are performed on all data and mask bits are used to indicate whether the operation result data is valid or invalid. These are called masked operations.

These masked hector data are vector data H-(h
1, hz, ..., h,] and mask data J"
It can be expressed as = (J1, jz+..., j,).

Therefore, in the following explanation, a series of input data A-(a1, 22+...
, a,] and an instruction signal T= (1, O, ..., 1) that indicates whether the data is valid or invalid.This means that the element data al+a2+ ...+ am is input, a,
is valid data + a2 is invalid data.

..., al means valid data.

Now, FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, a pipeline circuit 1000 receives an input instruction signal T and a series of data A=(a1, a2...
.

all) is input, and a series of data ”=(y1, y
z+...,y,] is output.

The data holding circuit 102 inputs the selection signal S from the selection signal generation circuit 101 and decodes it with the decoder DCD, thereby forming four stages of data holding means R1, R2, R.
3. Selection signal for R4 “1I32+83+”4. and input data A to four stages of data holding means R1, R2,
It is stored in either one of R3 and R4. For example, the selection signal Sjl of the selection signal SI+”2+32+34
When is valid (logic "1"), data A is stored in data holding means R3. The data A stored in the data holding means R3 is transferred to the data holding means R after one timing cycle.
4 and is output as the output data of the data holding circuit 102, that is, the output data Y of the pipeline circuit 1000.

For example, as shown in the figure, the data holding means R2 includes a two-power one-output selection circuit 5E12 in which the output of the first data holding means R1 is added to the first stage input and the input data A is added to the second stage input; The selection circuit 5EL selects the inverted signal of the selection signal S2.
This can be realized by a register RG2 having a gate G12 which applies the selection signal S2 to the first stage of the selection circuit 5E12 and also applies the selection signal S2 as it is to the second stage of the selection circuit 5E12. When is invalid (logic "0"), the output data of the data holding means R1 is selected and stored.

Similarly to the data holding means R2, the data holding means R3, R4 also have the first stage input connected to the previous stage data holding means R2, R3.
The output of is added and the input data A is added to the second stage input 2
Selection circuit SE13 of human power 1 output, 5EL4 and selection circuit SE of inverted signal of selection signal S3+34], 3.5E1
G13.4 is added to the first stage of the selection circuits 5E13 and 5E14, and the selection signal S3+Sj is directly added to the second stage of the selection circuits 5E13 and 5E14. G14 and register RG3
．． The data holding means R1 is a selection circuit 5E that outputs the input data A when the selection signal S1 is valid.
LL, and can be realized by a register RGI which stores data A via this selection circuit 5EII.

When the input instruction signal T input corresponding to the data A indicates invalidity (logic "0"), the selection signal generation circuit 101 performs the following operations.
Four periodic values 1, 2. 3. 4° 1.2. . . , a selection signal S indicating the next value of the value indicated by the previous selection signal S is generated and output. For example, if the input instruction signal T-0 is input when the selection signal S indicates 1, the selection signal S indicates 2 at the next timing. Similarly, the selection signal S is 2
If the input instruction signal T=O is input when the selection signal S indicates 3, the selection signal S will indicate 3 at the next timing, and if the input instruction signal T=O is input when the selection signal S indicates 3, the selection signal S will indicate 3 at the next timing. In this case, the selection signal S indicates 4, and when the input instruction signal T=0 is input when the selection signal S indicates 4, the selection signal S indicates 1 at the next timing.

Conversely, when the input instruction signal T indicates valid (logic "1"),
The value indicated by the previous selection signal S is held.

For example, when the selection signal S indicates 1, the input instruction signal T=1
When inputted, the selection signal S shows 1 at the next timing as well.

As shown in the figure, the selection signal generation circuit 101 described above is a two-man power one-output selection system in which the output of +1 circuit AD is added to the first stage input and the value of the current selection signal S is added to the second stage input. This can be realized by a cycle counter CNT having a circuit 5E21 and a gate G21 which applies an inverted signal of the manual instruction signal T to the first stage of the selection circuit 5E21 and adds the input instruction signal T to the second stage. This cycle counter CNT
selects the value of rs+IJ, which is the output of the +1 circuit AD, when the input instruction signal T=O, and selects the value of "S" when T=1, thereby generating the selection signal S in synchronization with the timing cycle. change the value of. The range of values indicated by this selection signal S is 1. 2. 3. There are 4 ways.

The registers RGI to RG4 in the data holding means R1, R2, R3, and R4 are respectively set to the first . 2nd) 3rd. Fourth
The operation of the pipeline circuit 1000 will be described below with reference to the time chart of FIG. 2, assuming that the Z register 103 is a register that inputs and stores output data Y of the pipeline circuit 1000 and outputs it as data Z.

In FIG. 2, input data A=(a1,”!+aa+
...] corresponding to the input instruction signal T (0,1,0°0
．． 1,1. O, O, 0, 1, 0, 0, 1, 0°0.0.
O, O, -). In other words, a Z+ a S+a
6+ aIO+ aI:l+ "' is valid data, conversely "I+23+24+a? +aB+29+all+
a12+ a14+ a IS+ a1
6+a I? + a Ifi... is invalid data.

Also, the first element data a of the series of input data A,
The timing at which is inputted is tl, and the selection signal S at that time is 2. Before the data a1 is input, that is, before the timing 1, the selection signal S is set to one of four periodic values 1. 2. 3. 4. i.

2.3,4,1. . . , and shows a value of 2 at timing tl.

In FIG. 2, data a input at timing t1
1 is set to the second register R by the selection signal S=2 at that time.
It is input to G2 and stored at the next timing t2. The selection signal S at timing t2 is the same as the previous timing t1.
The input instruction signal T=Q at the time indicates the next value 3 of the selection signal S=2 at timing t1.

Subsequently, the data a2 inputted at timing t2 is inputted to the third register RG3 according to the selection signal S=3 at that time, and is stored at the next timing t3. Data a stored in the second register RG2 at timing t2
I is not stored in the third register RG3 at timing t3 and becomes invalid.

The selection signal S at timing t3 is the same as the previous timing t.
Due to the input instruction signal T=1 at the time of 2, the selection signal S=3 at the time of the 2-fiming t2 is held.

Furthermore, data a is input at timing t3.

is selected from the third register RG by the selection signal S=3 at that time.
3 and stored at the next timing t4. Data a2 stored in the third register RG3 at timing t3 is input to the fourth register RG4 at timing t3, and is stored at the next timing t4. timing t
The selection signal S at 4 is the input instruction signal T=O at timing t3.

The selection signal S=3 indicates the next value 4.

Similarly, data a4 inputted at timing t4 is inputted to the fourth register RG4 according to the selection signal S=4 at that time, and is stored at the next timing t5. timing t
The selection signal S at 5 indicates the next value 1 due to the input instruction signal T-01 selection signal S-4 at timing t4.

Similar operations are repeated in subsequent timing cycles, and data a2+a4. as+a 6+
a IO+ all+ aIff+ a16+
”・are respectively at timing t4.t5.t9.tl
O, tlL t12. t16, t17. ... and becomes element data of the output data Y of the pipeline circuit 1000, and is stored at the next timing t5. t6.
tlO, tll, t12. t13. t1
7°t18. ... is stored in the 2 register 103.

Here, input data A = (a 1) a 2+ a
Valid data a 2+ of the element data of n+ "')
If the output timing interval of a S+ a 6+ aIO+a 13+ ... is 5 between data a2 and a5
(-4X1+1) timing cycle, 1 (-4XO4-1) timing cycle between data a5 and a6, 1 timing cycle between data a6 and alO,
Data a. There are 5 timing cycles between and a13,
4×+1 timing cycle (
However, k is an integer) interval.

If pipeline circuit 1000 is used as pipeline circuits 901 and 902 in FIG.
B wins 8 yen. Here, as described above, the input register RIA is assigned the reference timing cycle 1 of the input crossbar 903, and the input register RIB is assigned the reference timing cycle 3 of the input crossbar 903, and the timing t5 (data a2 is Z register 103
In other words, the timing at which it is stored in the input register RIA)
The third example shows an example of the operation of the pipeline circuit 902 when 1 coincides with the crossbar reference timing (that is, the operation in FIG. 2 is the operation of the pipeline circuit 901).
This will be explained below with reference to the time chart shown in the figure.

In FIG. 3, at the timing of the timing cycle, the selection signal Sj changes one timing cycle ahead of the crossbar reference timing. That is, when the first valid data is input in this state (accompanied by the input instruction signal T=1), the valid data is input to the Z register 103 (i.e., input register RI) when the crossbar reference timing is 1.
B). As described above, the input register RIB which inputs the data B is assigned the crossbar reference timing 3, so it is necessary to shift the operation timing.

Therefore, for example, if the dummy input instruction signal T=1 is input twice at the timing before the first valid data is input, the pipeline circuit 902 can manually input the first valid data when the crossbar reference timing is 3. Can be stored in register RIB. That is, in FIG. 3, by inputting the dummy input instruction signal T=1 at timings t2 and t3, the controller waits at timing t4, one timing cycle behind the crossbar reference timing.

In this state, input data B-(b, b
z, t)1,...] and the input instruction signal T= (0,0,1,1,1,,0,1°1.0
．． O, 0, 1, . . . ], the pipeline circuit operates in the same way as the pipeline circuit described in FIG. b4. ．． b, b1, . . . are timing t6+tlO+jll+t, respectively. It
It is stored at 13+... and the next timing t? ＋L
II+ L 12'+j +31 j +a+ ・
... is stored in the Z register, that is, the input register RIB.

Through the operations shown in FIGS. 2 and 3, the data input to the input registers RIAjRIB is transferred to each bank BA of the memory 904 through the operations shown in the time chart of FIG.
NKI, BANK2. BANK3. Input to BANK4.

As mentioned above, input register RIA is assigned a reference timing cycle of 1, input register RIB is assigned a reference timing cycle of 3, and output register ROR1 is assigned a reference timing cycle of 1 when the reference timing cycle is 1. selects and inputs the output data of the input register RIB, stores it when the reference timing cycle is 2, holds the previous data when the reference timing cycle is 3, selects and inputs the input data of the input register RIB, It is stored when the reference timing cycle is 4, and when the reference timing cycle becomes 1 again, it retains the previous data and selects and inputs the output data of the input register RIA, and stores when the reference timing cycle is 2,
. . . The same operation is repeated every four timing cycles.

Also, as described above, the output register ROR2 operates in the same way as when the operation of the output register ROR1 is delayed by one timing cycle. That is, when the reference timing cycle is 2, the output data of the input register RIA is selected and inputted, and stored at the next timing, and when the reference timing cycle is 4, the output data of the input register RIB is selected and inputted at the next timing. The action of storing 4
Repeat every timing cycle. Output register RO
R3 performs the same operation as if the operation of output register ROR2 were delayed by one additional timing cycle, and output register ROR4 operates the same as if the operation of output register ROR3 was delayed by one additional timing cycle.

As a result of these operations, as shown in FIG. 4, at timing t5 when the reference timing cycle is 1, the input register RIA
Data a2 stored in is stored in output register ROR1 at timing t6, data a4 stored in input register RIA at timing t6 is stored in output register ROR2 at timing t7, and data a4 is stored in output register ROR2 at timing t7, and at timing t7 when the reference timing cycle is 3. Data b stored in input register RIB is transferred to output register RO at timing t8.
Stored in R1. After that, the same operation is repeated, and the data a2+')I+')3+all+b$+a13+
... is input to the memory bank BANK1 via the output register ROR1, and the data "4+" S+
b 4. b lO+a16. ... is output register R
The data ab+b%... is input to the memory bank BANK3 via the output register ROR3, and the data a
lO+ 1)? + ”・ is output register ROR4
The signal is input to the memory bank BANK4 via the .

Here, input data A=(aIla21a31”・)
Among the element data, data D-(d
l+d2+d3+dl+ds+”・) −(a!+aS
+"6+alO+a13+...') and input data B
= Data F of only valid data among the element data of (bl, bz, b3゜...) = (f1, fz+f3+f
4. fs+...) = (b3+ bAj bs.

b7. b8. ...], data D and F 4
+1st (k is an integer) data al (=az>
.

f+(-b:+)+d5(-a1,),f,(=
bs ) + - is sent to memory bank BANKI, 4Xk of data D and F + second data dz (-a5), f
z (=b4), ... goes to memory bank BANK2,
Data D and F 4. X k 4-3rd data d
3 (=86).

fs(-bs),... is transferred to the memory bank BANK3, and the 4×k+4th data d4(-a
It can be seen that +o), fa(=bx), and - are input to memory bank BANK4.

In other words, even if the input data includes invalid data, the pipeline circuit of the present invention is effective as a timing adjustment circuit for supplying data to an interleaving processing device along 1lli@ of only valid data. It can be seen that it is.

FIG. 5 is a process diagram of a second embodiment of the present invention. In addition to the input data A in the first embodiment of FIG. 1, an input instruction signal T is also input to the data holding circuit 502. This is an example of improving the effect of the pipeline circuit of the present invention.

In FIG. 5, a pipeline circuit 5000 receives an input instruction signal T and a series of data A-(a1, az+...).

am) as input, output instruction signal H and series of data Y
Output.

The data holding circuit 502 inputs the selection signal S from the selection signal generation circuit 501, and outputs the selection signal S by the decoder DCD.
The selection signals s1, sg for the data holding means R1, R2, R3゜R4 of the stage are decoded to s1, sg]+"4, and the data P is obtained by arranging S data 8 and the input instruction signal T corresponding to data 8 in a one-to-one correspondence. a four-stage data holding means R1,
Stored in one of R2, R3, and R4. For example, when the selection signal S3 of the selection signals SI+32+33134 is valid, the data P is stored in the data holding means R3. The data P stored in the data holding means R3 is
After one timing cycle, the data is stored in the data holding means R4 and becomes the output data of the data holding circuit 502, that is, the output data of the pipeline circuit 5000. Among this output data, output data corresponding to input data A is Y.

The data corresponding to the input instruction signal T is set to H, and the registers that input and store output data Y and H and output them as data Z and E are respectively Z register 503 and E register 5.
04.

The other parts in the pipeline circuit 5000 are the same as the pipeline circuit 1000 in FIG. 1, so the description thereof will be omitted.

Pipeline circuit 5000 is replaced by pipeline circuit 901. in FIG. And if used as 902,
The combination of the E register and Z register corresponds to the input registers RIA and RIB of the input crossbar 903, but for the sake of explanation, as shown in FIG.
The partial register corresponding to the register is RIAj and RI.
Let it be B. Registers RIA and EIA operate identically,
Registers RIB and EIB operate identically. Similarly,
As for the output registers, partial registers EOR1 to EOR4 are added as shown in Fig. 7, and registers ROR1 and EOR1 have the same operation, registers ROR2 and EOR2 have the same operation, registers ROR3 and EOR3 have the same operation, and register ROR4 has the same operation. and EOR4 operate in the same way, and an example of the operation inside the input crossbar 903 when the pipeline circuit 5000 is used as the pipeline circuits 901 and 902 in FIG. 7 is shown in the block diagram of FIG. This will be explained below with reference to the time chart in FIG.

Input data A='(a1,
a2+ a3+...], the input instruction signal corresponding to
TA = (0,1,0,0,L 1,0,0,0.L
O.

Q, L O, O, O70, ...], input data B to the pipeline circuit 902 = Cb1, bz, bs, ...
...], the input instruction signal corresponding to Ts - (0, 0,
1゜1.1. O, L 1. O, 0, 0, L...
] Then, in the same manner as in the first embodiment explained in FIGS. 1 to 4, data is stored in the input registers RIAjEIAjRIB and EI'B of the crossbar as shown in FIG. is input.

In FIG. 6, the data a2 and the instruction signal PA1'' of the data a2 stored in the input register RIAjEIA at timing t5 when the reference timing cycle is 1 are stored in the output registers ROR1 and EORI at timing t6,
The data a4 stored in the input register tAjEIA at the timing t6 and the instruction signal “0゛” of the data a4 are as follows.
It is stored in the output registers ROR2 and BOR2 at timing t7, and the reference timing cycle is 3 at timing t7.
The data bl stored in input registers RIB and EIB in
, and data b, the instruction signal Pa0'' is at timing t8.
are stored in the output registers ROR1 and EOR1. After that, the same operation is repeated, and the output register ROR1 is
a2+ bI+ b:lI ” l1,... are stored, and the corresponding instruction signals 1°0.1.O,...
・is stored in the output register EOR1, and data a 4+
a S+ bl+ "' is in the output register ROR2,
Corresponding instruction signal 0. 1. 1. ... is in the output register EOR2, data a6+ b S+... is in the output register ROR3, and the corresponding instruction signals 1, 1 . ... is in the output register EOR3, data aIO+b? +・
. . are stored in the output register ROR4, and the corresponding instruction signals 1°1, . . . are stored in the output register EOR4.

At timing t6, the data a2+ and data a2 instruction signal “
1" is input to BANK1 of the memory, and the instruction signal is "l", so data a2 is input at timing t7.
It is stored in BANKI of memory.

At timing t7, the data a4 stored in the output registers ROR2 and EOR2 and the instruction signal "'0" of the data a4
” is input to BANKI of the memory, but since the instruction signal is “O”, data a4 is not stored.

Thereafter, the data "2+ b3+ "' is stored in BANKI of the memory by the same operation, and the data as+b4
+... goes to BANK2, data a6+ bS+ "'
goes to BANK3, data aI O+ b? +”・ is stored in BANK4.

Through the operations described above, the input data A '' (al + a2+ '' 3+・
...] valid data aZ+as+a6+"IO+
aI3+ ”'+ and data B-(bl, b2.
b3. ...] valid data b3. b4. ．． b3
．． 'b7. This means that b8 is stored in the memory in the order of only valid data.

In this way, the pipeline circuit 5000 in FIG.
The pipeline circuit has the functions of the pipeline circuit 1000 shown in the figure, with an additional function of transmitting an instruction as to whether the output data is valid or invalid to the subsequent circuit.

〔Effect of the invention〕

As explained above, the pipeline circuit of the present invention uses a signal indicating whether input data is valid or invalid to generate a selection signal for determining the data retention time in the pipeline circuit. Therefore, even if the input timing of data is irregular, or if valid data and invalid data are mixed in the data, only valid data to be processed later can be sent at an appropriate timing, and The control circuit is also simple and can be realized with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is a time chart showing the operation within the pipeline circuit of the first embodiment, and FIG. 3 is the pipeline of the embodiment of FIG. 1. FIG. 4 is a time chart showing an example of the operation of the input crossbar using the output from the pipeline circuit of the first embodiment; FIG. A block diagram of the second embodiment, FIG. 6 is a time chart showing an example of the operation of the input crossbar using the output from the pipeline circuit of the second embodiment, and FIG. 7 is a pipeline diagram of the second embodiment. A block diagram showing an example of the configuration of a memory peripheral circuit to which the circuit is applied. FIG. 8 is a block diagram of a memory peripheral circuit of a data processing device having a memory composed of four banks. FIG. 9 is an input diagram of the memory peripheral circuit of FIG. A time chart showing an example of the operation of the crossbar 903; FIG. 10 is a block diagram of a conventional pipeline circuit;
), FIGS. 12 and 13 are time charts showing the operation of the pipeline circuit of FIG. 10. In the figure, 101.501...Selection signal generation circuit 102.5
02...Data holding circuit 1000.5000...
- Pipeline circuits 901, 902...Pipeline circuit 903...Input crossbar 904...Memory 801...Selection signal register 802
...Data holding circuit 8000 ...Pipeline circuit patent applicant
1 person from outside NEC Corporation

Claims (2)

[Claims] (1) A series of m input data A_1, A_2,...
, A_m, when the input instruction signal T_j input corresponding to one data A_j indicates invalidity, the periodic n
Among the possible values 1, 2,..., n, 1, 2,...
A selection signal S_j indicating the next value of the value indicated by the previous selection signal S_j_-_1 is output, and when the input instruction signal T_j indicates validity, the selection signal S_j indicating the same value as the value indicated by the selection signal S_j_-_1 is output. and a selection signal S_j generated by the selection signal generation circuit corresponding to the data A_j in response to the input of the data A_j, when the value indicated by the selection signal S_j is i, n Data A_j is input to the data holding means Ri of the i-th stage among the data holding means R1, R2, . . . , Rn of the stages, and the data holding means Ri+1, Ri+2, . and a data holding circuit that outputs the data after n-i+1 timing cycles from the input of the data A_j via the m data A_1, A_2, . . . , A_j, .
..., A_m, and the m input instruction signals T_1, T_
2, . pipeline circuit. (2) In the pipeline circuit according to claim 1, the data holding circuit stores the m input data A_1.
, A_2, . . . , A_m, the same information as the m input instruction signals T_1, T_2, . . . , T_m is input.