JPH01291522A - Programmable logic device - Google Patents

Abstract

PURPOSE:To read out data stored in the memory transistor of an AND array in a PLD in spite of the presence/absence of security data by providing a control means to output a data readout voltage outputted from a voltage means from the bit line of the AND array corresponding to an inputted control signal. CONSTITUTION:When a word line WL1 or WL2 is selected as an H level, the output terminal of an OR gate OR3 in a security attaching circuit 10 goes to the H level, and a voltage of L level is inputted to the first input terminal of an AND gate AND1, then, the output terminal of the AND gate AND1 goes to an L level. Therefore, an output signal SEQa with L level is inputted to the first input terminal of an OR gate OR1 in a verify circuit 2, and thereby, the verify circuit 2 is set at an operating state, and it is possible to read out the data from a FAMOSFETtheta M in the AND array 6.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to programmable logic devices (hereinafter referred to as
It's called PLD. ) regarding.

[Conventional technology] FIG. 2 is a circuit diagram of a conventional PLD.

In FIG. 2, the Y decoder 3 decodes the input Y address signal of, for example, 4 bits, and outputs the decoded signal to nine Y address selection lines YS1 to YS9. These nine Y address selection lines YSI to YS
9 is an N-channel MO3' for Y address selection.
l field effect transistor (hereinafter referred to as N-channel MO3il)
The field effect transistor is called NMO3FET. ) is connected to each gate of Ql to Q9.

During programming, the program circuit 1 is connected to each floating gate MO3 field effect transistor (hereinafter referred to as FAM○5FET) of the AND array 6, which will be described in detail later.
A DC high voltage Vpp of, for example, +12V is output from the output terminal for programming the OFF state. The output terminal of the program circuit l is connected to the bit line BLI via each drain and source of the NMO3FETs Ql to Q8.
or connected to BL8. Further, the output terminal of the program circuit 1 is connected to the node N1 of the security circuit 4 via the drain and source of the NMO3FET Q9.

The X decoder 5 receives the input 3-bit X address signal R.
An is decoded and the decoded signal is converted into eight word lines WL to WL8 (hereinafter, the symbols are collectively referred to as WL).
shall be. ).

An EEFROM, for example, FMO3, is installed at each intersection of the bit lines BLI to BL3 (hereinafter, the symbols are collectively referred to as BL) and the word lines WLI to WL8.
FET M is formed.

Here, as shown in FIG. 3, the gate of FMO3FETM is connected to the word line WL, and the FMO3FETM
The drain of M is connected to the bit line BL and FMO3
The source of FET M is connected to ground. Therefore,
A total of 64 FMs at each intersection of 8 word lines WL1 to WL8 and 8 bit lines BLI to BL8.
An O3FETM is formed. Further, the eight bit lines BLI to BL8 are connected to a known OR array (not shown) within this PLD.

In the verify circuit 2, the control signal input terminal στπ is connected to the second input terminal of the OR gate OR1, and is also connected to the gate of the NMO8FET TR5 via the inverter INVI of the security circuit 4. In addition, the control signal input terminal σ10π is the N of the security circuit 4.
Connected to each gate of MO3FET TR6 and TR7.

Further, the output signal SEQ of the security circuit 4 output from the inverter INV3 of the security circuit 4 is input to the first input terminal of the OR gate OR1.

The output terminal of OR gate OR1 is connected to the first input terminal of OR gate oR2, and the output terminal of OR gate OR1 is connected to the first input terminal of OR gate oR2.
Connected to each gate of TRI and TR2. Here, N
The drains of MO3FET TRI and TR2 are connected to the +5■ DC power supply VCC, for example, and the NMO3FET
The source of TRI is connected to the second input terminal of OR gate OR2 and to the drain of NMO3FET TR3.

Furthermore, the source of NMO3FET TR2 is NMO
3FET TR3 gate and NMOS FET
Connected to the drain of TR4, NMO3FET TR
The source of 4 is connected to ground. NMO3FET
The source of TR3 and the gate of NMO3FET TR4 are connected to the output terminal of the program circuit 1. The output signal Vn of the verify circuit 2 is output from the output terminal of the OR game 1-0R2.

In security circuit 4, node N1 is FMO3F
Connected to the drain of ET MM and NMO
Connected to the drain of 3FET TR5. Also, F
The source of MO3FET MM is connected to ground and F
The gate of MO3FET MM is connected to voltage application terminal AV. Furthermore, NMO3FET TR5(7)7
- The source is the source of NMOS FET TR6 and the source of NMOS FET TR6.
It is connected to the drain of MO3FET TR7, and also connected to the input terminal of inverter INV3 via inverter INV2. The drain of the NMO3FET TR6 is connected to the DC power supply VCC, which is, for example, +5V, and the 7-path of the NMO8FET TR7 is connected to the '7-sim. The output signal SEQ of the security circuit 4 is output from the output terminal of the inverter INV3 to the OR gate OR1.
is input to the first input terminal of. The FAMOSFET MM in the security circuit 4 is an EEPROM in which security bit data is written to prevent the data of the FAMOSFET M in the AND array 6 from being read. Here, when writing the security bit data to the FAMO8FET MM and programming it to off, the FAM in the AND array 6
The data of OSFET M can be made unreadable, and the security bit data can be made unreadable.
AMO3FET FAMOSFET in AND array 6 when not written to MM and programmed off.
M data can be made readable.

Here, input the security bit data to FAMOSFE.
When writing to TMM, program voltage input terminal AV
For example, a program voltage of +12.5 V is applied to the FAMOSFET MM, and the program voltage is applied from the program circuit 1 to the drain of the FAMOSFET MM. This allows the FAMOSFET MM to be programmed off and the security bit data to be written to the FAMO3FET MM.

On the other hand, when data of the security bit is not written to the FAMO3FET MM, a DC voltage Vcc of, for example, +5V is applied to the program voltage input terminal AV.

Regarding the operations of the conventional PLD configured as described above, (1) PLD decoding operation, (2) verifying operation,
and (3) security operations will be explained below.

(1) PLD decoding operation During this operation, one FMO in the AND array 6
A 4-bit Y address signal CAn and a 3-bit X address signal RAn for selecting SFET M are input to an X decoder 3 and an X decoder 5, respectively. In response, the X decoder 3 decodes the input Y address signal CAn and outputs the decoded signal to the Y address selection lines YS1 to YS8. It decodes the signal RAn and outputs the decoded signal to the word lines WLl to WB2. For example, when selecting the FMOSFET M at the intersection of the bit line BLI and the word line WLI, the
to YS9 are set to the L level, and the X decoder 5 sets the word line WL1 to the H level and the remaining word lines WL2 to WB2 to the L level. At this time, NMO3FET Ql is turned on and the remaining NM
O3FET Q2 to Q9 are turned off. During logic operation, as will be described in detail later, the verify circuit 2 outputs the H level DC voltage Vcc from the output terminal to the selected N
Output to bit line BLI via the drain and source of MO3FET Ql. Therefore, bit line BL
When I is set to H level and word line WL1 is set to H level, the selected FMOSFET M
f7) An H level DC voltage is applied to the gate. At this time, for example, when FMOSFET M is programmed off, FMOSFET M still remains off and bit line BLI remains at H level.

On the other hand, when FMOSFET M is not programmed, FMOSFET M is turned on and bit line BLl is connected to ground and becomes L level.

(2) Verify operation During this verify operation, the L level control signal σ
ππ is manually input to the second input terminal of the OR gate ○R1 of the verify circuit 2. Here, when the output signal SEQ of the security circuit 4 is at L level, the OR gate ORI
The output terminal of NMO3FE becomes L level, and at this time, NMO3FE
T TRI.

TR2 turns on, which causes NMO3FET
TR3 turns on. At this time, an H-level DC voltage from the DC power supply Vcc is applied to the drain and source of NMO8FET TR1, the drain and source of NMO3FET TR3, and one NMOSFE selected by the Y address signal CAn among NMO3FETs Ql to Q9.
It is output to one of the bit lines BLI to BL8 through the drain and source of T.

Therefore, the selected bit line is set to H level, the selected word line is set to H level, and one selected FAMO3FET connected to the selected bit line and the selected word line is set to H level. M
When programmed off, the selected FAMO above
5FET M is turned off. At this time, the potential Va of the node connected to the selected bit line is H
Since the potential vb of the node in the verify circuit 2 becomes the H level, an output signal Vn of the H level is output from the output terminal of the OR gate OR2.

As described above, the X address signal RAn and the Y address signal C
The data write state of the FAMO3FETM selected by An, that is, the selected FAMO3F
Whether or not ETM is programmed off can be output as an output signal Vn.

(3) During the security operation verify operation, the control signal σER is set to L level, and in response, the verify circuit 2
T Outputs H level DC voltage Vcc from the source of TR3. On the other hand, the Y address signal CAn for selecting NMOS FET Q9 is input and the NMOSF
ET Q9 is turned on. As a result, the H level DC voltage Vcc is input from the verify circuit 2 to the 7-domain Nl in the security circuit 4 via the drain and source of the selected NMOSFET Q9. On the other hand, for example, an H level DC voltage Vcc of +5V is applied to the FAMO5FET MM via the program voltage input terminal AV.
input into the gate.

Kokote, the above F AMOS FET MM fake+
When the data of the srity bit is not written,
FAMO3FET MM is on, while NMO
H level DC voltage Vc is applied to the gate of SFET TR5.
c is applied and NMOSFET TR5 is on, so the source of NMOSFET TR6 and NM
The voltage Vc at the connection point of the drain of OSFET TR7 becomes L level, and as a result, the L level output signal SEQ is input from the output terminal of inverter INV3 to the first input terminal of OR gate ORI of verify circuit 2.
The verify circuit 2 enters the operating state described above.

On the other hand, when the security bit data is written in the FAMO3FET MM, the FAMO5FE
TMM remains off and NMOS remains off as above.
Since FET TR5 is on, the above voltage V
C′h<H level, and this causes the inverter IN
The H level output signal SEQ from the output terminal of V3 is input to the first input terminal of ORI of the verify circuit 2, and the verify circuit 2 becomes inactive. At this time, in the verify circuit 2, the OR gate OR1
The output terminal of the NMOS becomes H level, which causes the NMOS
Both FET TRI and TR2 are turned off, and the output terminal of OR gate ○R2 becomes H level. Above N
When MO3FETs TRI and TR2 are both turned off, no DC voltage Vcc is supplied to the bit line. Furthermore, an H level output signal Vn is output from the output terminal of the OR gate OR2.

Therefore, the FAMO3FET in the security circuit 4
When security bit data is written in MM, one bit (DFAMO) in AND array 6 selected by X address signal RAn and Y address signal CAn
Regardless of the presence or absence of writing to 8FET M (D-?-), the verify circuit 2 outputs an H level output signal Vn, thereby
It becomes impossible to read data from FET M.

[Problems to be Solved by the Invention] In the conventional PLD described above, when the security bit data is written in the security circuit 4 (71FAMO3FET MM), the output signal SEQ becomes H level and verification is not performed. Circuit 2 does not operate and all FAMO3FEs in the AND array 6
Data cannot be read from TM.

Therefore, the security bit data is transferred to FAMO3FE.
When writing to the TMM, it is necessary to constantly read out data, such as so-called signature data to identify the product type during factory inspection of this PLD, and user code data to allow users to identify individual PLDs. There is a problem in that certain types of data cannot be read out.

An object of the present invention is to solve the above-mentioned problems, and to write the data of the security bit to a memory transistor such as a FAMO3FETMM, regardless of whether or not the data of the security bit is written to a memory transistor such as a FAMO3FETMM. An object of the present invention is to provide a PLD equipped with a security function that can read out data.

[Means for Solving the Problems] The present invention provides an AND array including a plurality of first memory transistors, and security data for preventing data stored in the first memory transistors from being read. a second memory transistor for storing, and does not output a data read voltage to the bit line of the AND array when the security data is stored in the second memory transistor; and voltage output means for outputting a data read voltage to the bit line of the AND array when data is not stored in the second memory transistor, the voltage output means in response to an input control signal. The present invention is characterized by comprising a control means for controlling the data read voltage to be outputted to the bit line of the AND array.

The present invention is characterized in that the manually input control signal is the voltage of the word line of the AND array.

In the present invention, the manually input control signal is a signal obtained by decoding an address signal for designating a selected one of the plurality of first memory transistors of the AND array. It is characterized by

[Function] The PLD configured as described above includes a control signal for controlling the voltage output means to output the data read voltage to the bit line of the AND array in response to an input control signal. Therefore, by inputting the control signal, the data read voltage can be output to the bit line of the AND array regardless of whether or not confidential data is written.

Therefore, it is possible to read data stored in the first memory transistor, such as various specific data that always require data reading as described above.

Further, the output control signal may be, for example, a voltage of a word line of the AND array, or an address for designating a selected one of the plurality of first memory transistors of the AND array. This is a composite signal.

[Embodiment] FIG. 1 is a block diagram of a PLD that is an embodiment of the present invention, and the same parts in FIG. 1 as in FIG. 2 are designated by the same reference numerals.

The PLD of this embodiment has two specific word lines WLl compared to the conventional PLD of FIG.

The present invention includes a security addition circuit 10 that outputs an L level output signal 5EQa to the verify circuit 2 regardless of the security focus data setting in the security circuit 4 when reading data from the FAMO3FET M connected to the WL2. Features. The above differences will be explained in detail below.

In FIG. 1, the output signal SEQ output from the security circuit 4 is input to the first input terminal of the AND gate ANDl in the seven-keyity adding circuit 10. The two word lines WLl and WL2 are OR gates, respectively.
3 input terminals. The output terminal of OR gate OR3 is connected to AND gate AN via inverter INVIO.
It is connected to the second input terminal ' of Dl. The output signal 5EQa of the security addition circuit 10 is connected to the AND gate AND
From the output terminal of I to the OR gate in the verify circuit 2
It is input to the first input terminal of l.

In the PLD configured as above, when word line WLI or WL2 is set to H level and selected,
The output terminal of the OR gate OR3 in the security addition circuit IO becomes H level, and the L level voltage is input to the first input terminal of Antogame LANDI.
The output terminal of the AND gate AND1 becomes L level.

Therefore, the L level output signal 5EQa is input to the first input terminal of the OR gate ○R1 in the verify circuit 2,
As a result, the verify circuit 2 becomes operational, and data can be read from the FAMO3FETM in the AND array 6.

As explained above, word line wr, 1. When wL2 is set to H level and selected, L is sent to verify circuit 2.
Since the security addition circuit 10 that outputs the level output signal 5EQa is provided, when the word line WLI, WL2 is selected, that is, when the word line: /WL l, WL21= connected FAMO3FET M is selected,
Security addition circuit 10 outputs L level output signal 5EQ
a can be output to the verify circuit 2. This brings the verify circuit 2 into an operating state, which has the advantage of being able to read data from the FAMO3FET M in the AND array 6.

In the above embodiment, word lines WLI, W
When one of L2 is selected, output signal 5
Verify circuit 2 by setting EQa to L level.
The FAMO3F is configured to be in an operating state, but the present invention is not limited to this, and the FAMO3F can be configured to read data regardless of whether security bit data is written or not.
Any word line WLI to W to which the ETM is connected
L8 is connected to the agate OR3 in the security addition circuit 10.
It may also be configured by connecting it to the input terminal of.

In the above embodiment, regardless of whether security bit data is written or not, the FA in the AND array 6
In order to read the data written in MO3FET M, X
A composite signal generated from the address signal or the Y address signal may be used, or another decoder may be provided, and another selected address signal may be input to this other decoder and decoded by this other decoder. It may be configured such that the generated signal is input to the OR gate OR3 in the security addition circuit IO.

In the above embodiment, a FAMO, which is an electrically erasable and programmable ROM (hereinafter referred to as EEPROM), is used as a memory transistor in the AND array 6.
8FET M is used, but is not limited to this, and other types of EEF ROM.

An erasable and programmable ROM (hereinafter referred to as EPROM) or a fuse-type memory element may also be used.

[Effects of the Invention] As detailed above, according to the present invention, in the PLD,
Since the control means is provided for controlling the data read voltage outputted from the voltage means' to be outputted to the bit line of the AND array in response to the input control signal, regardless of whether confidential data is written or not, It is possible to read data stored in the memory transistors of the AND array of the PLD, such as certain types of data that require constant data reading.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a PLD according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional PLD, and FIG. 3 is a circuit diagram showing the FAMO3FET of FIGS. 1 and 2. DESCRIPTION OF SYMBOLS 1... Program circuit, 2... Verification circuit, 3... Y decoder, 4... Security circuit, 5... X decoder, 6... AND array, 10... Security addition circuit. Patent Applicant Rico Co., Ltd. First Attorney Patent Attorney Aohaku Ao Haka 1 person Figure 3

Claims (3)

[Claims] (1) an AND array including a plurality of first memory transistors; a second memory transistor storing confidentiality data for preventing data stored in the first memory transistor from being read; When the security data is stored in the second memory transistor, no data read voltage is output to the bit line of the AND array; on the other hand, when the security data is not stored in the second memory transistor. and voltage output means for outputting a data read voltage to the bit line of the AND array, wherein the data read voltage is output from the voltage output means to the bit line of the AND array in response to an input control signal. A programmable logic device characterized by comprising control means for controlling output to a bit line. (2) The programmable logic device according to claim 1, wherein the input control signal is a voltage of a word line of the AND array. (3) The input control signal is a signal obtained by decoding an address signal for designating one memory transistor selected from among the plurality of first memory transistors of the AND array. A programmable logic device according to claim 1, characterized in that: