JPH10289592A - Nonvolatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make possible simultaneously writing plural bits in a memory cell and improving a processing speed at a write-in time by writing plural bit data in a latch means at a data write-in time and simultaneously selecting plural word lines with these data. SOLUTION: An address is inputted to an address input circuit 11, and the data are inputted to an I/O circuit 13 at the write-in time. The input address is decoded by a pre-decode circuit 23, and a pre-decode signal is generated, and one is selected from decode circuits DC0-DC63, and the data are written in a latch circuit in its circuit by a latch write-in circuit 25. When respective latch circuits of all decode circuits DC0-DC63 are selected, and the write-in are ended, a control gate is selected by a control gate decode circuit 17, and a bit line is selected by a bit line decode circuit 19. Since plural selection gates of the memory cell are selected simultaneously by a latch data value and a selection signal of a driver selection circuit 27, plural bit data are written simultaneously in a memory cell array 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device such as a flash memory.

[0002]

2. Description of the Related Art Conventionally, as a memory cell array used for a nonvolatile semiconductor memory device such as a flash memory, a NAND type cell and a NOR type cell which can be highly integrated have been known. However, these cells are not suitable for high-speed reading or reading at a low voltage because the threshold voltage must be controlled to a voltage within a predetermined narrow range at the time of writing or erasing. There is a split gate type cell as a cell in which these problems are improved. As an example of this split gate type cell, a region sandwiched between opposed strip-shaped buried diffusion layers (bit lines) is defined as a channel region, and a region within a predetermined range continuous from one end of the channel region is defined as a charge storage layer (floating gate). ) And a control gate, and the remaining region of the channel region is controlled by a selection gate. FIG. 5 shows a part of a circuit diagram of a memory cell array using the split gate type cells.

[0003] As shown in the figure, the split gate type cell includes memory cells M00 to M33 for storing data, and select transistors S00 to S33 adjacent to these memory cells M00 to M33, respectively. Memory cells M00 to M33 and select transistor S adjacent thereto
It forms a pair with 00 to S33. The split gate type cells include control gate lines C0 and C1 for selecting memory cells M00 to M33, and select transistors S00 to S33.
33, select gate lines SG0 to SG3 for selecting
The memory cells M00 to M33 and the selection transistors S00 to S00
Bit lines BS0 to BS2 for selecting a pair of S33,
BD0 to BD2. Here, the bit line BS
0 to BS2 are connected to the sources of memory cells M00 to M33, and bit lines BD0 to BD2 are connected to memory cells M00 to M33.
33 is connected to the drain. The write and erase operations will be described below.

In such a split gate type cell, data is written by applying a predetermined voltage to the select gate 55 of the select transistor, the control gate 51 of the memory cell, and the bit line to inject electrons into the floating gate 53. Performed by For example, when writing data to the memory cell M11, the selection gate line SG1 is set at 2V, the selection gates SG0, SG2, SG3 are set at 0V, the bit line BS0 is set at 0V, and the bit line BD0 is set at 5V.
The other bit lines BD1, BS1, and BS2 are set to 0V,
The control gate C0 is set to 12V. Further, at the time of writing data, the data is erased in advance from the memory cell to which the data is written, and the memory cell is in a state of holding either “0” or “1” by erasing.

[0005] Data is erased by applying a predetermined voltage to the control gate 51 and the bit line of the memory cell to extract electrons from the floating gate 53 which is a charge storage layer of the memory cell. For example, when data is erased from the memory cells M00 to M03 and M10 to M13,
The select gate lines SG0 to SG3 are all set to 0V, the bit line BD0 is set to 5V, and the other bit lines BD1, BS0
BS2 is opened, the control gate line C0 is set to -12V, and the other control gate lines C1 are set to 0V. Thus, in the split gate type cell, the minimum unit of erasure is 1
A memory cell group sharing one control gate line (hereinafter referred to as an “erase block”), in other words, a memory cell group sharing one bit line. That is, the erase unit is a bit line unit.

On the other hand, conventionally, there is a method of simultaneously writing a plurality of bits to a memory cell in order to improve processing efficiency when writing data to the memory cell.
For example, the method disclosed in Japanese Unexamined Patent Publication No. Hei 3-295098 shows a case where a NAND cell in which an erase unit is a word line unit is used for a memory cell array, and a latch circuit is provided for each bit line. By writing data to the latch circuit, and after completing the data writing to the latch circuit, by simultaneously controlling the potentials of all the bit lines to a predetermined voltage for writing according to the data written to the latch circuit, the memory cells on the plurality of bit lines At the same time. This enables writing in a shorter time than writing in byte units.

[0007]

However, this method is
In the case of a memory cell array composed of split gate type cells as shown in FIG. 5, it cannot be applied because the erase unit is a bit line as described above. That is, in the split gate type cell shown in this example, at the time of writing data, only one bit line can be written at a time. Therefore, as described above, one latch is provided for each bit line, and The method of writing data at the same time cannot be applied. Therefore, conventionally, in a semiconductor memory device such as a split gate type cell having a memory cell array in which an erase unit is a bit line, it has been impossible to improve the processing speed by simultaneously writing a plurality of bits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to enable simultaneous writing of a plurality of bits in a memory cell whose erasing unit is in the bit line direction. It is another object of the present invention to provide a nonvolatile semiconductor memory device in which the processing speed at the time of writing is improved.

[0009]

A first non-volatile semiconductor memory device according to the present invention has a memory cell in which a charge storage layer and a control gate are laminated and stores data based on charges stored in the charge storage layer. Have a memory cell array arranged in a matrix. The memory cell array includes bit lines connecting memory cells in a first direction of the matrix and word lines connecting memory cells in a second direction of the matrix. The first nonvolatile semiconductor memory device has such a memory cell, specifies a memory cell by selecting a bit line and a word line, writes data therein, and connects the memory cell connected to the same bit line. In a nonvolatile semiconductor memory device having a group as an erase unit, write data composed of a plurality of bits is held for each word line selected based on a data address, and based on a data address and a value of the held data. Decoding means for simultaneously selecting a plurality of word lines connected to the memory cells to which data is to be written. This enables simultaneous writing of data to a plurality of memory cells on the same bit line. Further, in the first nonvolatile semiconductor memory device, the decoding means includes a predecoding means for sequentially selecting a word line group based on an address of write data, and a word line group for each word line group selected by the predecoding means. Latch means for holding data to be written to a memory cell connected to one of the word lines, and a memory cell to which data is to be written based on the value of the data held in the latch means and the address of the data. Driver means for simultaneously selecting a plurality of word lines connected to the same.

In a second nonvolatile semiconductor memory device according to the present invention, a predetermined region continuous from one end of a channel region is controlled by a charge storage layer and a control gate, and a remaining region of the channel region is selected by a selection gate. And a memory cell array in which split gate type memory cells for storing data based on charges stored in the charge storage layer are arranged in a matrix. The memory cell array includes a bit line connecting the memory cells in a first direction of the matrix for detecting a data read current, a control gate line connecting the control gates of the memory cells in the same direction as the bit lines, And a selection gate line connecting between the selection gates of the memory cells in the second direction of the matrix. The second nonvolatile semiconductor memory device has the above-described memory cell, specifies a memory cell by selecting a bit line, a control gate line, and a select gate line, and writes data to the same bit line. In a nonvolatile semiconductor memory device having a connected memory cell group as an erasing unit, write data composed of a plurality of bits is held for each selection gate line selected based on the address of the data, and the data address and the held data are held. Decoding means for simultaneously selecting a plurality of selection gate lines connected to the memory cells to which data is to be written based on the value of the selected data and applying a predetermined voltage for writing to the selected selection gate lines. Was. This enables simultaneous writing of data to a plurality of memory cells on the same bit line. Further, in the second nonvolatile semiconductor memory device, the decoding means includes: a predecoding means for sequentially selecting a selection gate line group based on an address of write data; and a selection gate line group selected by the predecoding means. Latch means for holding data to be written to a memory cell connected to one of the select gate lines in a select gate line group, and data is written based on the data value and the data address held in the latch means. Driver means for simultaneously selecting a plurality of select gate lines connected to the memory cells to be selected and applying a predetermined voltage for writing to the selected select gate lines.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention will be described with reference to the accompanying drawings. <1. Overall Configuration> FIG. 1 is a schematic block diagram of a semiconductor memory according to the present embodiment. This semiconductor memory includes an address input circuit 11 for inputting an address, an I / O circuit 13 for inputting data, a memory cell array 15 composed of split gate type memory cells, and a control gate for the memory cell array 15 based on the input address. A control gate decode circuit 17 for selecting a line, a bit line decode circuit 19 for selecting a bit line of the memory cell array 15 based on an input address, a select gate line of the memory cell array 15 based on an input address, and A decoding unit 21 for providing write data. Further, the semiconductor memory includes a predecode circuit 23 that generates a predecode signal that is a signal for selecting a select gate line of the memory cell array 15 based on an input address;
A latch writing circuit 25 for writing data to be latched in the decoding unit 21; a driver selection circuit 27 for selecting a driver for selecting a selection gate line of the memory cell array 15 based on an input address; Circuit 2 that compares the data read through the memory cell with the data stored in the memory cell array 15
9, a sense amplifier 30 for detecting a bit line current, and a mode control circuit 3 for controlling the operation of these circuits.
1 and a timing control circuit 33 for giving timing to the mode control circuit 31.

The memory cell array 15 in the semiconductor memory is composed of the split gate type cell shown in FIG. 5 and has 1024 select gate lines. 1
The 024 select gate lines are divided into 64 select gate line groups every 16 lines. As shown in FIG. 1, the decode unit 21 includes 64 decode circuits DC0 to DC63 corresponding to each of these select gate line groups.
Consists of Each of the decode circuits DC0 to DC63, as shown in FIG.
, A latch circuit 43, and a select gate driver circuit 45. The select gate decode circuit 41 inputs a predecode signal, decodes the predecode signal, and
One of the four select gate line groups is selected. The latch circuit 43 latches (holds) write data. The selection gate driver circuit 45 includes a write enable signal (hereinafter, referred to as “RE signal”), a program enable signal (hereinafter, referred to as “PE signal”), and driver selection signals VS0 to VS15, / VS0 to / VS.
15 (“/” represents an inverted signal), and selects a selection gate line of the memory cell array 15 and supplies a predetermined voltage to the selected selection gate line.

<2. Operation> When data is written to the semiconductor memory configured as described above, a “write operation”, which is an operation of writing data to a memory cell, is performed, and then, whether data is correctly written to the memory cell Are performed, and the above-described "write operation" and "verify operation" are repeated until it is confirmed that data has been correctly written.

<2.1. Write Operation> The outline of the “write operation” will be described below. In the “write operation”, first, an address is input to the address input circuit 11 and data is input to the I / O circuit 13. The input address is decoded by the predecode circuit 23, and a predecode signal is generated. With this predecode signal, one of the decode circuits DC0 to DC63 is output.
One decode circuit is selected. Data is written to the latch circuit 43 in the selected decoding circuit by the latch writing circuit 25. After the data is written into the latch circuit 43, a predecode signal for selecting the next decode circuit is generated by the predecode circuit 23, and the next decode circuit is selected based on the predecode signal. Data is written.
Thereafter, the decoding circuit is sequentially selected, and data is written to the latch circuit 43 in the decoding circuit. When all the latch circuits 43 are selected and the data writing is completed, the control gate is selected by the control gate decode circuit 17, the bit line is selected by the bit line decode circuit 19, and the data latched by the latch circuit 43 is selected. The selection gate driver circuit 45 selects a plurality of selection gates of the memory cell at the same time on the basis of the value of the data and the selection signal from the driver selection circuit 27. In this way, data of a maximum of 64 bits is simultaneously written.

That is, in the semiconductor memory of the present embodiment, the decoding section 21
Of the memory cell array 15 at the same time based on the value of the latched data and the address of the data, thereby simultaneously selecting a plurality of selection gates of the memory cell array 15. Writing can be performed.

The details of the "write operation" will be described below. For convenience of description, before describing the details of the “write operation”, first, a detailed configuration of the decoding unit 21 will be described. FIG. 3 shows a circuit diagram of the decoding unit 21. As shown in the figure, in the decoding unit 21, a circuit unit including 64 select gate decode circuits 41 is referred to as a predecoder unit 410, a circuit unit including 64 latch circuits 43 is referred to as a latch unit 430, and 64 A circuit section including the selection gate driver circuit 45 is referred to as a driver section 450. In addition,
Since the circuit configurations of the decoding circuits DC0 to DC63 are all the same, the decoding circuit DC0 will be described in the following description.

In the decoding circuit DC0, the selection gate decoding circuit 41 has a NOR gate NR0.
The input terminal of the NOR gate NR0 is connected to three of the twelve predecode signal lines. Latch circuit 43
Is two inverters IV connected in cross-coupling
1, IV2, and each inverter IV
1, the input terminals of IV2 are MOS transistors Tr1, Tr
2 are connected to data lines / LD and LD. The gates of the transistors Tr1 and Tr2 are connected to the output terminal of the NOR gate NR0.

The selection gate driver circuit 45 includes a NAND
Gates NA1 to NA3, inverter IV3, drivers DR0 to DR15, and pull-down transistor Tr3
To Tr18. Driver DR0-DR1
Reference numeral 5 denotes an inverter. The input terminal of the NAND gate NA1 is connected to the output terminal of the NOR gate NR0 and the RE signal line, and the input terminal of the NAND gate NA2 is connected to the output terminal of the latch circuit 43 and the PE signal line.
The output terminals of the gates NA1 and NA2 are connected to the input terminal of the NAND gate NA3, respectively, and the output terminal of the NAND gate NA3 is connected to the input terminal of the inverter IV3. The output terminal of the inverter IV3 is connected to a driver D for selecting the selection gate lines SG0 to SG15 of the memory cell array 15.
Connected to the input terminals of R0 to DR15. Driver DR0
To DR15 are connected to select gate lines SG0 to SG15 of the memory cell array 15. Driver DR0
The control input terminal of DR15 has driver selection signal lines VS0 to VS0.
VS15 is connected to the driver selection signal lines VS0 to VS0.
One of the drivers DR0 to DR15 is selected by the VS15. Pull-down transistors Tr3 to Tr18
Has a drain connected to the output terminals of the drivers DR0 to DR15, a source grounded, and a gate connected to the driver selection signal lines / VS0 to / VS15.

Hereinafter, the details of the "write operation" will be described based on the operation of the decoding section 21 configured as described above. As described above, before the “write operation” starts, data is erased in advance from the memory cells in the erase block including the memory cells to which the data is written. In the case of the present embodiment, when the memory cell is erased, it is in a state of holding data “1”, and when it is written, it is in a state of holding data of “0”.

In the "write operation", first, the RE signal and the PE signal are set to Lo by the mode control circuit 31.
The level is set to w level (hereinafter, referred to as “L”). At this time, the output of the inverter IV3 is at a high level (hereinafter, referred to as a high level).
Called "H". ), And “L” is output from the drivers DR0 to DR15.
G1023 is set to “L”, and no memory cell is selected. That is, at this time, the memory cell array 15 and the decode unit 21 are disconnected. In this state, as described above, the decode circuit DC
0 to DC63 are sequentially selected. Here, selection of a decoding circuit by a predecode signal will be described.

As shown in FIG. 4, the predecode circuit 23
Is a 12-bit signal, and designates one of the 64 decoding circuits. Further, as shown in the figure, 12 bits of the predecode signal are divided into three groups G1 to G3 each of 4 bits, which is an information amount necessary to designate one of 64 decoding circuits. Of the six bits, the first two bits correspond to the group G1, the middle two bits correspond to the group G2, and the last two bits correspond to the group G3. Each group G1 to G3 of the predecode signal is 2
It has four signal lines corresponding to the four signals represented by bits. The NOR gates NR0 to NR63 in the decode circuits DC0 to DC63 have one group G1 to G3.
Three signal lines selected one by one are connected. Here, a signal line is connected to each of the NOR gates NR0 to NR63 so that a 6-bit value can be sequentially expressed by a combination of three signal lines. In the present embodiment, all three input bits of the NOR gates NR0 to NR63 in the predecode signal are at the low level.
A decode circuit including an R gate is selected.

As described above, the decoding circuits DC0 to DC0 are generated by the predecoding signal from the predecoding circuit 23.
63 is selected and the selected decoding circuits DC0 to DC0 are selected.
Data is written to the latch circuit 43 provided in the DC 63. For example, when the decode circuit DC0 is selected by the predecode signal, the selection gate decode circuit 4
The output of the NOR gate NR1 at "1" becomes "H".
As a result, the transistors Tr1 and Tr2 are turned on, and the data output to the data lines LD and / LD are latched by the latch circuit 43. Thereafter, similarly, the other decoding circuits DC1 to DC63 are sequentially selected, and the decoding circuits DC1 to DC63 are similarly selected.
The data is sequentially latched by each latch circuit 43 in DC63.

During this time, the bit lines BS0, BD0... Are selected by the bit line decode circuit 19 and the control gate lines C0... Are selected by the control gate decode circuit 17 in accordance with the memory cell to be written. It is controlled to a predetermined voltage.

Hereinafter, memory cells M15, M31,.
The case where data is written to 023 will be described.
At this time, the 16th select gate line SG15, SG31,... SG1023, control gate line C0, and bit lines BS0, BD0 in each select gate line group are controlled to a predetermined voltage. Specifically, the voltage of the bit line BD0 is 5
V, the voltage of the bit line BS0 becomes 0 V, and the control gate line C
The voltage of 0 is set to 12V. At the same time, the 16th select gate line SG15, S15 in each select gate line group
In order to select G31,..., SG1023, only the voltage of the driver selection signal line VS15 is set to 1.8 V by the driver selection circuit 27, and the voltages of the other driver selection signal lines VS0 to VS14 are set to 0V. Is done.

When data writing to the latch circuits 43 in all the decoding circuits DC0 to DC63 is completed, the mode control circuit 31 changes the PE signal from "L" to "H". Here, the PE signal is "H".
Is determined by the time required for writing to the memory cell, and is, for example, about 10 μsec.

When data "0" is written in the latch circuit 43 (in this embodiment, "0" is "L"
Corresponding to ), When the PE signal becomes “H”, the NAND
The inputs of the gate NA2 are all "H", the output is "L", the NAND gate NA3 outputs "H", and the inverter IV3 outputs "L". At this time, the driver selection signal line VS1 is set based on the input address.
5 outputs the voltage 1.8V of the driver selection signal line VS15 to the selection gate lines SG15, SG31,... SG1023. .., SG1008 to SG1022 connected to the unselected drivers DR0 to DR14.
Become "L" by the pull-down transistors Tr3. In this way, 16 gates in each select gate line group
.., SG1023.
Is selected. Therefore, the selection transistor S15,
SG31,..., S1023 are turned on, and the control gate line C0 is turned on.
Is selected, when the data latched in each latch circuit 43 is “0”, the memory cells M15 and M3
Data "0" is written to 1, ..., M1023.

On the other hand, when data "1" is written in the latch circuit 43, the output of the NAND gate NA2 becomes "H" and the output of the NAND gate NA1 is "H". L ”, and the inverter IV3 outputs“ H ”. For this reason, the driver DR15 outputs "L" despite being selected by the driver selection signal line VS15, and the driver DR15 outputs
, S, connected to the select gate lines S15, S31,.
G1023 becomes “L”. Unselected driver DR0
, DR1008 to DR1022 are select gates connected to pull-down transistors Tr3 to Tr1.
7 to “L”. As described above, when data “1” is stored in the latch circuit 43, no data is written to the memory cell M15 because the selection gate is not selected. This is because the data "1" at the time of erasing is originally held in the memory cell as described above, so that the data does not need to be rewritten.

As described above, in the "write operation", the selection gate line is selected by the predecoder 410 in the decoder 21 based on the input address.
The write data is latched by the latch section 430 in correspondence with the selection gate line. Thereafter, the selection gate line is selected by the driver unit 450 based on the input address,
Data is written to the memory cell when the latched data is "0", and data is not written to the memory cell when the latched data is "1". The voltage of the gate line is controlled to a predetermined voltage. This makes it possible to simultaneously write a plurality of bits of data to the memory cells.

<2.2. Verify Operation> The "verify operation" will be described in detail below. When data is written to the memory cell in the "write operation", the data latched in the latch circuit 43 and the data stored in the memory cell 15 are read out by the comparison circuit 29, and these data are compared. The result is output to the mode control circuit 31. The mode control circuit 31 refers to the comparison result. If the data is not correctly written, the data is written again to the memory cell in which the data has not been correctly written. The "write operation" and the "verify operation" are repeated.

Here, the verify operation for memory cell M15 will be described. After data is written to the memory cell, the mode control circuit 31
The signal is changed from “H” to “L”, and the driver selection signal line V
S15 is 5V, bit line BS0 is 2V, bit line BD0
Is set to 2V and the control gate line C0 is set to 4.5V, so that the memory cell M15 is prepared for verification.

In this state, the RE signal is changed from "L" to "H". When the RE signal is "H", the NAND gate N
The output of A1 is the inverse of the output of NOR gate NR0. When the decode circuit DC0 is selected by the predecode signal, the output of the NOR gate NR0 of the decode circuit DC0 becomes “H” and the NAND gate NA
1 becomes "L" and the output of the NAND gate NA3 becomes "H", so that the voltage of the selection gate line SG15 connected to the driver DR15 selected by the driver selection signal line VS15 changes to the driver selection signal line VS15. , Which is 5V. On the other hand, when the decode circuit DC0 is not selected by the predecode signal, the output of the NOR gate NR0 becomes "L",
The output of A1 is "H", the output of NAND gate NA2 is "H", the output of NAND gate NA3 is "L", and the output of inverter IV3 is "H". Therefore, regardless of selection / non-selection by the driver selection signal lines VS0 to VS15, the selection gate lines SG0 to SG0 are not selected.
SG15 is controlled to "L". As described above, in the decoding circuit selected by the predecode signal, only the selection gate line selected by the driver selection signal line has 5
V.

At this time, if sufficient writing is performed on the selected memory cell (here, memory cell M15), no current flows between bit line BS0 and bit line BD0. If sufficient writing has not been performed on the selected memory cell, bit lines BS0 and BD0
A current flows between. Since the sense amplifier 30 for detecting this current is connected to the end of the bit line BS0, the data writing to the memory cell can be confirmed by detecting the current flowing through the bit line BS0 with this sense amplifier. That is, the comparison circuit 29 compares the current detection result by the sense amplifier 30 with the data latched by the latch circuit 43, and outputs the comparison result to the mode control circuit 31. Mode control circuit 3
1 judges the comparison result, and if the writing has been sufficiently performed, rewrites the content of the latch circuit 43 to “1”. If the writing is insufficient, the content of the latch circuit 43 is set to “0”.
Rewrite to As described above, verification is performed on one select gate line group. Thereafter, so that the verification is performed for all the selected gate line groups,
The decoding circuit is sequentially selected by the predecode signal,
Verification is performed sequentially. Verify is performed on all select gate line groups, and if there is at least one insufficiently written memory cell, the RE signal and the P signal
The E signal is set to "L", and data is written again according to the above-described write procedure. The above-described “write operation” and “verify operation” are repeated until all the data stored in the latch circuit 43 becomes “1”.

<3. Conclusion> As described above, the semiconductor memory according to the present embodiment has an erasing unit in the bit line direction and has a latch for storing a plurality of bits of data in a semiconductor memory having a memory cell array 15 composed of split gate memory cells. The decoding section 21 having the section 430 is provided.
Data is latched to 0, a plurality of selection gate lines of the memory cell array 15 are simultaneously selected based on the latched data value and data address, and a predetermined voltage for writing is supplied to the selected selection gate line. . This enables simultaneous writing of a plurality of bits of data to a plurality of memory cells on the same bit line, thereby shortening the processing time at the time of writing.

In the above description, a semiconductor memory using a memory cell array composed of split gate type memory cells has been described. However, the memory cell array is not limited to this, and a memory cell having a charge storage layer and a control gate may be used. One memory cell is specified by a bit line and a word line in a matrix arrangement, and the present invention can be applied to a semiconductor memory using a memory cell array having a memory cell group connected to the same bit line as an erase unit. That is, the word line is regarded as the selection gate line, the decode unit 21 is provided for the word line, the write data is latched, and the latched data is output at the same time. A plurality of bits of data can be written, and the same effect can be obtained.

[0035]

According to the non-volatile semiconductor memory device of the present invention, a charge storage layer and a control gate are formed in a stack, and memory cells for storing data based on the charges stored in the charge storage layer are arranged in a matrix. In a nonvolatile semiconductor device including a memory cell array having an erasing unit in a line direction, when data is written, data of a plurality of bits is written to a latch means, and a plurality of word lines are simultaneously selected based on the latched data of a plurality of bits. Thus, simultaneous writing of a plurality of bits into a memory cell is enabled, and the processing speed at the time of writing can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a schematic configuration diagram of a decoding circuit.

FIG. 3 is a circuit diagram of a decoding unit.

FIG. 4 is a circuit diagram of a select gate decode circuit.

FIG. 5 is a configuration diagram of a memory cell array using split gate cells.

[Explanation of symbols]

11 ... address input circuit, 13 ... I / O circuit, 15
... memory cell array, 17 ... control gate decode circuit,
19: bit line decoding circuit, 21: decoding unit,
23: Predecode section, 25: Latch write circuit, 26, 30: Sense amplifier, 27: Driver selection circuit, 29: Comparison circuit, 31: Mode control circuit, 33: Timing control circuit, 41
... Selection gate decode circuit, 43 ... Latch circuit, 4
5 ... selection gate driver circuit 51 ... control gate
53: floating gate, 410: predecoder, 430: latch, 450: driver, BS
0 to BS2, BD0 to BD2 ... bit lines, C0, C1
... Control gate line, DR0, DR15 ... Driver, IV
1 to IV3: inverter, LD: latch data line,
M00 to M1023 ... memory cells, NR1, NR63
... NOR gates, NA1 to NA3 ... NAND gates
S00 to S1023 ... selection transistors, SG0
SG1023: selection gate line, Tr1, Tr2: transistor, Tr3 to Tr18: pull-down transistor, VS0 to VS15: driver selection signal line.

Claims (4)

[Claims] 1. A charge storage layer and a control gate are stacked and formed, and memory cells for storing data based on charges stored in the charge storage layer are arranged in a matrix, and the memory cells are connected in a first direction of the matrix. Bit lines,
A non-volatile semiconductor storage device having a memory cell array including a word line connecting memory cells in a second direction of the matrix, wherein the memory cell is specified by selecting the bit line and the word line. In a nonvolatile semiconductor memory device in which a memory cell group connected to the same bit line is used as an erase unit, write data consisting of a plurality of bits is written for each word line selected based on the address of the data. And decoding means for simultaneously selecting a plurality of word lines connected to a memory cell to which data is to be written, based on the address of the data and the value of the held data. Semiconductor memory device. 2. The non-volatile semiconductor memory device according to claim 1, wherein said decoding means selects a word line group sequentially based on an address of said write data;
For each word line group selected by the predecoding means,
Latch means for holding data to be written to a memory cell connected to one of the word lines in the word line group; and data based on the value of the data held in the latch means and the address of the data. A non-volatile semiconductor memory device having driver means for simultaneously selecting a plurality of word lines connected to a memory cell to be written. 3. A predetermined region continuous from one end of the channel region is controlled by a charge storage layer and a control gate, and the remaining region of the channel region is controlled by a selection gate to store the charge in the charge storage layer. A nonvolatile semiconductor memory device having a memory cell array in which split gate type memory cells for storing data based on electric charges are arranged in a matrix, wherein the memory cell array includes a memory cell array for detecting a data read current. A bit line connecting a memory cell in the direction 1; a control gate line connecting a control gate of the memory cell in the same direction as the bit line; and a select gate of the memory cell in a second direction of the matrix A memory cell by selecting the bit line, the control gate line, and the select gate line. In a nonvolatile semiconductor memory device in which a memory cell group connected to the same bit line is used as an erase unit, write data consisting of a plurality of bits is selected by a selection gate selected based on an address of the data. A plurality of select gate lines connected to memory cells to which data is to be written are simultaneously selected based on the data address and the value of the held data. And a decoding means for applying a predetermined voltage for writing to the nonvolatile semiconductor memory device. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said decoding means is a predecoding means for sequentially selecting a selection gate line group based on an address of said write data, and is selected by said predecoding means. For each selected gate line group, latch means for holding data to be written to a memory cell connected to one select gate line in the selected gate line group; and a value of the data held in the latch means. Driver means for simultaneously selecting a plurality of selection gate lines connected to the memory cells to which data is to be written based on the address of the data and applying a predetermined voltage for writing to the selected selection gate lines. A nonvolatile semiconductor memory device characterized by the above-mentioned.