JPH01289269A - Spare gate device - Google Patents
Spare gate deviceInfo
- Publication number
- JPH01289269A JPH01289269A JP63119616A JP11961688A JPH01289269A JP H01289269 A JPH01289269 A JP H01289269A JP 63119616 A JP63119616 A JP 63119616A JP 11961688 A JP11961688 A JP 11961688A JP H01289269 A JPH01289269 A JP H01289269A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- input
- spare
- output
- scan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は論理LSIの中に予備ゲートが設けられてい
て、論理LSIの論理修正を行うことのできる予備ゲー
ト装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a spare gate device in which a spare gate is provided in a logic LSI and can modify the logic of the logic LSI.
第2図は従来の予備ゲート装置の構成図で、図において
、lはスキャン入力、2はスキャン出力、3はスキャン
パス、4は予備ゲート用入力A、5は予備ゲート用入力
B、6は予備ゲートの出力Y、7は予備ゲート入力A4
と予備ゲート入力B5の論理積をとり出力を予備ゲート
出力Yに送出するANDゲートである。FIG. 2 is a configuration diagram of a conventional backup gate device. In the figure, l is a scan input, 2 is a scan output, 3 is a scan path, 4 is a backup gate input A, 5 is a backup gate input B, and 6 is a scan output. Spare gate output Y, 7 is spare gate input A4
This is an AND gate that performs the logical product of and the preliminary gate input B5 and sends the output to the preliminary gate output Y.
ここでこのANDゲート7が予備ゲートに相当すること
になる。Here, this AND gate 7 corresponds to a spare gate.
次に動作について説明する。通常のスキャン動作は、ス
キャン入力lからデータが入力され、スキャンパス3を
通って、スキャン出力2にデータが出力されて、行われ
る。Next, the operation will be explained. A normal scan operation is performed by inputting data from the scan input 1, passing through the scan path 3, and outputting the data to the scan output 2.
一方、この論理LSIの空きピン及び空きゲートを用い
て構成した予備ゲートは、予備ゲート入力A4と、予備
ゲート入力B5とに与えられた信号を、ΔNl)ゲート
7で論理積をとり、AN+)ゲート7の出力を予備ゲー
ト出力Y6を介して外部へ送出することにより、
Y=A、 and、B
という機能を実行する。したがって入力Δ4、入力B5
及び出力Y6にLSI外部で信号を接続するごとにより
、当Y・備ゲートは論理積の機能をもつゲートとして、
所用の論理修正に用いられる。On the other hand, the spare gate constructed using the empty pins and empty gates of this logic LSI performs the AND operation of the signals given to the spare gate input A4 and the spare gate input B5 at the ΔNl) gate 7, By sending the output of gate 7 to the outside via preliminary gate output Y6, the function Y=A, and, B is executed. Therefore, input Δ4, input B5
By connecting a signal to the output Y6 from outside the LSI, the Y-bit gate functions as a gate with an AND function.
Used for necessary logic correction.
従来の予備ゲート装置は以上のように構成されているの
で、例えば2入力l出力の空きビンを使用して、2入力
l出力の単一の機能しか実現できず、論理修正に柔軟に
対応できないという問題点があった。Since the conventional backup gate device is configured as described above, for example, it can only realize a single function of 2 inputs and 1 output by using an empty bin with 2 inputs and 1 output, and cannot flexibly respond to logic modifications. There was a problem.
この発明は上記のような問題点を解消するためになされ
たもので、LSIのビンを消費せずに複数機能を切替え
られる方法を持ち、限られた空きビンを有効に利用して
、論理修正に柔軟に対応できる予備ゲート装置を得るこ
とを目的とする。This invention was made to solve the above-mentioned problems, and has a method of switching multiple functions without consuming LSI bins, and makes effective use of limited empty bins to correct logic. The purpose is to obtain a spare gate device that can flexibly respond to
この発明に係る予備ゲート装置は、Y備ゲ〜1・12の
論理機能を切換える切換部9と、上記切換部9の切換を
制御するデータを保持するラッチ部10と、上記スキャ
ン入力lから入力されるデータに基づき上記スキャンパ
ス3を介して上記ラッチ部10にデータを書き込む書込
部11とを設けたことを特徴とするものである。The spare gate device according to the present invention includes a switching section 9 for switching the logical functions of Y-bits to 1 and 12, a latch section 10 for holding data for controlling the switching of the switching section 9, and an input from the scan input l. The present invention is characterized in that it is provided with a writing section 11 that writes data to the latch section 10 via the scan path 3 based on the data.
この発明における切換部9は予備ゲート12の機能を切
り換えて出力する。この切換を制御はスキャン入力1が
入力されたデータをスキャンパス3を介してラッチ部1
0に書き込み、このラッチ部に書き込まれたデータに基
づいて行う。この時のラッチ部10へのデータの書き込
みは書込部11が行う。The switching section 9 in this invention switches the function of the spare gate 12 and outputs it. This switching is controlled by sending input data from scan input 1 to latch unit 1 via scan path 3.
0, and the process is performed based on the data written to this latch section. The writing section 11 writes data to the latch section 10 at this time.
以下、この発明の一実施例を図について説明する。なお
、従来技術と同一の構成要素については同一番号を付し
てその説明を省略する。An embodiment of the present invention will be described below with reference to the drawings. Note that the same components as those in the prior art are given the same numbers and their explanations are omitted.
第1図はこの発明の一実施例を示す構成図で、図におい
て、8はORゲート、9はANDゲート7とORゲート
8の出力を選択し結果を予備ゲート出力6に送出する切
換部、IOは該切換部9の選択を指定するスキャン入力
のみを入力とするシフトレジスタで構成されるラッチ部
である。FIG. 1 is a block diagram showing an embodiment of the present invention, in which 8 is an OR gate, 9 is a switching unit that selects the outputs of AND gate 7 and OR gate 8 and sends the result to preliminary gate output 6; IO is a latch section composed of a shift register that receives only a scan input specifying selection of the switching section 9.
また11はラッチ部lOへのデータの書き込みを行う書
込部である。Further, 11 is a writing section that writes data to the latch section IO.
ここにANDゲート7とORゲート8とが組になって予
備ゲート12を構成することになる。Here, the AND gate 7 and the OR gate 8 are combined to form a spare gate 12.
次に動作について説明する。予備ゲートの機能を指定す
るラッチ部10には、あらかじめスキャン入力lからデ
ータを入力し、スキャンパス3を介して、スキャン動作
により論理値“0”又は“l″を誓すき込んでおく。予
備ゲート入力A4と予備ゲート入力B5とに与えられた
信号は、ANDゲート7及びORゲート8に送られ、そ
れぞれ論理積、論理和がつくられる。ANDゲート7の
出力とORゲート8の出力は、切換部9に送られ、機能
指定ラッチ部lOの内容が論理値″0”の時はANDゲ
ート7の出力が、論理値“l″の時は01’?ゲート8
の出力が選択され、予備ゲート出力Y6を介して外部に
送出される。Next, the operation will be explained. Data is inputted in advance from the scan input 1 to the latch unit 10 that specifies the function of the spare gate, and a logical value "0" or "1" is written through the scan path 3 by a scan operation. The signals applied to the preliminary gate input A4 and the preliminary gate input B5 are sent to an AND gate 7 and an OR gate 8, and a logical product and a logical sum are respectively generated. The output of the AND gate 7 and the output of the OR gate 8 are sent to the switching unit 9, and when the content of the function specifying latch unit 1O is a logic value "0", the output of the AND gate 7 is a logic value "1". Is it 01'? gate 8
The output of is selected and sent to the outside via the preliminary gate output Y6.
したがって、当予備ゲートは機能を指定するラッチ部1
0に論理値“0”を書き込むと論理積の機能を持つゲー
トとして、論理値“1′を書き込むと論理和の機能を持
つゲートとして、所有の論理修正に用いられる。Therefore, this spare gate has latch section 1 that specifies the function.
When a logic value "0" is written to 0, the gate functions as a gate with an AND function, and when a logic value "1" is written, it becomes a gate with an OR function, which is used for modifying the owned logic.
この時のラッチ部10へのデータの書き込みは書込部l
lで行う。At this time, data is written to the latch section 10 by the writing section l.
Do it with l.
なお、上記実施例では機能を指定するラッチ部IOが1
bitで選択できる機能が2種類のものを示したが、ラ
ッチ部10を複数bitにしてもよく、上記実施例以上
に選択できる機能を増加させることができる。Note that in the above embodiment, the latch section IO for specifying the function is 1
Although two types of functions are shown that can be selected by bits, the latch section 10 may have a plurality of bits, and the number of functions that can be selected can be increased more than in the above embodiment.
以上のように、この発明によれば、予備ゲートの機能を
切換える切換部と、上記切換部の切換を制御するデータ
を保持するラッチ部と、上記スキャン入力から入力され
るデータに基づき上記スキャンパスを介して上記ラッチ
部にデータを書き込む書込部とを設けたので、LSIの
ピン数を消費することなく予備ゲートの機能を複数に拡
張することができ、限られた空きビン数を最大限に利用
して論理修正に柔軟に対応できる効果がある。As described above, according to the present invention, there is provided a switching section that switches the function of the spare gate, a latch section that holds data that controls switching of the switching section, and the scan path based on the data input from the scan input. Since a writing section is provided to write data to the latch section through the LSI, the function of the spare gate can be expanded to multiple without consuming the number of LSI pins, and the limited number of empty bins can be maximized. It has the effect of being able to respond flexibly to logical modifications by using it.
第1図はこの発明の一実施例を示す構成図、第2図は従
来の予備ゲート装置の構成図である。
図において、■はスキャン入力、2はスキャン出力、3
はスキャンパス、4は予備ゲート入力A、5は予備ゲー
ト入力B、6は予備ゲート出力Y、7はANDゲート、
8はORゲート、9は切換部、10はラッチ部、11は
書込部である。
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 大 岩 増 雄(ばか2名)第22FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional preliminary gate device. In the figure, ■ is the scan input, 2 is the scan output, and 3 is the scan input.
is the scan path, 4 is the spare gate input A, 5 is the spare gate input B, 6 is the spare gate output Y, 7 is the AND gate,
8 is an OR gate, 9 is a switching section, 10 is a latch section, and 11 is a writing section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa (2 idiots) 22nd
Claims (1)
力を出力するスキャンパスと、所定の予備ゲートを有し
、上記論理LSIの論理修正を行う時上記予備ゲートを
用いる予備ゲート装置において、上記予備ゲートの論理
機能を切換える切換部と、上記切換部の切換を制御する
データを保持するラッチ部と、上記スキャン入力から入
力されるデータに基づき上記スキャンパスを介して上記
ラッチ部にデータを書き込む書込部とを設けたことを特
徴とする予備ゲート装置。In the spare gate device, which has a scan path that outputs a scan output when a scan input is input into the logic LSI, and a predetermined spare gate, and uses the spare gate when modifying the logic of the logic LSI, the spare gate is A switching section that switches logical functions, a latch section that holds data that controls switching of the switching section, and a writing section that writes data to the latch section via the scan path based on data input from the scan input. A preliminary gate device characterized by being provided with.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63119616A JPH01289269A (en) | 1988-05-17 | 1988-05-17 | Spare gate device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63119616A JPH01289269A (en) | 1988-05-17 | 1988-05-17 | Spare gate device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01289269A true JPH01289269A (en) | 1989-11-21 |
Family
ID=14765833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63119616A Pending JPH01289269A (en) | 1988-05-17 | 1988-05-17 | Spare gate device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01289269A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008287708A (en) * | 2007-04-19 | 2008-11-27 | Panasonic Corp | Reconfiguration arithmetic circuit |
US9201117B2 (en) | 2013-05-06 | 2015-12-01 | International Business Machines Corporation | Managing redundancy repair using boundary scans |
-
1988
- 1988-05-17 JP JP63119616A patent/JPH01289269A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008287708A (en) * | 2007-04-19 | 2008-11-27 | Panasonic Corp | Reconfiguration arithmetic circuit |
US7996657B2 (en) | 2007-04-19 | 2011-08-09 | Panasonic Corporation | Reconfigurable computing circuit |
US9201117B2 (en) | 2013-05-06 | 2015-12-01 | International Business Machines Corporation | Managing redundancy repair using boundary scans |
US9568549B2 (en) | 2013-05-06 | 2017-02-14 | International Business Machines Corporation | Managing redundancy repair using boundary scans |
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