JPH01211141A - Register pointer circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of a status polling by continuously reading a status register without repeating the setting when the same status register is read with three FFs. CONSTITUTION:When a hardware resetting signal 35 becomes H, all the outputs of respective pointer unit circuits 101-104 become L. Simultaneously, respective outputs of FF 41-43 become L, H and L, and even after the signal 35 is returned to L, these initial states are held. Thereafter, a pointer to select a status register to be read to respective circuits 101-104 by a writing signal 36 is set, next, a reading signal 37 is inputted, a change is absent at the output of an inverter 2 and therefore, transfer gates 11-13 are in an off state and the no change is at the pointer contents of respective circuits 101-104. But, a reading action is stored by the signal 37 with an FF 41. Thereafter, even when the signal 37 is returned to the L, the contents of the pointer are kept as they are, and therefore, next, when the reading action is executed, the same pointer can be read.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a controller used in the periphery of a microprocessor, and particularly to a controller in which a pointer is set for selecting a register to be written or read from among a plurality of registers. The present invention relates to a register pointer circuit that outputs a register selection signal.

[Conventional technology]

FIG. 5 is a circuit diagram showing a conventional example of this type of register pointer circuit, and FIG. 6 is a timing chart thereof.

In this conventional example, the pointer is 4 bits, and each bit of data 31, 32, 33, and 34 is written to four pointer unit circuits 501, 502, 503, and 504, respectively. The pointer unit circuit 501 includes transfer gates 13.14 inverters 15. noah gate 16
a first latch circuit configured with a clocked inverter 17. Transfer gate 18. Inverter 19.
It has a second latch circuit composed of a NOR gate 52, and the input section of the clocked inverter 17 is connected to the NOR gate 1.
Connected to the 1 input terminal of 6. A hardware reset signal 35 is input to the other input terminal of the NOR gate 16 and the other input terminal of the NOR gate 52, and the data 31 is input as a pointer to the first latch circuit via the transfer gate +1, and the data 31 is input to the second latch circuit as a pointer. The circuit passes through two inverters 21 and 22 connected in series on the output side to the decoder +05, and the inverted signal is sent to the inverter 2.
1 to the decoder 105, respectively. Further, the output side of the inverter 22 is connected to a circuit extending from the transfer gate I3 to the transfer gate 12 via a transfer gate 53, and the transfer gate 12 is connected to ground. Other pointer unit circuits 502, 5
03 and 504 also have the same configuration as the pointer unit circuit 501, and input data: ]2, 33, and 34, respectively, and output them to the decoder 105. NOR gate 50 inputs 1, write signal 36 or read signal 37, and connects transfer gate 14 and clocked inverter 17.
It also controls on/off of the transfer gates 13 and 18 via the inverter 2. The Nant gate 54 receives the write signal 36, the output of the inverter 2 via the inverters 8 and 9, and each pointer (
Noah gate I whose input is (corresponding to each data 31 to 34)
Transfer gate 1 is on/off controlled via an inverter 7 using the output of 0 as 3 inputs. The Nandt gate 3 receives two inputs, the output of the inverter 2 via inverters 8 and 9, and the output of the NOR gate 10 via the inverter 5, and outputs the output from the transfer gate 1 via the inverter 4.
-12 on/off control J control. NOR gate 51 uses the outputs of inverters 4 and 7 as two inputs to control on/off of transfer gate 53. These on/
The same off control applies to the other pointer unit circuits 502 to 504. The decoder 105 receives pointers input from each pointer unit circuit 501 to 504,
It performs a logical product with a write signal 36 or a read signal 37 that is input separately, decodes the pointer, and outputs a register selection signal for selecting a target register.

Next, the operation of this conventional example will be explained with reference to FIG.

Here, it is assumed that pointers are set using data 31 to 34 in the zero-numbered register made up of pointer unit circuits 501 to 504.

At time to, hardware reset signal 35 (level "
When the level “H”) is input, the level “L” is input to the first latch circuit.
is latched, the output of the second latch circuit also becomes "L", and all pointers output from the inverter 22 to the decoder 105 become "L". This initial state is maintained by the first and second latch circuits even after the hardware reset signal 35 returns to "L" at time t1.

Next, in order to set the pointer to the register to be selected, a write operation is performed using the write signal 36 at time t2. When the write signal 36 becomes "H" at time t2, the contents of the pointer are already "L", so the zero register is selected, the output of the NOR gate 10 is "H", and the output of the inverter 2 is also "H". Therefore, the output of the inverter becomes "H", and data 31 to 34 are transferred to each pointer unit circuit 50 through transfer gates 11 and 13.
The signals are latched by the first latch circuits 1 to 504, respectively. Both second latch circuits continue to hold "L" and select the zeroth register. Write signal 3 at time t3
6 goes off, transfer gates 11 and 13 close, clocked inverter 17 opens, and the pointer ("H" or "L") of the first latch circuit is loaded and held in the second latch circuit. . Therefore, the pointer output from each inverter 22 also matches the data 31 to 34,
The output of the NOR gate IO is inverted to "L". Next, when the write signal 36 is input again at time t4, the pointer is decoded by the decoder 105, a register selection signal is sent out, and a control register (not shown) is selected. While the write signal 36 is "H", the inverter 2 becomes "H" again and the transfer gate 18 is turned on.
Since the clocked inverter 17 is turned off, the second latch circuit continues to hold the pointer, and since the pointer has a value other than zero to point to the control register, the NOR gate IO continues to be "L". . Therefore, inverter 4 is active, transfer gate 53 is closed, transfer gate 12 is open,
In order to clear the pointer held in the first latch circuit, the ground level "L" is latched in place of the pointer. At time t5, the write signal 36 becomes "L", the clocked inverter 17 opens and "L" is loaded into the second latch circuit, the output of the inverter 22 changes to "L", and the output of the NOR gate IO becomes "L". Return to “H”. In this way, the pointer is reinitialized and at time t
Prepare for the next pointer setting after 5. At time t6, a pointer is set to read the status register, but the operation up to time t7 is the same as the pointer setting from time t2 to time t4. Next, at time t7, the set pointer is read out by the read signal 37.

Here, the pointer selects the status register,
Since the value indicates a value other than zero, the output of the NOR gate 10 is "L", and as in the write operation period, the output of the inverter 4 is "L".
becomes active, and the pointer is cleared and initialized to "L". Therefore, in order to read the same status register, it is necessary to set the same pointer again using the write signal 36 at time 0, and read it at time 0, and in order to continue reading the same status register, this operation It becomes repetitive.

(Problem to be Solved by the Invention) The conventional register pointer circuit described above returns the pointer contents to the initial state each time it is read, so when the same status register is selected continuously. However, the drawback is that the pointer must be set again.

[Means for solving problems]

The register pointer circuit of the present invention sets a pointer when the write signal is turned on in the reset state, outputs the set pointer when the write signal turns off, and then outputs the set pointer by the write signal input again. When a read signal is input after the pointer is reset or set by a write signal, a number of pointer unit circuits equal to the number of pointer bits output while holding the set pointer, and when the read signal is turned on. A first flip-flop that is set and stores its state, and a first flip-flop that is set and stores its state.
A second flip-flop which is set by logical ANDing the output of the flip-flop and the turned-on write signal and resets the output of each pointer unit circuit; and the second
and a decoder that decodes the pointer input from each pointer unit circuit according to a write signal or a read signal and outputs a register selection signal, or When the signal turns on, the pointer is set, and when the write signal turns off, the set pointer is output, and then the set pointer is reset by the write signal input again, or the pointer is set by the write signal. After that, there are a number of pointer unit circuits equal to the number of pointer bits that output the pointer while holding the pointer set when the read signal is input, and a first pointer unit circuit that is set when the read signal is turned on and stores its state. Flip-flop and the first set
A second flip-flop, which is set by logical ANDing the output of the flip-flop and the turned-on write signal, and a pointer input from each pointer unit circuit,
Decodes and outputs according to the write signal or read signal, and when all input pointers are set to zero, outputs an instruction signal instructing to select the register to be selected according to the write signal. means for blocking the input of a write signal to the decoder by the signal output from the first flip-flop set by the read signal; and the output of the second flip-flop set by the read signal or the instruction from the decoder. A gate that inputs one of the signals and outputs a register selection signal of the register to be selected; and a third flip-flop that resets the set first and second flip-flops when the write signal turns off. It has

[For production]

The present invention notes that the register pointer must point to register number zero only during a write operation following a read operation, except when a write operation follows an output operation of a pointer other than zero. Then, the first to third flip-flops are installed, and the pointer is not cleared each time for a read operation, and the fact that a read operation has occurred is stored in the first flip-flop, and then When a write signal is input, in the first aspect of the invention, the contents of the pointer are cleared by the output of the second flip-flop, and in the second aspect of the invention, the write signal input to the decoder is masked and the pointer is output from the decoder. In addition to blocking the output of the second flip-flop, the zeroth register is directly selected by the output of the second flip-flop. After the above write operation is completed, the first and second flip-flops are reset by the third flip-flop.

In this way, when continuously reading the same register, the reading can be performed continuously without repeating the setting of the pointer other than the initial setting.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the register pointer circuit according to the first aspect of the present invention, and FIG. 2 is a timing chart thereof.

In this embodiment, in the conventional circuit described above, an inverter 1 that inputs only the write signal 36 is installed instead of the NOR gate 50, and the NOR gate 51 and the inverter 2 are installed.
2, the circuit leading to the transfer gate 12 is removed, a Nandts gate 6 from which the input of the write signal 36 is removed is provided in place of the Nandts gate 54, and the NOR gate 52 is replaced with a three-person gate 20. Furthermore, a flip-flop 41 that stores read operations, a flip-flop 42 that latches the write operation following the read operation and clears the pointer contents, and a flip-flop that resets the flip-flops 41 and 42 to their initial states after the write operation is completed. A flip-flop 43 and an inverter 29 are added, and the output of the flip-flop 42 is inputted to the three-person gate 20 via the inverter 29 together with the hardware reset signal 35 and the output of the inverter 19. The flip-flop 41 has a NOR gate 23 which has two inputs of the read signal 37 and the output of the NOR gate 24, and a NOR gate 24 which has three inputs of the hardware reset signal 35, the output of the NOR gate 23, and the output of the flip-flop 43. . The flip-flop 42 includes a NOR gate 25 having three inputs: the hardware reset signal 35, the output of the AND-NOR gate 26, and the output of the flip-flop 43, an AND gate having two inputs the output of the flip-flop 41, and the write signal 36, and the It has an AND/NOR gate 26 which is a NOR gate whose two inputs are the output of the AND gate and the output of the NOR gate 25. flip flop 4
3 is made up of two sets of OR/Nant gates 27 and 28, and the OR/Nant gate 27 is a NOR gate whose two inputs are the write signal 36 and the output of the NOR gate 25, and the output of the NOR gate and the output of the OR/Nant gate 28. Consists of a Nantes gate with 2 inputs, or Nantes gate 28
consists of a NOR gate having the write signal 36 and the output of the AND-NOR gate 26 as two inputs, and a NAND gate having the output of the NOR gate and the output of the OR-NAND gate 27 as two inputs.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

Time 1. The hardware reset signal 35 (level “H”)
”) is input, 0 (“L”) is latched in the second latch circuit of each pointer unit circuit 101-104 as in the case of the conventional example described above, and all outputs from the inverter 22 are “L”. ” becomes.

At the same time, the output of the flip-flop 41, the output of the flip-flop 42 to the inverter 29, and the output of the flip-flop 43
The outputs are “L” and “H” respectively.

“L” and time 1. and hardware reset signal 3
These initial states are maintained even after the signal 5 returns to "L". Next, during the period from time t2 to time t6, the pointer is set by the write signal 36, and after the control register is selected and data is written, the pointer contents are initialized again. The operations of the unit circuits 101 to 104 are completely the same as in the conventional example, and the explanation will be omitted. In addition, each flip-flop 41
, 42°43, there is no change in the output. Next, similarly at time t6, each pointer unit circuit 1 is
A pointer for selecting a stator register to be read is set in 01 to 104. At time t7, a read signal 37 is input to read the stator register, but in this case, unlike the conventional example, there is no change in the output of the inverter 2, so transfer gates 11, 12, and 13 are all off, and each pointer Unit circuit 101~
No change occurs in the pointer contents of 104 (Noah Gate 1
There is no change in the output of 6). However, flip-flop 4
1 is set at time t7 by the read signal 37, and the output changes to "H" to memorize the read operation. Read signal 3
Even if 7 returns to "L", there is no change in the output of the inverter 22, and the contents of the pointer continue to point to the previous status register, so if the second read operation is performed at time 8, the result will be at time t7. You can read the same pointer as .

Next, pointer setting for selecting another status register at time t9 will be explained. At this time, as explained in the case of the conventional example, the pointer must select the zero number of the register, so it is necessary to set all the pointers to "L", and when the write signal 36 is input, the NOR gate 10 Since the output of the inverter 4 is "L", the output of the inverter 4 changes to "H" via the Nant gate 3, the transfer gate 12 is opened, "L" (ground) is input to the first latch circuit, and the NOR gate The output of No. 16 changes to "L". On the other hand, since the input from the flip-flop 41 has already changed to "H", the flip-flop 42 is set by the input of the write signal 36, and its output changes to "L". Therefore, the output of the inverter 29 is inverted to "H", and each pointer unit circuit 101 N1
The pointer 04 is forced to “L” through the Noah gate 20.
”.As a result, the output of the NOR gate 10 becomes “H”.
'', the output of the inverter 4 is changed to "L" via the Nant gate 3, the transfer gate 12 is closed and the ground input is cut off, and the transfer gate 11 is opened via the Nant gate 6 and the inverter 7, and the next new Data 31-34 are latched into the first latch circuit.

When the write signal 3δ becomes "L" at the next time t16, a new pointer is output from the second latch circuit and the next status register is selected again in the same way as the previous time.

On the other hand, at the same time, the flip-flop 43 outputs the write signal 36.
is set via the oanant gate 28 when it becomes "L", and its "H" output resets the flip-flops 41 and 42 to return to the initial state, and when the flip-flops 41 and 42 return to their initial states, " L
”.

FIG. 3 is a circuit diagram showing an embodiment of the register pointer circuit according to the second aspect of the present invention, and FIG. 4 is a timing chart thereof.

In this embodiment, a two-person gate 52 similar to the conventional example is installed in place of the three-person gate 20 of the second latch circuit in the embodiment described in item 1 above, and a hardware reset signal 35 and an inverter are connected. The output of the NOR gate 10 is inputted to the two-input NAND gate 48 via the inverter 49 together with the output of the NOR gate 23 of the flip-flop 41, and the output of the NAND gate 48 is input to one of the inverter 5 and the NAND gate 6. Input to input terminal.

Further, the output of the NOR gate 23 is input to the NAND gate 44 along with the write signal 36, and the output of the NAND gate 44 is input to the decoder 106 via the inverter 45, and the flip-flop 41 is set (the output of the NOR gate 23 is is "L"), the input write signal 36 is masked and not transmitted to the decoder 106.Furthermore, a NOR gate 46 and an inverter 47 are installed in series, and the NOR gate 46 receives the output of the inverter 29 and the decoder 106. When the instruction signal 38 instructing the selection of the zero address register, which is the logical product of the write signal 36 and the pointer signal whose all bits are "0", is input, and one of these signals is "H", The zero address register is selected by the output (“H” level) of the inverter 47.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

Similar to the embodiment described in the first section, when the hardware reset signal 35 is input at time 0, the second latch circuit of each pointer unit circuit 301 to 304 is set to 0 ("L").
) is latched, and the output from inverter 22 is all "
At the same time, the input from the flip-flop 42 to the inverter 29 becomes "H", so both of the two inputs of the NOR gate 46 are "L", and the inverter 47
"L" is output from. Further, the output of the flip-flop 41 is held at "H". This initial state is at time 1. It is held even after the hardware reset signal 35 returns to "L". On the other hand, since the NOR gate IO outputs "H", one input of the Nant gate 48 is "L", and therefore its output holds "H". At time t2, the write signal 36 is input to the decoder 106 via the Nant gate 44 and the inverter 45, and in response to this, the write signal 36 is input to the decoder 106.
The output of the inverter 47 is changed to "H" by the zeroth register selection signal 38 outputted from 06 to the NOR gate 46, and the zeroth register is selected. On the other hand, the write signal 36 input to each pointer unit circuit 301 to 301
As a result, data 31 to 3 are set as in the conventional example and the first embodiment.
4 is latched in the first latch circuit, and these pointers are loaded into the second latch circuit at time t3 with the fall of the write signal 36, and at the same time, the instruction signal 38 is also set to "L".
Turn to Further, the output of the Nant gate 48 also changes to "L". Below, selection of control registers from time t4 to time t and each pointer unit circuit 301 to 301 will be described.
Return to the initial state and time 1. The subsequent repeated reading of the status register is exactly the same as in the embodiment described in Section 1, so the explanation will be omitted. However, in the pointer setting at time t6, the decoder 1
The output of the inverter 47 is set to "H" by the instruction signal 38 from 06, and the zero address register is selected.

Next, pointer setting for selecting another status register at time t will be explained.

When the write signal 36 is input at time t9, the flip-flop 41 is already at time 1. The flip-flop 42 is set and the output to the inverter 29 changes to "L" because the input of the read signal 37 at And decoder 10
Since the input of the write signal 36 to 6 is also masked by the Nant gate 44, each pointer unit circuit 3
New data 31~ to the first latch circuits 01~304
34 is latched. At time t16, with the fall of the write signal 36, this new pointer is loaded into the second latch circuit in preparation for the next readout, and at the same time, the flip-flop 43 loads the new pointer into the flip-flops 41 and 42.
is reset and returns to the initial state, as in the embodiment described in Section 1.

(Effects of the Invention) As explained above, in the present invention, the register pointer must point to zero only during the write operation following the read operation, except during the write operation following the write operation of a non-zero pointer. By taking advantage of this fact and using the first to third flip-flops or other means, when reading the same status register, the pointer can be read continuously without repeating settings other than the initial setting. Since the status register can be read by using the CPU, the load on the CPU side can be reduced and the efficiency of status polling can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the register pointer circuit according to the first aspect of the present invention, FIG. 2 is a timing chart thereof, and FIG.
Figure 4 is a circuit diagram of an embodiment of the register pointer circuit according to the second aspect of the present invention, Figure 4 is its timing chart, Figure 5 is a circuit diagram of a conventional register pointer circuit, and Figure 6 is a circuit diagram of the conventional example of the register pointer circuit. This is a timing chart. 1.2, 4, 5, 7, 9, 15, 19, 21, 22, 2
9,45,47.49...Inverter, 3.6,44.48-...Nant Gate, 10.1B, 20,2:1,24.25 ,46.
52------・Noah Gate, 11.12, 13, 14
．． 18----- Transfer gate, 17-...
... Clocked inverter, 2 B ---------and-nor gate, 27.28------ oranth gate, 31.32, 33.34 --- data, 3
5---Hardware reset signal, 36...
...Write signal, 37-...Read signal,
38-----Instruction signal, 41.42.43-----Flip-flop, 10
1.102,103,104,301,302,303
, 304...-Pointer unit circuit, 105, IO2-...Decoder.

Claims (1)

[Claims] 1. Microprocessor peripheral L having multiple registers
In the SI, a pointer for selecting a register to be written or read is set, and a register pointer circuit outputs a register selection signal corresponding to the pointer via a decoder, and the write signal is turned on in a reset state. When the pointer is set and the write signal turns off, the set pointer is output, and then the set pointer is reset by the write signal input again, or the read signal is set after the pointer is set by the write signal. A set of pointer unit circuits, the number of which is equal to the number of pointer bits, that outputs the set pointer while holding it when input, and a first flip-flop that is set when the read signal is turned on and stores its state. being the first
A second flip-flop which is set by logical ANDing the output of the flip-flop and the turned-on write signal and resets the output of each pointer unit circuit; and the second
A register pointer circuit comprising: a third flip-flop that resets a flip-flop; and a decoder that decodes a pointer input from each pointer unit circuit according to a write signal or a read signal and outputs a register selection signal. 2. Microprocessor peripheral L with multiple registers
In SI, a pointer for selecting a register to be written or read is set, and a register pointer circuit outputs a register selection signal corresponding to the pointer via a decoder and a gate, and when a write signal is turned on. After the pointer is set and the write signal is turned off, the set pointer is output, and then the set pointer is reset by the input write signal again, or after the pointer is set by the write signal,
a number of pointer unit circuits equal to the number of pointer bits that output the set pointer while holding it when a read signal is input; and a first flip-flop that is set when the read signal is turned on and stores its state. , the output of the first flip-flop that is set and the turned-on write signal are logically ANDed, and the second flip-flop is set, and the pointer input from each pointer unit circuit is output as a write signal or a read signal. a decoder that decodes and outputs according to a signal, and outputs an instruction signal instructing to select a register to be selected according to a write signal when all input pointers are set to zero; means for blocking the input of a write signal to the decoder by a signal output from the first flip-flop set by the signal; and means for blocking either the output of the second flip-flop set or the instruction signal from the decoder. A register pointer having a gate that inputs and outputs a register selection signal of the register to be selected, and a third flip-flop that resets the set first and second flip-flops when the write signal turns off. circuit.