JPH01289168A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit a regression due to a thermal oxidation of a conducting layer and the generation of bird's beak at the gate of the bottom part of a semiconductor device and to improve the characteristics of the device by a method wherein, after the conducting layer is formed by patterning on a substrate, desired impurity ions are implanted in an inactive part forming region and the substrate is heat-treated. CONSTITUTION:A conducting layer 12 consisting of one layer or more is formed on a substrate 11, on which an active part forming region A and an inactive part forming region B of a semiconductor element are demarcated; the layer 12 is selectively removed to form by patterning and desired impurity ions 13 are selectively implanted in the region B. Then, the substrate 11 is heat-treated to activate the layer 12 and the layer 12 is insulated by a thermal oxide film 14. As a result, while a solid phase diffusion of the impurity ions takes place from the region B to the region A, a dielectric treatment against a regression due to a thermal oxidation of the conducting layer can be executed in a transitional period, during which the concentration of the impurity is increased gradually from the state of a nondoped polycrystalline semiconductor film.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, especially an L for increasing density and integration.
Field-effect transistors (MOSFEs) that constitute SI, etc.
Regarding the method of introducing impurity ions into the 111 layer which becomes the gate electrode of T) and the method of forming the same, it is possible to suppress the regression of the conductive layer due to thermal oxidation and the generation of a gate bird's beak at the bottom of the conductive layer, thereby reducing the asymmetry of the transistor characteristics. The method includes a step of forming a conductive layer consisting of one or more layers on a substrate that defines an active part forming area and a non-active part forming area of a semiconductor element, and selectively forming the conductive layer. a step of selectively implanting desired impurity ions into a non-active portion formation region of the conductive layer; heat treating the substrate to activate the conductive TLM; The field effect transistor is formed by defining a semiconductor substrate of one conductivity type with a field insulating film, and forming an active region and a non-active region of the semiconductor element. a step of selectively forming a conductive layer consisting of one or more layers on the substrate; and a step of selectively implanting a first desired impurity ion into a non-active portion forming region of the conductive layer; heat-treating the substrate to activate the conductive layer and at the same time insulating the conductive layer with a first insulating film; and selectively applying impurity ions of a low concentration and opposite conductivity type to the active region forming region. forming a pair of first opposite conductivity type impurity diffusion regions by implanting a second impurity into the sidewall of the conductive layer;
forming an insulating film, and then selectively implanting high concentration impurity ions of opposite conductivity type into the active part formation region to form a pair of second impurity diffusion regions of opposite conductivity type; , a step of forming a third insulating film on the entire surface of the substrate, and then performing a heat treatment to planarize and activate the impurity diffusion region of the opposite conductivity type of the 1.2. The structure includes a step of selectively opening the insulating film No. 3 to form each electrode.

[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, it relates to a method for manufacturing a semiconductor device.More specifically, the present invention relates to a method for manufacturing a semiconductor device. The present invention relates to a method of introducing impurity ions into a layer.

With the recent increase in speed and integration of LSI, MOSFET
Miniaturization of the gate length (channel length) is required. For this reason, MOSFETs having an impurity diffusion region (drain) such as an LDD structure have been developed;
In the DfN structure, when the source and drain are reversed, an asymmetry problem arises in that the transistor characteristics are different.

Therefore, in order to promote higher integration of LSIs, it is necessary to improve the asymmetry and form a stable MOSFET.

[Conventional technology]

FIG. 4 is an explanatory view of a conventional method for manufacturing a semiconductor device, and the same figure shows a process diagram for forming a pair of impurity diffusion regions that will become the source or drain of a MOSFET.

In the figure, a gate oxide film 3 is formed on a P-type S+ substrate 1 defined by a field insulating film 2, and then a gate oxide film 3 is formed on the entire surface ^
An n+ poly-Si film 4 containing S'S ene and P' ions is formed.

Here, by anisotropic etching using RIE method etc., n9
The poly 5illi4 is selectively removed and patterned to form a gate electrode. Note that 4a and 4b are damaged parts that occur in gate oxidation [3, etc.] due to overetching in anisotropic etching such as RIE, which may deteriorate the dielectric strength between the gate electrode and the p-type Si substrate 1. (
Figure (a)).

Hi
(In order to reduce the concentration to 3%, heat treatment is performed on the n poly-Si film 4 to form thermal oxidation v5.The heat treatment conditions at this time are 950°C for 530 minutes in an oxygen atmosphere.6a, 6b
is what is called a gate bird's beak that occurs at the bottom of the n9 poly 5il14. Further, the gate bird's beaks 6a and 6b are largely generated by doping the polySt film 4 used for the gate electrode with impurity ions at a high concentration, and the oxidation and growth rate thereof is several times higher than that of a non-doped polySt film. Note that ΔW is the retreat distance of the n° poly 5ill, which changes depending on the impurity concentration of the n° poly Si film 4 and the heat treatment conditions (FIG. 4(b)).

Next, we will develop an LD with a low impurity concentration to prevent the short channel effect caused by hot carriers and the like due to the miniaturization of semiconductor devices.
Form D area. LDDSJI area is p-type S1 substrate 1
P° ions 7 are implanted into the n- impurity diffusion regions 8a, 8.
In order to prevent channeling, the ion implantation method is performed by forming an ion implantation angle θ - approximately 7 [
0] and P9 ions 7 are implanted into the p-type Si base w, 1.

Therefore, the gate electrode acts as a shield and generates a shadow portion 9 in the ion implantation direction. As a result, n- impurity diffusion regions 8a and 8b are formed symmetrically under the gate electrode (
There is no overlap (overlap), but asymmetrical (offset).

Note that due to the asymmetry between the n- impurity diffusion regions 8a, 8b and the gate birthbeaks 6a, 6b, when the functions of the source and drain of the MOSFET are exchanged, the transistor characteristics become asymmetrical.

[Problem to be solved by the invention]

By the way, according to the conventional example, as shown in FIG. 4, N4 poly 5iljJ4 containing impurity ions is used as the conductive layer forming the gate electrode, and heat treatment is performed to compensate for the insulation of the damaged parts 4a and 4b due to patterning. An oxide film 5 is formed.

Therefore, a recess distance ΔW of the n poly-Si film 4 occurs, and gate birth beaks 6a and 6b are generated at the bottom thereof. The first problem is that this phenomenon is several times larger than that of non-doped polystH.

In addition, the L
The ion implantation for the DDN region is performed at an angle of about 7 degrees to prevent channeling.

For this reason, the gate electrode becomes a shield and a shadow portion 9 is generated, and the n- impurity diffusion regions 8a, 8b cannot be formed symmetrically under the gate electrode.
and asymmetrically formed n- impurity diffusion regions 8a, 8b.
Naturally, depending on how the internal circuit of the same MO3FET device is used, the source and drain may be reversed.
When the SFET is made to function, there is a second problem in that the rA value voltage V, current amplification factor, etc. change, and the transistor characteristics become asymmetrical, which limits the applicability of semiconductor integrated circuits and the like.

The present invention was created in view of the problems of the conventional example, and suppresses the regression of the conductive layer that becomes the gate electrode due to thermal oxidation and the generation of gate bird's beak at the bottom of the conductive layer, thereby suppressing the MOS.
An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to improve the asymmetry of transistor characteristics of an FET.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention has a principle process diagram as shown in FIG.
As shown in FIG. 2.3, one embodiment of the invention is based on the principle that a semiconductor device consisting of one or more layers is formed on a substrate 11 that defines an active part formation elf region A and a non-active part formation region B of a semiconductor element. 1
12, selectively removing the conductive layer 12 to form a pattern, and then selectively implanting desired impurity ions 13 into the non-active portion forming region B of the conductive layer 112; It is characterized by comprising a step of thermally treating the substrate 11 to activate the conductive layer 12 and insulating the conductive layer 12 with a thermal oxide film 14. The active plate forming area A and the non-active part forming area B of the semiconductor element are defined by the yield insulating film 22.
and then form! a step of selectively forming a conductive layer 23 consisting of one or more layers on the f-substrate 21; and a step of selectively implanting first desired impurity ions 25 into the non-active part forming region B of the conductive layer 23; The substrate 21 is heat-treated to activate the conductor N23, and at the same time, the conductor N23 is activated by the first insulating IFff27. 23; and selectively implanting impurity ions of low concentration and opposite conductivity type into the active plate forming region A to form a pair of first impurity diffusion regions 29a and 29b of opposite conductivity type. , a second insulating film 30 is formed on the side wall of the conductive layer 23, and then impurity ions of high concentration and opposite conductivity type are selectively implanted into the active part forming region A to form a pair of second insulating films 30. A step of forming impurity diffusion regions 32a and 32b of opposite conductivity type, and forming a third insulating film 33 on the entire surface of the substrate 21, and then heat-treating to planarize and form impurity diffusion regions 32a and 32b of opposite conductivity type. activating the impurity diffusion regions 32a and 32b; 2. 3 (7) Insulation WJ, 27, 30.3
The above object is achieved by forming the electrodes S and DG by selectively opening the electrodes S and DG.

[Effect]

According to the principle of the method for manufacturing a semiconductor device of the present invention, after patterning a conductive layer including a non-doped polycrystalline semiconductor film on a substrate, desired impurity ions are implanted into a non-active part forming region, and then the substrate is heat-treated. doing.

Therefore, by performing heat treatment for activating the conductive layer in the active plate forming region and forming a thermal oxide film insulating the conductive layer at the same time, impurity ions are solidified from the non-active part forming area to the active plate forming area. During phase diffusion, insulation treatment can be performed by thermal oxidation of the conductive layer during a transition period in which the impurity concentration gradually increases from the state of a non-doped polycrystalline semiconductor film.

This eliminates the need for direct heat treatment of polycrystalline semiconductor films containing impurity ions, as is the case with conventional methods.
It is possible to suppress the occurrence of gate bird's beak such as ET and the progress of the receding distance of the polycrystalline semiconductor film.

Further, according to the method for forming a field effect transistor of the present invention, by applying the principle of the method for manufacturing a semiconductor device of the present invention, the occurrence of gate bird's beak and the progression of the receding distance of the polycrystalline semiconductor film can be minimized. can be suppressed to a minimum.

Therefore, when ion implanting the LDD region to prevent the short channel effect, that is, when implanting impurity ions into the substrate with an inclination of approximately 7° to form a pair of impurity diffusion regions, the asymmetry of the region is Since the influence of the bird's beak can be ignored after some time, it becomes possible to suppress an increase in asymmetry.

As a result, even when the functions of the source and drain of the MOSFET are reversed, it is possible to suppress the dark voltage V to within an allowable range, and to obtain transistor characteristics that are extremely close to symmetry.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2.3 are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows a process diagram for forming a MOSFET according to a first embodiment of the present invention.

For example, the case of forming an n-channel MO3FET will be explained. In addition, the same figure (ao) is the top view.

In addition, (a,) to (g,) in the same figure are forming process diagrams related to the X+)'+ arrow cross section in the top view (ao), and the top view (a,) to (g2) are , same top view (ao)
, a forming process diagram according to a cross section taken along the arrows Xz and Vg is shown.

In the figure, a p-type Si substrate 21 is heat-treated by selective LOCO3 method or the like to form a field insulating film 22 and define an active plate forming area A and a non-active part forming area B of the semiconductor element. After that, gate oxide film 2 with a film thickness of about 100 [people]
2a is formed, and a non-doped polyester 5tffi of about 500 to 1000 yen is formed on the entire surface of the p-type Si base #l 121 as a conductive film 11i23 which becomes a gate electrode.

Further, the conductor [23] may be provided with a metal or a silicide compound that compensates for contact resistance to form a two-layer structure. The details are described in the second embodiment.

Furthermore, a resist film (not shown) is patterned by photolithography or the like, and this resist film is used as a mask to make the R
PolySil'J23 is etched by anisotropic etching such as IE method.
is selectively removed and the gate electrode is patterned.

Note that CCl410t gas or the like is used as the etching gas (see the same figure (al) (at)).
A resist film 24 is formed on the p-type Si substrate 21 to activate i23.

Note that openings 26 are provided in the resist Wi24 on the non-active portion formation region B of the poly-Si film 23, for example, at intervals of 10 [μm].

Next, using the resist rg, 24 as a mask, impurity ions such as As"" or P1 ions are implanted into the poly 51M423 by an ion implantation method. The ion implantation conditions are a dose of about I x 10''(cm-'') and an implantation energy of about 50 (KeV) (see figure (b)).
+) (bx)).

Next, in order to compensate for the insulation of damaged parts such as gate oxidation 1] 922a that occurred during patterning of the non-doped poly S1 film 23 and to activate the poly S1 film 23, the p-type S1
The substrate 21 is heat-treated. Note that the heat treatment conditions are such that the heating temperature is approximately 1000° C. and the heating time is approximately 30 (minutes) in an oxygen atmosphere. Through this heat treatment, P ions 25 poly 5iWi2 were implanted into the non-active part forming region B.
3 is diffused in the solid phase in the lateral direction, activated, and simultaneously polySi
The area around the film 23 is thermally oxidized to form a SiO film 27.

In this case, as shown in the broken line circle in the figure, the retreat distance ΔW is extremely small compared to the conventional thermal oxidation of n° poly 5ilFJ containing impurities. During the heat treatment, impurity ions are gradually solid-phase diffused from the non-active portion forming region B. The impurity concentration of J23 gradually increases i! It is thought that the surrounding area will be heat treated during the 4th period. This makes it possible to suppress the occurrence of gate bird's beak that causes asymmetric transistor characteristics as in the prior art.

Then L D D jl to prevent short channel effects
For example, by using an ion implantation method, A3 degree ions 28 are implanted at an ion implantation angle θ of approximately 3 to 101 degrees to prevent channeling.

The ion implantation conditions are such that the dose is I x 10'' (
cm-"), and the implantation energy is about 30 (KeV). As a result, a pair of low-concentration n- impurity diffusion regions 29a and 29b are formed (see FIG. 2(dt)).
(dt)).

Next, sidewall insulating films 30 are formed on both sides of the gate electrode 23a by CVD or the like in a self-aligned manner, and then As'' ions 3
1 is implanted into the active part formation region A to form a pair of n impurity diffusion regions 32a and 32b ((e,) in the same figure).
).

Further, a PSG film 33 and the like are formed on the p-type Si substrate 21, and then heat treatment is performed for planarization.

At this time, the n' impurity diffusion regions 32a and 32b are activated at the same time ((r+)(rz) in the figure).

Further, the PSG film 33 is selectively opened to open an electrode window, and then a complementary contact 1Ji 34, an M wiring 35, etc. are formed, and each electrode of source S, drain D, and G) is formed.

Through these formation steps, an n-channel MO3FET can be manufactured.

FIG. 3 is a process diagram for forming a MOSFET according to a second embodiment of the present invention.

Components with the same reference numerals as those in the first embodiment have the same functions, so their explanation will be omitted.

Also, the difference from the first embodiment is that non-doped poly-Si
The point is that the conductive layer 11123 serving as the gate electrode has a two-layer structure of the film 23 and a metal or silicide film 36 for the purpose of contact resistance compensation.

In the figure, a p-type Si substrate 21 is coated with non-doped bo'JS.
The i film 23 and the metal or silicide compound 36 are sequentially laminated to form a two-layer structure, and the conductor 1 is used as the layer 23.

Note that the metal or silicide compound 36 contains W.

Mo, TiO high melting point metals, WSi, MoSi.

A silicide film such as TiSi is used.

Next, heat treatment is performed to activate the conductive tlfj 23 and form a thermal oxide film 27 on the sidewalls of the conductive layer 23. Furthermore, as in the first embodiment, it is possible to suppress the occurrence of gate bird's beak (same as in the first embodiment). Figure (bl) (bri).

Next, as in the first embodiment, As'' ions 28 are implanted into the active part formation region A, and a pair of n- impurity diffusion formation regions 2 are formed.
9a and 29b to prevent short channel effects.
Form a D D region.

As a result, as in the first embodiment, the influence of the gate bird's beak can be almost ignored, and asymmetry can be improved.

Note that the formation steps after (c, ) (c= ) in the same figure are the same as in the first embodiment.

After patterning the conductive layer 23 including the non-doped poly S1 film 23 on the p-type St substrate 21 in this way, P0 ions 25 are implanted into the non-active part forming region B, and then the vaginal substrate 21 is heat-treated. There is.

For this purpose, heat treatment for activating the conductive layer N23 in the active part forming region A and the conductive layer I! Sin@ film 27 film type 7 insulating 23
By doing this at the same time, while P' ions 25 are being solid-phase diffused from the non-active part forming area B to the active part forming area A,
The non-doped poly 5tll123 of the active part forming region A
During the transition period when the P' ion concentration gradually increases from the state of , insulation treatment can be performed by thermal oxidation of the conductive N23.

This eliminates the need for direct heat treatment of a poly-Si film (doped poly-Si film) containing a high concentration of impurity ions as in the conventional method, which prevents the occurrence of gate bird's beak and poly-SiW!
It becomes possible to suppress the progress of the retreat distance ΔW0 of i23.

Therefore, LDD 'fi which prevents short channel effects
When implanting impurity ions in the l region, that is, with an ion implantation angle of approximately 3 to 10'', the P0 ions 25 are converted into p-type St.
Injected into the substrate 21, a pair of n- impurity diffusion regions 29a,
When forming 29b, the influence of the gate bird's beak on the asymmetry of the region can be largely ignored, making it possible to suppress an increase in asymmetry.

As a result, even when the functions of the source and drain of the MOSFET are reversed, it is possible to suppress the threshold voltage V to within an allowable range and to obtain transistor characteristics that are extremely close to symmetry.

[Effects of the Invention] As described above, according to the present invention, the activation treatment of the conductive layer that becomes the gate electrode can be performed to such an extent that the occurrence of gate bird's beak as in the conventional method can be ignored.

Therefore, it is possible to improve the asymmetry of transistor characteristics such as dark value voltage, thereby making it possible to construct a semiconductor integrated circuit with stable dark value voltage, high performance, high density, and high degree of integration.

[Brief explanation of the drawing]

1(a) to 1(c) are principle process diagrams related to a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to 2(g) are
) is a process diagram for forming a MOSFET according to the first embodiment of the present invention, and FIGS. 3(aI) to (Ct) are process diagrams for forming a MOSFET according to a second embodiment of the present invention. Figure 4 (
a) to (C) are diagrams illustrating a method of manufacturing a semiconductor device according to a conventional example. (Explanation of symbols) 1.11.21...p-type S+ substrate (semiconductor substrate or substrate of one conductivity type), 2.22...field insulating film, 3.22a...gate oxide film, 4.・・n0 poly-Si film (poly-Si film containing impurity ions)
membrane), 4a, 4b...damaged parts by tE method, etc., 5.1
4.27...5toxFt (thermal oxide film or first insulating film), 6a, 6b... Gate bird's beak, 7.1
3.25...P゛ion impurity ion), 8a, 8b
, 29a, 29b-n- impurity diffusion region (first impurity diffusion region of opposite conductivity type), 9...Shaded portion, 12.23... Conductive layer or poly-Si film (polycrystalline semiconductor Wi), 24 ...Resist film, 26...Opening, 23a...Gate electrode, 28.31...^S゛ ion (desired impurity ion)
, 24a, 24b...resist film, 30...side wall! @Edge IPJ (second insulating film), 32a
, 32b... n' impurity diffusion region (opposite conductivity type impurity diffusion region), 33... PSGFI (third insulating film), 34... contact compensation layer, 35... curved wiring (metal wiring) ), 36...Metal or silicide compound, A...Active part formation region, B...Inactive part formation region, Hega, He-0...Retreat distance, θ...Ion implantation angle, S, D, G...source, drain, gate (each electrode)
.

Claims (3)

[Claims] (1) A step of forming a conductive layer (12) consisting of one or more layers on a substrate (11) that defines an active part formation region (A) and a non-active part formation region (B) of a semiconductor element, and the conductive layer (12) is selectively removed to form a pattern, and then a non-active part forming region (B) of the conductive layer (12) is formed.
) selectively implanting desired impurity ions (13) into the substrate (11), activating the conductive layer (12) by heat-treating the substrate (11), and converting the conductive layer (12) into a thermal oxide film (14). ) A method for manufacturing a semiconductor device, the method comprising the step of: (2) A semiconductor substrate (21) of one conductivity type is defined by a field insulating film (22) to form an active part forming region (A) and a non-active part forming region (B) of a semiconductor element, and then A step of selectively forming a conductive layer (23) consisting of one or more layers on a substrate (21), and selectively forming a first desired impurity ion (23) in a non-active part formation region (B) of the conductive layer (23).
5) and heat-treating the substrate (21) to form the conductive layer (23).
and simultaneously insulating the conductive layer (23) with a first insulating film (27), and selectively implanting impurity ions of low concentration and opposite conductivity type into the active part forming region (A). and a pair of first impurity diffusion regions of opposite conductivity type (
29a, 29b), and forming a second insulating film (30) on the side wall of the conductive layer (23), and then selectively applying a high concentration and opposite insulating film to the active region (A). Impurity ions of conductivity type are implanted to form a pair of second impurity diffusion regions (32a, 32b) of opposite conductivity type.
), and a third insulating film (33) is formed on the entire surface of the substrate (21), and then heat treatment is performed to flatten and form impurity diffusion regions (32a) of opposite conductivity types to the first and second insulating films.
, 32b), and selectively opening the first, second, and third insulating films (27, 30, 33) to form each electrode (S, D, G). A method for manufacturing a semiconductor device, characterized in that: (3) Manufacturing the semiconductor device according to claim 1 or 2, wherein the conductive layer (12) has a two-layer structure of a metal or silicide compound (36) and a non-doped polycrystalline semiconductor film (23). Method.