JPH01288177A - Special effect circuit for video signal - Google Patents

Abstract

PURPOSE:To vary the size of one frame of mosaic smoothly with inexpensive constitution by supplying a special effect signal and a blanking signal respectively as a reset signal and a sample state holding signal to a sample-and-hold pulse generating circuit through a control circuit. CONSTITUTION:A sample-and-hold circuit(S/H) 12 holds sample state for horizontal blanking period of an input video signal and applies sampling and holding alternately at other video period. The number of times of the sample and holding during one horizontal scanning period is varied in response to the level of a special effect variable signal. The change in the hole time width of the output video signal of the output terminal 17 due to the level change in the special effect variable signal is executed minutely. Since the S/H circuit 12 is an analog circuit, no AD nor DA converter is required. Moreover, since the S/H circuit 12 is held in the sample state at the special effect nonoperation, the input video signal is outputted to the output terminal 17 through the S/H circuit 12 as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a special effect circuit for video signals, and more particularly to a special effect circuit that performs signal processing to give a video signal a so-called mosaic-like special effect different from the original image. .

BACKGROUND OF THE INVENTION FIG. 9 shows a block system diagram of an example of a conventional video signal special effects circuit. -Y) is converted into a digital signal by the AD converter 2 and then supplied to the digital memory 3, where it is sequentially written to the write address designated by the write address designation circuit 4. The write addresses by the write address designating circuit 4 are generated so as to sequentially write digital signals without skipping, as schematically shown in FIG. 10(A) corresponding to the screen.

The stored digital signals written in the digital memory 3 in this way are read out in order according to the read address from the read address designation circuit 5 and supplied to the DA converter 6, where the video signal, which is an AB-log signal, is After being returned to , it is output to the output terminal 7.

Here, the above-mentioned read aretos is performed by, for example, setting the lower two bits of the address to the same value as shown in FIG. 10 (
As shown schematically in B), the same address value is output repeatedly, for example four times,
One pixel is displayed in a rectangular area of 4×4 pixels, as shown by the double frame in B).

Therefore, for example, if the original image based on the video signal input to the input terminal 1 is circular as shown in FIG.
As shown by the shoulder line in 8), a so-called mosaic-like special image is obtained.

Problems to be Solved by the Invention However, when applying special effects to a color video signal, the conventional video signal special effect circuit described above applies a total of three types of signals: a luminance signal and two types of color difference signals. Against AD
Conversion@2, digital memory 3, and DA converter 6 were required separately, resulting in large scale and high cost.

Furthermore, even if an attempt is made to increase the number of mosaic stages, conventional circuits result in digital changes, and in order to reduce the difference in the stepwise changes in the size of each frame of the mosaic, it is necessary to Addressing became extremely complex and difficult to implement.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a special effects circuit for video signals that can smoothly change the size of one frame of a mosaic with an inexpensive configuration.

Means for Solving the Problems FIG. 1 shows a block diagram of the principle of the present invention. In the figure, a video signal from an input terminal 10 is supplied to a sample and hold circuit 12. On the other hand, 13 is an input terminal for a special effect variable signal VCTL, and 14 is a blanking signal (rBLK signal, hereinafter referred to as 1) which is at a high level only during the horizontal blanking period of the video signal and is at a low level during the remaining video period. )
This is the input terminal of The special effect variable signal VCTL is a signal whose level changes in an analog manner depending on the degree of special effect arbitrarily set by the user.

These special effect signals and BLK signals are each supplied to a control circuit 15, where they are converted into a reset signal and a sample state holding signal, and then supplied to a sample and hold pulse generation circuit 16. The sample and hold pulse generation circuit 16 is composed of a variable duty pulse oscillator,
Generates a sample hold pulse (hereinafter also referred to as "S/H pulse") whose only hold time width is variable according to the level of special effect variable No. 64 VCTL, and generates a sample hold pulse (hereinafter also referred to as "Is/H circuit"). Output to 12.

The above is a special effect circuit for a video signal according to claim 1, but the special effect circuit for a video signal according to claim 2 additionally includes a variable filter circuit 11 as a sample and hold circuit. This is provided on the input side of 12.

The variable filter circuit 11 constitutes a low-pass filter only in a video section other than the horizontal blanking period of the input video signal, and allows the input video signal to pass through as is during the horizontal blanking period.

The operational S/H circuit 12 holds the sample state during the horizontal blanking period of the input video signal, and alternately performs the sampling operation and the hold operation during the other video periods. The number of times this sample and hold operation is performed during one horizontal scanning period is varied depending on the level of the special effect variable signal. The hold time width of the output video signal at the output terminal 17 changes minutely due to the level change of the special effect variable signal. Also, S/
)1 Since the circuit 12 is an analog circuit, an AD converter or an OA converter can be made unnecessary.

In addition, since the S/H circuit 12 is held in the sample state when the special effect is not operating, the input video signal is directly transferred to the S/H circuit 12.
The signal passes through the circuit 12 and is output to the output terminal 17.

Furthermore, when the variable filter circuit 11 is provided, P+! of the video section subjected to ripple hold! Since high frequency components such as noise in the image signal portion are attenuated by the variable filter circuit 11, the influence of noise can be reduced.

Embodiment FIG. 2 is a circuit diagram of an embodiment of the present invention, in which the same components as those in FIG. Second
In the figure, the special effect variable signal VCTL is, for example, Ov~
A signal whose level changes in an analog manner within the range of 5■.
First, the operation when <5V, as shown by C in FIG. 3, will be explained.

A resistor Ros capacitor C4 and a resistor R are connected to the input terminal 13.
NP to which the base is connected via the circuit section consisting of a.
The N transistor Qs receives a 5V special effect variable signal Vc.
It is turned on by vL.

On the other hand, a BLK signal as shown by d in FIG. 3 is inputted to the input terminal 14 at a period of 1H (H is a horizontal scanning period) and taken out through the diode Ds.

Since the anode of the diode D4 is approximately at ground level, a signal having the same waveform as the BLK signal signal is taken out from the common connection point of the cathodes of the diodes D4 and Ds, as shown by e in FIG. The voltage is applied to the base of the transistor Q6, and to one input terminal of a two-person NOR circuit, which will be described later.

One end of the capacitor C+ is connected to the common connection point between the resistor R+ and the base of the NPN transistor Q1, and the other end is grounded via the collector and emitter of the transistor Qt.
The variable filter circuit 11 is configured together with the inverter 18 and the inverter 18 . As described above, since a signal having the opposite phase to the signal e shown in FIG. 3 is applied to the base of the transistor Qε, the transistor Q6 is turned off during the horizontal blanking period and turned on during the other video periods.

Therefore, the video signal inputted to the input terminal 10 and shown as a in FIG.
During the erasing period, the transistor Q remains unchanged without being attenuated.
1, and the other video section is connected to the transistor Q.
6 is turned on, a low-pass filter (LPF) consisting of the resistor R1 and the capacitor C, + is configured, so that, for example, 2.6 is turned on.
High frequency components containing noise of 5M H2 or more are attenuated and supplied to the base of transistor Q+. Therefore,
The video signal waveform input to the base of the transistor Q1 is as shown by b in FIG.

In this way, by attenuating the high frequency components of the video signal in the video section, the sample hold circuit 1 described later
Fluctuations due to noise in the level at the time of sample operation can be greatly reduced, and since sample and hold is repeated for each scanning line as in this embodiment, the detection limit for errors in the sample level is increased. Even if the image quality is maintained, sample-level image quality deterioration can be achieved without causing any visual problems.

The connection point between the emitter of the transistor Q+ and the resistor R2 is connected to the NPN transistors Qz, Q*, and the resistors R3 and R via the switch circuit SW+ and the hold capacitor C2.
Output terminal 17 via a rose circuit constituted by 4.
It is connected to the. The switching of the switch circuit SW 1 is controlled by the output pulse (S/H pulse) of the inverter 21 in the sample and hold pulse generation circuit 16 .

Here, the inverter 19, the diodes D+ to Ds, the resistor Rs-RM, the charging/discharging capacitor C3, the PNP transistor Q4-NoR circuit 2o, and the inverter 21 constitute a sample hold pulse generation circuit 16, and the variable duty voltage control It has an oscillator (VCO) configuration. The high level III (sample width) of the S/)l pulse is determined by the capacitance value of the capacitor C8 and the resistance value of the resistor Rs, and the low level period (hold width) is determined by the capacitor C8.
3. Diodes D1 and D2 are used as determined by resistors Ra, R7 and the emitter-collector resistance of PNP transistor Q4.

Although the diode D3 and the resistor R+6 are not necessarily necessary, they play a role in making the hold width change appropriately in response to changes in the special effect variable signal VcTL.

During the horizontal blanking period in which the control signal e from the control circuit 15 is at a high level, the NOR@ path 20
The output signal of the inverter 21 is always at 0-level, so the output signal of the inverter 21 remains at a high level without changing (
oscillation stops).

Therefore, the control signal e has a function as a signal that maintains the sample state at this time.

Furthermore, when the control signal e is at high level, the output signal of one inverter is at low level, and the diode D
Since l is on and D2 is off, N of capacitor C3
The input terminal side of the OR circuit 20 is a resistor Rs and a diode D.
It is set to low level via +. This state is always fixed as long as the control signal e is at high level,
In this sense, the control signal e also functions as a reset signal when oscillation is started by falling to a low level next time.

On the other hand, in the video section where the control signal C is at a low level, the output of the NOR circuit 20 changes depending on the potential at the common connection point of the resistor Rs*R7, the capacitor C3, the collector of the transistor Q4, and one input terminal of the NOR circuit 20. The logic value of the signal changes.

Here, the output signal of the inverter 21 is in a low level period I.
Since the diode D2 is turned on at 2I and the transistor Q4 is turned off by the signal Vc-rL at 5.2, the diode D2. Capacitor C3 is charged via resistors R6 and R7, respectively.

Therefore, the voltage on the input terminal side of the NOR circuit 20 of the capacitor C3 rises according to the charging time constant determined by the 8 values of the resistors R6 and R7 and the capacitor C3, and when it exceeds the threshold of the NOR circuit 20, at that point The output signal of the circuit 20 changes to low level, and therefore the output signal of the inverter 21 changes from low level to high level.

Then, the output signal of the inverter 19 becomes low level, so the diode D1 turns on, and the capacitor C
The charging charge of 8 is passed through the resistor Rs and the diode D1,
It is discharged according to a discharge time constant determined by eight values of C3 and Rs. Therefore, the potential on the input terminal side of the NOR circuit 20 of the capacitor C3 gradually decreases, and when the threshold of the NOR circuit 20 is exceeded, the output signal of the NOR circuit 20 changes from the low level to the high level again. do.

Thereafter, the same operation as above is repeated, and capacitor C3
The potential on the input terminal side of the NOR circuit 20 changes as shown by f in FIG. 3, and the output signal of the inverter 21 changes as shown by q in FIG.

In this way, as shown by 0 in FIG. 3, a pulse train is obtained in which a relatively long time width TsAMPLE and a relatively long time width TsAMPLE, which start from the moment the signal e becomes low level, alternately appear.

This signal Q is applied to the switch circuit SW as an S/l-1 pulse.
During the high level period sAMPLε switch circuit SW+ is turned on and the sample time), the charging of capacitor C2 at this time is applied to the next low level period THOL D switch circuit SWI is turned off. Hold.

As a result, a video signal in which only the video signal portion of the video section is sampled and held is outputted to the output terminal 17, as shown by h in FIG.

Next, the operation when the special effect variable signal Vc T L is <3V as shown by C in FIG. 4 will be explained. Figure 4, 3rd
Signals in the same parts as in the figure are given the same symbols. At this time, the base current flows through the transistor Q4, so the transistor Q4 operates in the active region. As a result, the potential on the input terminal side of the NOR circuit 20 of the capacitor C3 is the same as that of the capacitor C3 and the resistor R during the high level period of the inverter 21.
The point that it decreases with the discharge time constant determined by the 8 values of s is the same as in the case of Fig. 3, but when it increases due to charging, the resistance R6* R
7.i The difference is that the charge rises rapidly according to the charging time constant determined by each part of the capacitor C3 and the emitter-collector resistance of the transistor Q4.

Therefore, the potential on the NOR low-circuit input terminal side of the capacitor Cs changes as shown by f in FIG. It will be shorter than the case shown in the figure. Therefore, the output video signal has a waveform sampled and held at a short sambling period, as shown by h in FIG.

Next, we will explain the operation when the special effect variable (H VCTL is OV as shown by C in FIG. 5. In FIG. 5, signals in the same parts as in FIG. 3 are given the same symbols. Since the transistor Qs is turned off, the signal e is always outputted as a high level signal through the diode D4 as shown by e in FIG. 5, regardless of whether the BLK signal d is input.

This causes the NOR circuit 20 to
The output signal of the inverter 21 is fixed at a low level, and the output signal (S/H pulse) of the inverter 21 is always at a high level as shown by Q in FIG. 5, so the switch circuit S W + is always on.

The output impedance of the emitter follower circuit consisting of the transistor Q+ and the resistor R2 is sufficiently low, and the transistor Qs is always off, so the input video signal a is not attenuated and remains unaffected by the variable filter circuit 11 and the capacitor C2. As shown by h in FIG. 5, the signal is output to the output terminal 17.

In the above explanation, the special effect variable signal VCTL is 5V, 3V.
Although the three cases of V and OV have been explained, this signal Vc T L is continuously set within a range of 5 from ov to a value desired by the user, and is a special effect variable signal. The sampling time width Ts^MPLε and hold time width THOL of the S/H pulse q are determined according to the value of VCTL.
D changes smoothly as shown in FIG.

In FIG. 6, the oscillation stop is caused by the special effect variable signal VCTL.
is the threshold voltage of 0.7V that turns off transistor Q5.
The following is the ending. Furthermore, when VCTL is 0.7V or more, transistor Qs is turned on, transistor Q4 operates in the active region, and the sampling time width T of S/H pulse q is
SAMPLE is constant and hold time [THoL
Only o becomes proportionally longer.

As a result, according to this embodiment, when the video signal of the original image is input to the input terminal 10 as shown in FIG. 11(A), the output video signal of the output terminal 17 is displayed. ) as shown by diagonal lines. In FIG. 11(C), the vertical lines are numbering points (actually invisible), which are usually constant in the same field.

As can be seen by comparing Figure M11 (c) and Figure (8), according to this embodiment, each scanning line is sampled at regular intervals, so processing is performed in the l-direction. Although there is no vertical step, it shows a pseudo vertical step, which is affected by the slope of the boundary line of the original image. Furthermore, in this embodiment, the so-called mosaic-like stepwise change can be made much simpler and smoother than in the past.

The above has explained the luminance signal, but when performing mosaic processing on a color video signal, as shown in Fig. 7,
Mosaic processing is performed on each of the luminance signal Y9 color difference signals (RY) and (BY). In FIG. 7, 23 is a luminance signal input terminal, and 24 and 25 are color difference signal input terminals, respectively.
), (8-Y). Further, 26 is a special effect variable signal VCTL input terminal.

The BLK signal generated by the BLK signal generation circuit 27 by known means based on the horizontal synchronization signal of the luminance signal is supplied to the control circuit and S/H pulse generation circuit 28 together with a special effect variable signal. The control circuit and the S/H pulse generation circuit 28 are connected to the control circuit 15.
The S/H pulse and control signal outputted from this circuit are connected to the LPF and tFs/HD paths 29, 30 and 3.
1, respectively.

LPF and ffS/H [129, 30 and 31 are the second
A circuit section consisting of the variable filter circuit 11 and the S/H circuit 12 shown in the figure outputs a luminance signal, two color difference signals R-Y, which are subjected to special effect video signal processing in parallel to output terminals 32, 33, and 34.
B-Y is output.

In this way, even when the signal processing of this embodiment is applied to color video signals, an extremely simple configuration can be achieved.

FIG. 8 shows another embodiment in which special effect processing is simply performed on a color video signal. In the figure, input terminal 36
The N'r SC color video signal input to the
The Y/C separation circuit 37 separates the signal into a luminance signal Y and a carrier color signal C, and each undergoes noise reduction and other predetermined signal processing by an Ij1 good signal processing circuit 38 and a color signal processing circuit 39, respectively.

The special effect circuit 40 is the special effect circuit of the present invention shown in FIGS. 1 and 2, and performs signal processing for special effects only on the luminance signal from the luminance signal processing circuit 38.

The luminance signal taken out from the special effects circuit 40 and the carrier color signal taken out from the color signal processing circuit 39 are combined in a Korean circuit 41 to form a color video signal, which is then outputted to an output terminal 42.

In this embodiment, no special effect processing is performed on the carrier color signal, but if the number of sample and hold times in a 1H period is about 30 or more, the resolution of the color signal system of the human eye is low, so no special effect processing is applied to the carrier color signal. The fact that this is not applied to the carrier color signal is hardly detected, and it is possible to obtain a special image that is suitable for practical viewing.

Note that when the present invention is applied to a VTR, the input video signal may be either a reproduced video signal or a video signal to be recorded. Further, the variable filter circuit 11 may not necessarily be provided.

Effects of the Invention As described above, according to the present invention, a video signal with a mosaic-like special effect can be obtained with a simpler and cheaper configuration than conventional circuits, and the sampling interval can be changed smoothly. Therefore, it is easy to gradually transition from a normal image to a large mosaic-like special effect image with gentler changes than before, and vice versa. In addition, since noise is reduced by a variable filter circuit, operation is stable with little sample level error, and there is little deterioration in image quality.Furthermore, special effects can be easily changed using only special effect variable signals. Since sample and hold pulses are not generated when special effects are not applied, they are less likely to become a source of interference.Furthermore, since the reset signal of the sample and hold pulse generation circuit and the sample-shaped part holding signal are performed using the same signal, the circuit configuration is simple. It has certain features.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIGS. 3 to 5 are signal waveform diagrams for explaining the operation of FIG. 2, and FIG. 1 and 2 are explanatory diagrams of the relationship between the special effect variable signal and the sample hold pulse, and FIGS. 7 and 8 are block systems showing eight examples of special effect processing for color video signals, respectively. 9 is a block system diagram of an example of a conventional circuit, and FIG.
The figure is a diagram schematically showing an example of the relationship between the write address and the read address in FIG. 9, and FIG. 11 is a diagram showing a comparison of the processed output images of the conventional circuit and the circuit of the present invention for the original image. . 10... Video signal input terminal, 11... Variable filter circuit, 12... Sample hold circuit, 13... Special effect variable signal input terminal, 14-... Blanking signal (BLK signal) input terminal, 15... Control circuit, 16... Sample and hold pulse generation circuit, 17.
...Video signal output terminal. Patent applicant: Victor Japan Co., Ltd. Figure 5 Ov Hi 9 Hi → Ginma 0 -0 (J 't) Φ
, OI = 0. 0 0 Cfu
Φ 啼-01-cFigure 6Figure 8Figure 9Figure 0Figure ■Figure

Claims (2)

[Claims] (1) In a video signal special effects circuit that thins out video information in video sections other than the horizontal blanking period in the time axis direction and outputs a video signal with special effects, an input video signal of the original image is supplied. and a sample-and-hold pulse configured with a variable duty pulse oscillator that generates a sample-and-hold pulse whose only hold time width is variable according to the level of a variable special effect signal from the outside and supplies it to the sample-and-hold circuit. a holding signal for causing the sample-and-hold pulse generating circuit to output a signal for holding the sample-and-hold circuit in a sample state during a horizontal blanking period of the input video signal and when a special effect is not activated, respectively; A special effects circuit for a video signal, comprising a control circuit that outputs a reset signal that resets the sample-and-hold pulse generation circuit every erasing period. (2) The variable filter circuit is configured to constitute a low-pass filter only in a video section other than the horizontal blanking period of the input video signal, and is switched to pass the input video signal as is during the horizontal blanking period. 2. The video signal special effects circuit according to claim 1, wherein the circuit is provided on the input side of the sample and hold circuit.