GB1588188A

GB1588188A - Television receiver

Info

Publication number: GB1588188A
Application number: GB5343777A
Authority: GB
Original assignee: Deutsche ITT Industries GmbH; ITT Industries Inc
Current assignee: TDK Micronas GmbH; ITT Inc
Priority date: 1976-12-23
Filing date: 1977-12-22
Publication date: 1981-04-15
Also published as: ES465380A1; IT1088573B; FR2375774A1; DE2658449A1

Description

(54) IMPROVEMENTS IN AND RELATING TO TELEVISION RECEIVERS (71) We, ITT INDUSTRIES INC, a Corporation organised and existing under the Laws of the State of Delaware, United States of America, of 320 Park Avenue, New York 22, State of New York, United States of America, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a television receiver having the facility of displaying within a minor area of its screen an enlarged version of a portion of an image reproduced from a received programme on a major area of the screen. Television receivers having this facility and using a storage arrangement for the video information of the image section with associated write, read, and changeover switching circuits controlled at least in part by vertical and or horizontal pulses are known from German Published Application (DT-OS) 2,301,065.

In the known television receivers of the above-mentioned kind, the storage arrangement is a storage tube with associated write, read, and change-over switching circuits and the circuits necessary to operate the storage tube, such as horizontal and vertical deflection circuits. Because of the use of a storage tube, the enlarged version can display the instantaneous video information of the image portion as a still image only.

According to the present invention there is provided a television receiver with the ability to display, on its screen, an enlarged version of a selectable portion of the main image, comprising: a first, a second and a third (or additional) analog information store; a source of different sets of clock signals controlling the stores; first means for writing during a field scan into either the first or second stores the information contained in the line portions within the selected image portion; second means for reading out during the same field scan from either the second or the first stores information stored therein during the previous field scan and reproducing that read-out information in an enlarged version at a position on the screen, the third store being used to repeat each read-out line as often as is required to secure the necessary enlargement; and logic means for controlling the operation of the stores, clock signal source, and first and second means.

According to the present invention there is also provided a television receiver with a facility for displaying within a minor area of its screen an enlarged version of a portion of an image reproduced from a received programme on a major area of the screen and comprising: a storage arrangement for the video information of the image portion with associated write, read, and changeover switching circuits controlled at least in part by vertical or horizontal or vertical and horizontal pulses; wherein the storage arrangement comprises two like analog stores constructed on the charge transfer principle whose signal inputs are constantly fed with the composite video signal and whose signal outputs are coupled, respectively, to a first and a second input of a first electronic changeover switch, the signal output of the first changeover switch being coupled to a first signal input of a second electronic changeover switch; wherein the storage arrangement further includes an additional analog store constructed on the charge transfer principle whose signal input is connected to the signal output of the second electronic changeover switch, and whose signal output is coupled to the second signal input of the second electronic changeover switch; wherein the signal output of the second electronic changeover switch is also coupled to the first signal input of a third electronic changeover switch, whose second signal input is constantly fed with the composite video signal and whose signal output is coupled to a video amplifier; and wherein a logic circuit provides signals which are applied at the control inputs of the first, second and third electronic changeover switches, and sets of clock signals which operate the two analog stores and the additional analog stores.

An embodiment of the invention is described below with reference to the accompanying drawings, in which: Figure 1 is a very schematic front view of a television receiver incorporating the aforementioned facility; Figure 2 is a block schematic diagram of a television receiver possessing the aforementioned facility; Figure 3 is a circuit diagram of a preferred store for use in the receiver of Figure 2; Figure 4 is a circuit diagram of a shift register serving as an auxiliary clock signal generator for use in the receiver of Figure 2 for controlling a store as in Figure 3; Figure 5 is a block schematic diagram of a preferred logic circuit as in Figure 3; Figure 6 is a block schematic diagram of a first counting and comparing circuit in the logic circuit of Figure 5; Figure 7 is a block schematic diagram of a second counting and comparing circuit in the logic circuit of Figure 5; Figure 8 is a block schematic diagram of a second gate and frequency-divider circuit in the logic circuit of Figure 5; and Figure 9 is a block schematic diagram of a third gate and frequency-divider circuit in the logic circuit of Figure 5.

Figure 1 shows the result to be obtained on the screen 2 of a television receiver 1, where an image as reproduced from a received programme is displayed on a major area of the screen 2 and that the part of the image appearing in the image section 21, which is arbitrarily movable across the screen 2, is also visible in an enlarged version 22 in a preferably fixed minor area of the screen 2.

Figure 2 shows the block schematic diagram of the television receiver of Fignre 1 shows all units required for a monochrome television set; for the sake of completeness, the circuits commonly contained in any monochrome television set are shown as well. The invention is not, however, limited to monochrome television sets but can also be used in colour television sets.

For simplicity, however, the stages addition ally required in colour television sets are not shown in Fissure 2.

The units in the upper half of Figure 2 (above the chain line), except the unit 29, correspond to those of a conventional television receiver, while the units of the lower half together with the unit 29 are the units additionally provided in accordance with the invention.

The signal path for the reproduced programme consists of the tuner 3, the intermediate-frequency (i-f) amplifier 4 with the i-f stage proper 41 and the following i-f detector 42, the video amplifier 5, and the picture tube 6. Between the i-f stage 41 and the i-f detector 42, the i-f signal for the audio amplifier 9 with the following loudspeaker 10 is taken off. The composite video signal appearing at the output of the i-f detector 42, to which in colour television receivers the colour picture information et cetera is added, is applied not only to the video amplifier 5, but also to the synch separator 78, which generates the horizontal and vertical synch pulses from the composite video signal in known manner.

The horizontal synch pulses synchronize the horizontal deflection stage 7, consisting of the phase or frequency or phase-and-frequency comparator stage 71, the horizontal oscillator 72, and the horizontal output stage 73, with a signal of the same frequency as the horizontal oscillator 72, such as a signal from the horizontal output stage 73, being applied to the phase or frequency or phaseand-frequency comparator stage 71.

The vertical synch pulses synchronize the vertical deflection stage 8, which consists of the vertical oscillator 81 and the vertical output stage 82. The output signals of the vertical output stage 82 and of the horizontal output stage 73, which also generates the high voltage required for the picture tube 6, are applied to the deflection coils of the picture tube.

The signal path for the formation of the enlarged section 22 contains a store 27 consisting of two analog stores 271, 272 and an additional analog store 273, a first electronic changeover switch 26, a second electronic changeover switch 28, and a third electronic changeover switch 29 as well as a logic circuit 30 controlling the store 27 partly directly, partly through shift registers 401, 402 and partly through the electronic changeover switches 26, 28, 29.

Each input 2710, 2720 of the two analog stores 271, 272 is connected to the output of the i-f detector 42, so that the composite video signal is constantly applied to these inputs.

The output 2711 of the first analog store 271 and the output 2721 of the second analog store 272 are coupled to two switch inputs 261, 262 of the first electronic changeover switch 26, whose control input 264 is connected to an output 38 of the logic circuit 30. The output 263 of the first electronic switch 26 is coupled to a first switch input 281 of the second electronic switch 28, whose other switch input 282 is coupled to the output 2731 of the additional analog store 273, while its control input 284 is connected to an output 37 of the logic circuit 30.

A first switch input 291 of the third electronic changover switch 29 is connected to the output 283 of the second electronic changeover switch 28. Its other switch input 292 is connected to the output of the i-f detector 42, and its output 293 to the input of the video amplifier 5, while its control input 294 is connected to an output 39 of the logic circuit 30.

Thus, depending on the position of the three electronic changeover switches 26, 28, 29 either the composite video signal of the reproduced programme or one of the signals contained in the analog stores 271, 272 or in the additional analog store 273 is applied to the video amplifier 5.

The two analog stores 271, 272 are controlled by clock-signal outputs 576, 616 of the logic circuit 30, which generates two different sets of clock signals F1, Fll (readin clock signals) and F2, F12 (read-out clock signals) for this purpose, as will be explained below. The two analog stores 271, 272 are also supplied with the third auxiliary set of clock signals F3, . . ., Fl3, . . ., (shift clock signals) which are generated by shift registers 401, 402 in a manner described below. The additional analog store 273 is clocked by the second set of clock signals F2, F12 through its clock-signal input 2732.

Figure 3 is a circuit diagram of one of the two identical analog stores 271, 272. The circuit is a delay line built on the charge transfer principle. Charge transfer devices include the so-called bucket-brigade devices and charge-coupled devices. The analog store shown in Figure 3 is constructed on the principle of bucket-brigade circuits, which comprise a plurality of like stages each of which consists of a transistor T and a capacitor C between the base terminal and the collector terminal of this transistor and which are so arranged in series that the collector terminal of one transistor is connected to the emitter terminal of the next transistor, with the base terminals of the even-numbered transistors controlled by a first portion of a square-wave or trapezoidal clock signal, and the base terminals of the odd-numbered transistors by a second portion of a square-wave or trapezoidal clock signal. The two portions of the clock signal are equal in frequency and are so associated with one another that the effective pulses of one portion lie in the intervals between the effective pulses of the other portion.

Bucket-bridgade circuits can be constructed both from discrete components and in the form of integrated circuits. The transistors may be either bipolar or fieldeffect transistors; in the latter case, insulatedgate field-effect transistors, specifically MOS field-effect transistors, are particularly advantageous. The analog store shown in Figure 3 consists of such insulated-gate field-effect transistors, which may be either p-channel or n-channel transistors, depend ing on which integrated-circuit construction or which voltage polarity appears to be best suited for the specific application. It is also possible to use enhancement-mode or deple tion-mode field-effect transistors.

Among the transistors shown in Figure 3 are T0, T1, T2, T3, T4 . . . . T25, T2m-4s T2m~3, T2m~2., T2m~l and Too. These transis tors are linked with the associated capacitors C, C in the above-described manner and are connected in series. The even numbered transistors T0, T2, T4s .... T2rn-4, T2m-2s Too have their control electrodes connected to one part F1 of the first clock signal, while the control electrodes of the odd-numbered transistors T1, T3 .... T2m-3, T,,, are connected to the other part F11 of the first clock signal.

Each of the two parts F1, F11 of this set of read-in clock signals consists of a square-wave, equal-frequency, voltage re ferred to ground, with the pulses of one part lying in the interval between the pulses of the other part. Each part of the clock signal has, for instance, a pulse duty factor of 0.5, but it is also possible to choose a different pulse duty factor in such a way that between the pulses of the two parts of the clock signal there are intervals during which both parts are zero.

A composite video signal to be stored is applied to the input 2710 (2720), which is connected to the controllable current path of the input transistor T0. The other end of this current path is connected to one terminal of the input capacitor C0, whose other terminal is grounded. The last transis tor Too serves to terminate the bucket brigade circuit with respect to direct current.

One terminal of the controllable current path of the transistor Too is connected to the control electrode of this transistor.

The above components form, in Figure 3, the first series chain K. Figure 3 also shows parallel chains Q1, Q2, . . . . Qk-i, Qk and a second series chain K1. Connected to each odd-numbered transistor of the first series chain K, (the transistors T1, T3, ....

T2m-0, T,,) is a parallel chain of like stages, namely the parallel chains Q1, Q2 .... Qk~l Ok. No parallel chain is con- nected to the transistor T2m~l, since the latter is not a delay transistor, but a line terminating transistor. Each parallel chain contains the same number of stages n con nected in series to form a bucket brigade circuit.

The control electrodes of the transistors of the same ordinal number n (n = 1, 2 .) of each of the k parallel chains are coupled together and connected to a ter minal to which is applied one of the auxiliary (shift) clock signals F3, .... Thus, the auxiliary clock signal F3,1 is applied to the transistors T1,1, T2,1, .... Tk-l,l, Tk,l of the first parallel-chain stages. The auxiliary clock signal F3,2 is applied to the transistors T12, T2,2, . . . , Tk-i.2, Tk,2 as the second parallel-chain stages. The same is true of the (n-1)th parallel-chain transistors T1,n-ls T2,n1 .... Tk-1,n-1, Tk,n--l. to which the auxiliary clock signal F3,n- 1 is applied, and of the nth parallelchain stages comprising the transistors Tl,n, T2,n .... Tk--l.nr Tk.n, to which the auxiliary clock signal F3,n is applied.

The outputs of the individual parallel chains are coupled to the second series chain Kl, which is substantially identical in construction to the first series chain K. The second series chain K1 contains the transistors T12, T3, T'4 .... T2m-5, T2m-4, T2m-3, T2m-2, T2m-1, T00.

The output of each individual parallel chain is connected to the junction of the controllable current path of a respective oddnumbered transistor and the associated capacitor of the second series chain Kl.

Thus, the output of the parallel chain Q1 is coupled to the capacitor terminal associated with the first odd-numbered transistor; the first odd-numbered transistor of the second series chain Kl, corresponding to the first odd-numbered transistor T1 of the first series chain K, is not needed. The output of the second parallel chain Q2, the transistor T1,, is connected to the junction of the controllable current path of the transistor TlS and its associated capacitor. Likewise, the corresponding outputs of the parallel chains up to and including Qk-l, Qk, are connected to the junctions of the controllable current paths of the odd-numbered transistors up to and including T11rn-1, T'1m-a, and their associated capacitors.

An output transistor TA is controlled from the junction of the controllable current paths of the last-but-one transistor T12rn, and of the last-but-two transistor T'1m2, and its controllable current path is connected between a supply-voltage terminal Ijis and an output 2711, while the transistor Tloo forms the direct-current termination for the second series chain Kl by having its control terminal connected to the controllable current path.

The second series chain K is controlled by the second set of clock signals F2, F12, (the read-out clock signals) which may have the same waveform as that of the first set of clock signals F1, F1 1, (read-in clock signals) but its frequency is lower.

The n auxiliary (shift) clock signals F3,1, F3,2, F,n- 1, F3,n activate the individual parallel chain stages in time sequence as is indicated by the pulse scheme shown on the left of Figure 3, where the individual pulses are shifted in time with respect to each other, with the n pulses of the auxiliary clock signals of each clock period succeeding one another from n to 1, so that information always moves into an empty cell in the chain.

The third (shift) clock-signal generators for the auixiliary (shift) clock signals F3, ....; Fl3, .... are preferably n-stage shift registers 401, 402 each of whose n parallel outputs is connected to the n common terminals of the parallel chains of one of the analog stores 271, 272. These shift registers are operated so that a single stage is set whose information is shifted in the direction from the nth to the first stage under the control of the fourth set of clock signals F4, F14.

These shift registers 401, 402, which, too, are preferably implemented using MOS technology, are shown in Figure 4, only the first two stages and the last two stages being shown in detail, those intermediate ones not shown but indicated by dashed lines being identical. This shift register is a dynamic one which requires two non-overlapping clock signals for operation. The stage shown at the left in Figure 4 is framed by a broken line. This stage includes a first switching transistor 45, which has one end of its controllable current path grounded, and the other end connected to the controllable current path of a second switching transistor 46, which has the free end of its controllable current path connected to the first clocksignal input rail 48.

The controllable current path of a coupling transistor 43 is connected between an input 47 and a gate terminal of the second switching transistor 46, which is also connected through a capacitor 44 to the junction of the two switching transistors 45, 46, which also forms the output of the leftmost stage. The gate terminals of the first switching transistor 45 and of the coupling transistor 43 are connected to a second clock-signal input rail 49.

Successive stages are controlled by the fourth set of clock signal F4, F14 as follows.

The part F4 is applied to the first clocksignal input rail 48 which is also the second clock-signal input rail 491 in the adjacent stages, while the part F'4 is applied to the second clock-signal input rail 49 which is also the first clock-signal input rail 481 of these adjacent stages. In other words, the two parts F4, F'4 of the fourth clock signal are applied to successive stages crosswise interchanged.

The outputs of the stages provide the auxiliary (shift) clock signal F3,n, F3,n- 1, .... F3,2, F3,1.

The operation of the arrangement of Figure 4 is as follows.

It is assumed that a binary state HI, defined by high potential, is applied at the input 47. This HI state passes through the coupling transistor 43, which has been ren dered conductive by the -part F'4 of the clock signal, to the gate terminal of the second switching -transistor 46 and to the capacitor 44, whereby the latter becomes charged. During the next half cycle of the clock signal, when the part F4 of the clock signal is applied to the clock-signal input rail 48, the second switching transistor 46-is on because the capacitor 44 has become charged, and the HI potential reaches the output of the stage uninverted. The output signal, the signal F3,n, for example, assumes the defined value of the amplitude of the clock-signal part F4.

During the -next half cycle of the clock signal, the potential at the output for F3,n is forced to the -LO state, which is defined by a low potential, since the clock signal part F4 applied to the two series-connected switching transistors 45, 46 assumes its LO state, too, thereby turning the switching transistor 45 on and the second switching transistor 46 off. In each stage, a shifted HI or LO state is thus followed by a LO state.

This ensures that the duration of a HI state cannot exceed one half-cycle of a clock signal so that overlapping is automatically avoided.

During the half-cycle of the clock signal, which directly follows the shifting of the HI state and in which a LO state is shifted, the amplitude at the output is not, however, equal to ground potential but, in a way, undefined. It is determined by the ratio of the capacitance C44 of the capacitor 44 to-the node capacitance CA of the subcircuit connected to the output, with the following relation holding to a good approximation: ULO = UH C44/CA, where Ubo is the voltage of the LO state, and UHI is that of the HI state.

A sufficiently low amplitude U is always present since the respective outputs are followed by a corresponding number of parallel-chain stages as shown in Figure 3, which must be supplied with auxiliary clock signals, so the node capacitance CA is large comnared with the capacitance C44.

The amplitude Unto, which is negligible in the invention, oecurs when a HI state was present at the output two half-cycles of the clock signal earlier. In this case, the stillcharged capacitor 44 of the following stage discharges through the coupling transistor 43 back to the -node capacitance CA. This results in the above-mentioned capacitative voltage division in the ratio of C4 I CA. The permissible value of Uto is fixed because the voltage remaining across the capacitor 44 after the charge equalization must be lower than the threshold voltage of the second switching transistor 46. In the next possible LO state, however, -this residual charge completely disappears.

Figure 5 shows a block -schematic diagram of a preferred logic circuit 30, which controls the analog stores 271, 272, the addi tional analog stores 273, the shift registers 401, 402, and the electronic changeover switches 26, 28, 29 in the manner described above.

The logic circuit 30 includes a first counting and comparing circuit 51, by means of which the horizontal position of the image portion 21 can be adjusted. A first input 511 of this counting and comparing circuit 51 is fed, through an input 35.of the logic circuit, with vertical pulses B, which can be, in particular, either the vertical synch pulses or the vertical blanking pulses. A second input 512 is provided, through an input 36 of the logic circuit 30, with horizontal pulses Z, which can be, in particular, either the horizontal synch pulses or the horizontal blanking pulses.

A third input 513 is fed, through an input 31 of the logic circuit 30, with pulses R which serve to shift the image portion 21 on the screen 2 to the right and are generated by a user-operated command generator (not shown) such as an ultrasound remote control unit. These pulses are counted forwards by the counting section of the first counting and comparing circuit 51.

A fourth input 514 is provided, through an input 32 of the logic circuit 30, with pulses L which cause the image portion 21 on the screen 2 to be shifted to the left and are generated by means of the above-mentioned command generator operated by the user. These pulses are counted backwards by the counting section of the first counting and comparing circuit 51. A fifth input 515 is fed with the output signal A of a clock oscillator 52 which is the only clock oscillator in the arrangement and from whose output signal the above-mentioned different sets of clock signals are generated.

A first output 516 provides a signal H whose duration determines the horizontal extent of the image portion 21 in the respective line of a field. A second output 517 provides a pinary signal C which assumes one state when the image portion 21 lies in the left-hand half of the screen, and the other state when the image section 21 lies in the right-hand half.

The clock oscillator 52 triggered by the horizontal pulses Z, its input 521 being connected to the input 36 of the logic circuit 30. Its output 526 is connected to, inter alia, the fifth input 515 of the first counting and comparing circuit 51. The frequency of the output signal of the triggered oscillator 52 must be at least twice that of the highest frequency contained in the luminance signal.

The logic circuit 30 further contains a second counting and comparing circuit 53, with which the viewer can adjust the vertical position of the image portion 21 on the screen 2. A first input 531 of this second counting and comparing circuit 53 is fed with the vertical pulses B through the input 35, and a second input 532 is fed with the horizontal pulses Z through the input 36. A third input 533 is supplied, through an input 33, with pulses U which serve to shift the image section 21 on the screen 2 upwards and can be generated by means of the abovementioned command generator operated by the user. The counting section of the second counting and comparing circuit 53 counts these pulses backwards.

A fourth input 534 is fed, through an input 34, with pulses D which serve to shift the image section 21 downwards, and which can be generated by means of the abovementioned command generator. They are counted forwards by the counting section.

An output 536 provides pulses V whose duration determines the vertical position of the image portion 21 in each field.

The logic circuit 30 further includes a frequency divider 54, whose input 541 is connected to the output 526 of the triggered oscillator 52 and by means of whose divisor k, which is an integer and greater than one, the degree of enlargement, in the horizontal direction, of the enlarged section 22 can be determined. In Figure 5, the divisor k is assumed to be fixed and preset, but it is also possible to make the degree of enlargement selectable by the user, in which case the frequency divider 54 must have a variable ratio. The output 546 of the frequency divider 54 thus provides a signal G whose frequency equals the frequency of the output signal of the triggered oscillator 52 divided by k.

A first counter 55 of the logic circuit 30 determines, in Ic? alia, the vertical position of the enlarged section 22. Its counting input 551 is fed with the horizontal pulses Z through the input 36, and its reset input 550 is fed with the vertical pulses B through the input 35. At its first output 556, pulses N are developed and its second input 612 to the output 546 of the frequency-divider 54. The clock signals F2, Fl2 are developed at outputs 616, 616'.

By means of a first OR-gate 62, a flipflop 63, and a first AND-gate 64, a signal is generated with which the image portion 21 on the screen 2 can be marked. In the case of a colour television receiver, the signal, which appears at an output 40 of the logic circuit 30, can be used directly for colour killing, to be performed in known manner, so that the image portion 21 will appear in black-and-white during the colour-cast.

However, the signal at the output 40 can also be used to generate a signal which encloses the image portion 21 on the screen in a frame of any colour.

A first input 621 of the first OR-gate 62 is connected to the input 34, the down-shift commands D, a second input 622 to the input 33, the up-shift commands U, a third input 623 to the input 32, the left-shift commands L, and a fourth input 624 to the input 31, the right-shift commands R.

The output 626 is connected to an input 631 of the flip-flop 63, whose unstable state, if necessary, may be adjustable in known manner through adjustment of the time constant of an RC network.

The Q output 637 of the flip-flop 63 is coupled to a third input 643 of the first AND-gate 64, whose first input 641 is connected to the first output 516 of the first counting and comparing circuit 51, while its second input 642 is connected to the output 536 of the second counting and comparing circuit 51. The output 646 of the first ANDgate 64 provides the signal applied to the output 40 of the logic circuit 30 and marking the image section 21 on the screen 2.

Finally, the logic circuit 30 includes a second AND-gate 65, whose first input 651 is connected to the output 566 of the second counter 56, and whose second input 652 is coupled to the Q output 636 of the flip-flop 63, so the signal appearing at this Q output and the K-signal are ANDed and appear as a K1-signal at the output 653 which is coupled to an output 39 of the logic circuit.

Thus, the third electronic changeover switch 29 is not operated by the K-signal when the image section 21 on the screen 2 is being shifted, since no meaningful image can appear in the enlarged section 22 during this shifting.

Figure 6 shows a block schematic diagram of one possible embodiment of the first counting and comparing circuit 51. It consists of a first up-down (reversible) counter 5101, first and second up-counters 5102, 5103, a count comparator 5104, a first RS toggle 5105, and first and second NANDgates 5106, 5107. These two NAND-gates connect the right- and left-shift pulses R and L with the vertical pulses B in the manner shown, because the vertical pulses B are applied to one input of each of the NANDgates 5106, 5107 through a common first input 511, the right-shift pulses R are applied to a second input of the NAND-gate 5106 through a third input 513, and the leftshift pulses L are applied to a second input of the NAND-gate 5107 through a fourth input 514.

The reference characters given in brackets designate those terminals to which the unbracketed terminals of Figures 2 and 5 are connected. The same applies to the following figures.

.The output of the first NAND-gate 5106 is coupled to the up-counting-input 5111, and the output of the second NAND-gate 5107 to the down-counting-input 5121, of the first up-down counter 5101. The output 5141 corresponds to any count magnitude lying in the second half of the counter's range of count. The output signal of this output 5141, the C-signal, is applied to a second output terminal 517 and gives the above-mentioned information as to whether the image section 21 is in the left or right half of the screeen 2. When a left- or rightshift command L, R appears, vertical pulses B are, for the duration of this command, fed into either the up-counting or the downcounting input of the up-down counter 5101, thereby changing the registered count.

A counting input 5112 of the first upcounter 5102 is connected to a fifth input 515, and a reset input 5122 to a second input 512. This counter thus counts the individual pulses delivered by the triggered oscillator 52 between the horizontal pulses Z; that is, in each horizontal scan.

Count registrations 5151, 5152 of each of the two counters 5101, 5102 are monitored by a first count-comparing circuit 5104. Thus, whenever the count registration 5151, set by the user through the L or R signal and denoting the left edge of the image portion 21, occurs in the counter 5101, and the count registration 5152, the number of A pulses so far reached in a line in the counter 5102, the output 5144 of the first count-comparing circuit 5104 provides a signal which is applied to the S input of the first RS toggle 5105, which primes one input of the first gate and frequency-divider circuit 57 from its output Q.

A counting input 5113 of a second upcounter 5103 is connected to one of the lower counts 5132 of the first up-counter 5102, while a reset input 5123 of this counter is coupled to the output 5144 of the first count-comparing circuit 5104. The output 5143, corresponding to an upper count is connected to the R input of the first RS toggle 5105, at whose Q output and, con sequently, at the output 516 appears the aforementioned H signal, whose duration, which determines the horizontal position of the image portion 21 per line, is ended by 'the count 5143 which corresponds to the number of picture elements in a line which falls within the image portion 21.

Figure 7 shows a block schematic diagram of one embodiment of the second counting and comparing circuit 53. It contains a second up-down counter 5301, a third up-counter 5302, a fourth up-counter 5303, a second count-comparing circuit 5304, a second RS toggle 5305 and third and fourth NAND-gates 5306, 5307. One input of each of these NAND-gates is again fed with the vertical pulses B through a first input 531. A second input of the NANDgate 5306 is fed with the up-shift commands U through an input 533, and a second input of the NAND-gate 5307 is fed with the down-shift commands D through an input 534. The output of the NAND-gate 5306 is coupled to the up-counting-input 5311, and the output of the NAND-gate 5307 to the down-counting-input 5321 of the up-down counter 5301.

The horizontal pulses Z are applied to a counting input 5312 of the third up-counter 5302 through a second input 532, and the vertical pulses B are applied to a reset input 5322 of this counter. The second count comparing circuit 5304 again monitors the two count registrations 5351, which corresponds to the upper edge of the image portion 21 as set up by the user using U and D signals and 5352 which represents the number of lines following a B pulse, and the signal appearing at its output 5344 is applied to the S input of the second RS toggle 5305, which with its output Q primes a second input of the first gate and frequence-divider circuit 57.

An output 5332, corresponding to a lower count of the third up-counter 5302, is coupled to a counting input 5313 of the fourth up-counter 5303, whose reset input 5323 is connected to the output 5344 of the second count-comparing circuit 5304. The output 5343 of fourth up-counter 5303, corresponding to an upper count, is coupled to the R input of the second RS toggle 5305, at whose Q output and at consequently output 536 the above-mentioned V-signal appears, whose duration, which determines the vertical extent of the image portion 21 per field, is ended by the count 5143. Thus at any time when the signals H, A and V are present at the inputs of the circuit 57 the signals F1 and F11 are produced by which information is put into the stores 271 and 272.

Figure 8 shows a block schematic diagram of one embodiment of the second gate and frequency-divider circuit 58, which generates the fourth clock signal F4, F14 as well as the reset pulse for the third gate and frequency-divider circuit 60. The arrangement contains first, second, and third JK toggles 5801, 5802, 5803, a first inverter stage 5804, third and fourth AND-gates 5805, 5806, a second OR-gate 5807, a fifth AND-gate 5808, a second inverter stage 5809, and a fourth JK toggle 5810.

The clock input of the first JK toggle 5801 is connected to the first output 516 of the first counting and comparing circuit 51 through a first input 581, so the clock pulses applied to it are the H-pulses, which determine the horizontal position of the image portion 21 in each line. These H-pulses are also fed into the clock input of the second JK toggle 5802. The clock input of the third JK toggle 5803 is fed with the horizontal pulses Z through a third input 583 and through the input 36, while the clear inputs 5891, 5892, 5893 of the three JK toggles 5801, 5802, 5803 are connected to the third output 608 of the third gate and frequency-divider circuit 60 via the input 580.

The J and K inputs of the first JK toggle 5801 are connected to the second output 517 of the first counting and comparing circuit 51 through the first inverter stage 5804 and a second input 582 and are thus fed with inverted C-pulses, which contain the information about the position of the image portion 21 in the left or right half of the screen 2. These pulses are also applied in uninverted form to the J and K inputs of the second JK toggle 5802 and to a first input of the third AND-gate 5805 while being fed in inverted form, from the output of the first inverter stage 5804, to a first input of the fourth AND-gate 5806. A first input of the third AND-gate 5805 as well as the J and K inputs of the second JK toggle 5802 are thus connected to the second input 582.

A second input of the third AND-gate 5805 is connected to the Q output of the first JK toggle 5801, and a second input of the fourth AND-gate 5806 is coupled to the Q output of the third JK toggle 5803, whose J and K inputs are connected to the Q output of the second JK toggle 5802.

The output of the third AND-gate 5805 and the output of the fourth AND-gate 5806 are each coupled to one of the two inputs of the second OR-gate 5807, whose output is connected to a first input of the fifth AND-gate 5808, to the clear input 5890 of the fourth JK toggle 5810, and, through the second inverter stage 5809, to a third output 587 of the second gate and frequency-divider circuit 58.

A second input of the fifth AND-gate 5808 is connected to the output 526 of the triggered oscillator 52 through a fourth input 584 and is thus fed with the main clock signal A generated by this oscillator. The J and K inputs of the fourth JK toggle 5810 are jointly connected, via a resistor if necessary, to a positive voltage which must be chosen so that the potential necessary for the higher one of two binary states is applied at the two inputs. The output of the fifth AND-gate 5808 is coupled to the clock input of the fourth JK toggle 5810, so the latter generates, from the main clock signal intermittently appearing at the output of the fifth AND-gate 5808, two signals which are inverse to each other and have one-half the frequency of the main clock signal. These two signals appear at the Q and Q outputs and are applied as the fourth clock signals F4, F14 to the first and second outputs 586, 5861.

Thus, by interconnecting the signals applied at the four inputs 581 . . . 584 and at the reset input 580, the fourth clock signal F4, F14 is generated when the image portion is to be displayed in the enlarged section 22, or to be more exact, when the pulses S, T, produced, respectively, at the first output 606 and at the second output 607 of the third gate and frequency-divider circuit 60, are to be shifted in the shift registers 401, 402, which pulses, in turn, generate the auxiliary clock signals F3, . . . F13, with which the information contained in the respective uppermost row of the analog stores 271 and 272 is shifted transversely.

In the embodiment shown in Figure 8, the four JK toggles 5801, 5802, 5803, 58010 are operated essentially as binary division stages with respect to the applied clock signal, so that other toggles or similar binary division stages may be employed, too.

Figure 9 shows a block schematic diagram of one possible embodiment of the third gate and frequency-divider circuit 60. The circuit consists of a fifth up-counter 6001, a fifth JK toggle 6002, a secondary binary division stage 6003, sixth and seventh ANDgates 6004, 6005, a third inverter stage 6006, eighth, ninth, tenth, eleventh and twelfth AND-gates 6007, 6008, 6009, 6010, 6016, and third and fourth OR-gates 6017, 6018.

A counting input 6011 of the fifth upcounter 6001 and the clock input of the fifth JK toggle 6002 are connected to the outputs 586, 5861 of the second gate and frequencydivider circuit 58 through first and second inputs 601, 6011 and are thus fed with one part F4, F'4 of the fourth clock signal each.

A reset input 6021 of the fifth up-counter 6001 is connected to the second output 587 of the second gate and frequency-divider circuit 58 through a reset input 600 and is thus reset by the output signal of the second inverter stage 5809 (see Figure 8).

The J and K inputs of the fifth JK toggle 6002 are connected in common to an output 6031 of the fifth up-counter 6001, which output corresponds to a lower count. An output 6041 of the fifth up-counter 6001, which output corresponds to an upper, preferably the maximal, count, is connected to an output 608, whereby this output 6041 provides the reset signal for the three JK toggles 5801, 5802, 5803 of Figure 8.

The Q output of the fifth JK toggle 6002 is coupled to the input of the second binary division stage 6303, one output of which is connected to the clear input 6092 of the fifth JK toggle 6002, so this JK toggle is cleared after each fourth pulse appearing at the output 6031.

The Q output of the fifth JK toggle 6002 is also coupled to a first input of the sixth AND-gate 6004, whose second input is connected to the first output 596 of the first binary division stage 59 through a sixth input 605 and is thus fed with the X-signal, which controls the second electronic changeover switch 28.

Finally, the Q output of the fifth JK toggle 6002 is also coupled to a first input of the seventh AND-gate 6005, whose second input is connected to the sixth input 605 through the third inverter stage 6006, whereby the X-signal is applied to this second input of the seventh AND-gate 6005 in inverted form as compared to the signal applied to the second input of the sixth AND-gate 6004.

A first input of the eighth AND-gate 6007 is connected to the first output 556 of the first counter 55 through a fourth input 603, and a second input to the second output 657 of the first counter 55 through a fifth input 604.

The output signals of the sixth to eighth AND-gates 6004, 6005, 6007 and the Vsignal coming from the output 536 of the second counting and comparing circuit 53 and applied through a third input 602 are ANDed in the ninth to twelfth AND-gates 6008, 6009, 6010, 6016. To accomplish this, a first input of the ninth AND-gate 6008 and a first input of the twelfth AND-gate 6016 are connected to the output of the sixth AND-gate 6004; a first input of the tenth AND-gate 6009 and a first input of the eleventh AND-gate 6010 are connected to the output of the seventh AND-gate 6005: a second input of the tenth AND-gate 6009 and a second input of the twelfth AND-gate 6016 are connected to the output of the eighth AND-gate 6007, and a second input of the ninth AND-gate 6008 and a second input of the eleventh AND-gate 6010 are connected to the third input 602.

The output of the ninth AND-gate 60n8 and the output of the tenth AND-gate 6009 are each coupled to one of the two inputs of the third OR-gate 6017, while the output of the eleventh AND-gate 6010 and the output of the twelfth AND-gate 6016 are each coupled to one of the two inputs of the fourth OR-gate 6018. The output of the third OR-gate 6017 is connected to a first output 606, and the output of the fourth OR-gate 6018 is connected to a second output 607. As mentioned above, these two outputs provide the pulses S, T to be shifted in the shift registers 401, 402 by means of the fourth clock signal F4, F'4.

The first gate and frequency-divider circuit 57 consists of an AND-gate with three inputs for interconnecting the signals applied at these three inputs as described above, and of a toggle following this AND-gate and serving to generate two non-overlapping square-wave signals which are inverse to each other and represent the first clock signal F1, F'1.

The fourth gate and frequency-divider circuit 61 is somewhat similar to the first circuit 57. It consists of an AND-gate having two inputs and of a following toggle, so the outputs of the toggle provide two non-overlapping square-wave signals which are inverse to each other and represent the second clock signal F2, F'2.

The first counter 55 is a counter of low capacity corresponding at least to the number k, and can be a ring counter, a chain counter or a Johnson counter, for example, whose input is fed with the horizontal pulses Z. Its output corresponding to the count k is coupled to the count input of an upcounter whose reset input is fed with the vertical pulses B.

This up-counter has two outputs, namely a first lying at a low count and corresponding to the uppermost line of the enlarged section 22, and a second lying at an upper count and corresponding to a lowermost line of the enlarged section 22. The first output is coupled to the S input, and the second output to the R input, of an additional RS toggle whose Q output is coupled to the first input of an additional AND-gate having its second input connected to that output of the above-mentioned counter of low capacity which corresponds to the count k.

The output of this AND-gate is the second output 558 of the first counter 55, which provides the E signal controlling the second change-over switch 28. The Q output of the RS toggle is the third output 557 of the counter 55, and the first output 556 of the counter 55 is connected to a count of the counter of low capacity which corresponds to the value k- 1.

The second counter 56 may be an upcounter whose count input is fed with the output signal (signal G) of the frequencydivider 54. A count being the first as viewed from the count input corresponds to the beginning of the enlarged section 22 in each line, and a corresponding second count to the end of the enlarged section 22 in each line. The output signals corresponding to these two counts are each applied to one input of an additional RS toggle, one output signal of which is connected with the signal.

F of the second output 557 of the first counter by means of an additional ANDgate. The output of this AND-gate provides the K-signal.

To the above description of the operation of the television receiver with respect to the adjustment and reproduction of the enlarged section 22, the following should be added.

During each field of the programme being reproduced, the information contained in the image portion 21 is written into one or the other of the two analog stores 271, 272.

The enlarged section 22 is displayed in a place on the screen 2 fixed by the set manufacturer, for example, in an area near the corner at the lower right. With the type of analog stores used, the invention has the advantage that that part of the programme which is being reproduced in the image section 21 is shown in the enlarged section 22 at the same time, so the image displayed in the enlarged section is not a still image, as is the case in the prior art mentioned by way of introduction.

The enlargement in the vertical direction is effected with the selection of the count k, as mentioned above, while the enlargement in the horizontal direction is achieved by choosing the clock frequency for reading out the contents of the analog stores 271, 272 to be lower than that for writing these contents, i.e., by making the frequency of the first clock signal F1, F'1 higher than that of the second clock signal F2, F12.

The enlargement in the vertical direction is achieved by repeating individual lines k times by oirculation in the additional analog store 273. If, for example, the image section is to be enlarged three times its size in the vertical direction, a line section must be displayed on the screen three times, one line section below the other, the second electronic changeover switch 28 will, during the first reproduction of this line section, be placed in the position 281, in which this line section can be displayed from one of the two analog stores 271, 272. The line section is simultaneously written into the additional analog store 273. After this writing, the second electronic changeover switch 28 is placed in the other position 282, whereby any information read out of the additional analog store 273 during subsequent lines is re-entered into the same store. Thus, if the image section is to be enlarged three times its original size, as mentioned above, each line section will circulate twice in the additional analog store 273.

If bucket-brigade circuits are used for the additional analog store 273, it may be necessary to switch an amplifier into the circulating path to compensate for the attenuation of the bucket-brigade circuit. For clock-pulse suppression in the signal having been read out, the output signals of the stores 271, 272 are advantageously passed through sampleand-old circuits.

WHAT WE CLAIM IS:- 1. A television receiver with the ability to display, on its screen, an enlarged version of a selectable portion of the main image, comprising: a first, a second and a third (or additional) analog information store; a source of different sets of clock signals controlling the stores; first means for writing during a field scan into either the first or second stores the information contained in the line portions within the selected image portion; second means for reading out during the same field scan from either the second or the first stores information stored therein during the previous field scan and reproducing that read-out information in an enlarged version at a position on the screen, the third store being used to repeat each read-out line as often as is required to secure the necessary enlargement; and logic means for controlling the operation of the stores, clock signal source and first and second means.

2. A television receiver with a facility for displaying within a minor area of its screen an enlarged version of a portion of an image reproduced from a received programme on a major area of the screen and comprising: a storage arrangement for video information of the image portion with associated write, read, changeover switching circuits controlled at least in part by vertical, or horizontal, or vertical and horizontal pulses; wherein the storage arrangement comprises two like analog stores constructed on the charge transfer principle whose signal inputs are constantly fed with the composite video signal, and whose signal outputs are coupled, respectively, to a first and second input of a first electronic changeover switch, the signal output of the first changeover switch being coupled to a first signal input of a second electronic changeover switch; wherein the storage arrangement further includes an additional analog store constructed on the charge transfer principle whose signal input is connected to the signal output of the second electronic changeover switch and whose signal output is coupled to the second signal input of the second electronic change over switch; wherein the signal output of -the second electronic changeover switch is also coupled to the first signal input of a third electronic changeover switch whose second signal input is constantly fed with the composite video signal and whose signal output is coupled to a video amplifier; and wherein a logic circuit provides signals which are applied at the control inputs of the first second and third electronic changeover switches, and sets of clock signals which operate the two analog stores and the additional analog store.

3. A television receiver according to claim 1 or 2, wherein the two analog stores are operated by the same sets of clock signals.

4. A television receiver according to claim 1, 2 or 3 wherein each analog store comprises a first series chain of series-connected, like stages which are so operated by a first set of clock signals (read-in clock signals) that in one clock signal phase the even-numbered stages of the store contain an analog signal voltage value, and the oddnumbered stages of the store contain a neutral voltage value, while in the subsequent clock signal phase the odd-numbered stages of the store contain an analog signal voltage value, and the even-numbered stages of the store contain a neutral voltage value; wherein each even-numbered and each odd numbered stage of the store of the first series chain has a parallel chain connected thereto each of which consists of n series-connected stages; wherein the control electrodes of the transistor's like rank of each parallel chain are commoned; wherein the nth stages of the parallel chains are connected to the even-numbered or odd-numbered stages of a second series chain of series-connected, like stages operated by a second set of clock signals (read-out clock signals); and wherein the commoned control electrodes of the n stages of the parallel chains are each operated by a corresponding one out of a set of n auxiliary clock signals (shift clock signals) derived from an auxiliary clock signal generator.

5. A television receiver according to claim 4, wherein the auxiliary clock signal generator for each analog store is an n-stage shift register having its n parallel outputs coupled to the corresponding commoned control electrodes of the parallel chains; wherein one stage in each of the shift registers is set, and an appropriate information signal is shifted in the shift register in the direction from the nth to the first parallel-chain stages under the control of a fourth set of clock signals; and wherein the frequency of the second set of clock signals (read-out clock signals) is lower than that of the first set of clock signals (read-in clock signals).

6. A television receiver according to claim 5, wherein the shift registers are dynamic shift registers built with insulatedgate field-effect transistors of the same conductivity type and driven in the same man

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. If bucket-brigade circuits are used for the additional analog store 273, it may be necessary to switch an amplifier into the circulating path to compensate for the attenuation of the bucket-brigade circuit. For clock-pulse suppression in the signal having been read out, the output signals of the stores 271, 272 are advantageously passed through sampleand-old circuits. WHAT WE CLAIM IS:-

1. A television receiver with the ability to display, on its screen, an enlarged version of a selectable portion of the main image, comprising: a first, a second and a third (or additional) analog information store; a source of different sets of clock signals controlling the stores; first means for writing during a field scan into either the first or second stores the information contained in the line portions within the selected image portion; second means for reading out during the same field scan from either the second or the first stores information stored therein during the previous field scan and reproducing that read-out information in an enlarged version at a position on the screen, the third store being used to repeat each read-out line as often as is required to secure the necessary enlargement; and logic means for controlling the operation of the stores, clock signal source and first and second means.

ner, each stage thereof containing a coupling transistor having one end of its controllable current path connected to the information input, a first switching transistor having one end of its controlled current path grounded, and a second switching transistor as well as a capacitor, the series-connected controllable current paths of the first and second switching transistors being connected between ground and a first clock-signal input the capacitor being connected between the gate terminal of the second switching transistor and the junction of the two switching transistors, which forms the output of the stage, that end of the controllable current path of the coupling transistor not connected to the input being coupled to the gate terminal of the second switching transistor and the gate terminals of the first switching transistor and of the coupling transistor being connected in common to a second clock-signal input; and wherein in the stages, the first and second or second or first clock-signal inputs are alternately fed with one of the two parts of the fourth set of clock signals.

7. A television receiver according to claim 4, 5 or 6, wherein the additional analog store is a bucket-brigade circuit, and that the second set of clock signals (read-out clock signals) serve as the clock signals for this bucket-brigade circuit.

8. A television receiver according to any one of claims 1 to 7, wherein the logic circuit contains the following subcircuits: a) a first counting and comparing circuit for setting the horizontal position of the image portion to be enlarged which circuit has the following inputs: a first input for receiving pulses associated with vertical scanning (B), such as the vertical synch pulses or the vertical blanking pulses; a second input for receiving horizontal pulses associated with horizontal scanning (z), such as the horizontal synch pulses or the horizontal blanking pulses; a third input for receiving pulses (R) generated by a user-operated command generator and serving to shift the image portion to the right, which pulses are counted up or forwards; a fourth input for receiving pulses (L) generated by a user-operated command generator and serving to shift the image portion to the left, which pulses are counted down or backwards; and a fifth input for receiving output signal pulses (A) from a clock generator; b) an oscillator triggered by the horizontal pulses (Z) and used as a clock signal oscillator whose frequency is equal to at least twice the highest frequency contained in the luminance signal; c) a second counting and comparing circuit for setting the vertical position of the image portion to be enlarged which circuit has the following inputs: a first input for receiving pulses associated with vertical scanning (B), such as the vertical synch pulses or the vertical blanking pulses; a second input for receiving pulses associated with horizontal scanning (Z), such as the horizontal synch pulses or the horizontal blanking pulses; a third input for receiving pulses CU) generated by a user-operated command generator and serving to shift the image portion upwards, which pulses are counted down or backwards; and a fourth input for receiving pulses (D) generated by a user-operated command generator and serving to shift the image portion downwards, which pulses are counted up or forwards; d) a frequency divider whose input is connected to the output of the triggered oscillator and which divides by k, an integer greater than one, and determines the degree of enlargement of the enlarged version in the horizontal direction of scan; e) a first counter for establishing the vertical position of the enlarged version having a counting input and a reset input which are fed with the horizontal pulses Q and the vertical pulses (B), respectively, and having a first, a second, and a third output; f) a second counter for establishing the horizontal position of the enlarged version having a counting input connected to the output of the frequency divider and a reset input connected to the second output of the first counter; g) a first gate and frequency-divider circuit serving to generate the first set of clock signals (read-in clock signals) and having a first input connected to the first output of the first counting and comparing circuit, a second input connected to the output of the triggered oscillator and a third input connected to the output of the second counting and comparing circuit; h) a second gate and frequency-divider circuit serving to generate the fourth set of clock signals and having a first input connected to the first output of the first counting and comparing circuit, a second input to the second output of the first counting and comparing circuit, a third input for receiving the horizontal pulses C;Z) and a fourth input connected to the output of the triggered oscillator; i) a first binary division stage having an input for receiving the vertical pulses (B); j) a third gate and frequency-divider circuit serving to generate information signals to be shifted in the shift registers and having a first and a second input connected to outputs of the second gate and frequencydivider circuit, a third input connected to an output of the second counting and comparing circuit, a fourth input connected to the first output of the first counter, a fifth input connected to the second output of the first counter, a sixth input connected to the output of the first binary division stage, and an output connected to a reset input of the second gate and frequency-divider circuit; k) a fourth gate and frequency-divider circuit serving to generate the second set of clock signals and having a first input connected to the output of the frequencydivider, and a second input connected to the output of the second counter; 1) a first OR-gate having a first input for receiving the command pulses (D) for shifting the image portion downwards, a second input for receiving the command pulses (U) for shifting the image portion upwards, a third input for receiving the command pulses (L) for shifting the image portion to the left, and a fourth input for receiving the command pulses (R) for shifting the image portion to the right; m) a flip-flop having an input connected to the output of the first OR-gate; n) a first AND-gate having a first input connected to the output of the first counting and comparing circuit, a second input connected to the output of the second counting and comparing circuit, a third input connected to the Q output of the flip-flop and an output at which is produced a signal for marking the image portion on the screen; and o) a second AND-gate having a first input connected to the output of the second counter, a second input connected to the Q output of the flip-flop and an output at which is produced a signal (K1) controlling the third electronic changeover switch.

9. A television receiver able to display, at a fixed position on its screen, an enlarged version of a selectable portion of the main image, substantially as described with reference to the accompanying drawings.

10. An electrical circuit, for providing a television receiver with the ability to display an enlarged version of a selectable portion of a main image on its screen, the circuit including analog stores for the storage of the video information in the selectable portion, means for writing information into the stores, means for reading information out of the stores and reproducing it on the receiver's screen, clock signal source means, and logic control means for controlling said stores, clock means, writing means and reading means, wherein the logic control means causes video-information in the selectable portion to be written, during a given field scan, into an empty one of the stores and, during the same frame, causes videoinformation written into another store during the previous frame to be read out and reproduced in an enlarged version at a position on the screen, the clock signals causing movement of the video-information into, through, and out of the stores at suitable rates, and each line portion read out being circulated in a further store as often as is need to effect the necessary enlargement.