JPH01286653A - Flow control system - Google Patents

Abstract

PURPOSE:To efficiently execute the data transmission control by stopping and releasing a transmitting clock in accordance with the processing of the opponent side data. CONSTITUTION:An its own station side device 15 converts serial data RD received from an opponent side device 14 to parallel data by an SIO 2 and transfers them to a data buffer 3 by the instruction of a DMA control part 5. When the control part 5 completes the DMA processing, the part outputs a signal EOP 20, and thus, a control circuit 4 stops a transmitting clock ST17. During this, the processing of the receiving data is executed by an MPU 6, after the processing, a signal EN 22 is sent to the control circuit 4, the stoppage of the ST17 is released and the ST 17 is sent to the device 14 again. When a mark detecting circuit 1 detects the mark condition, the ST 17 is stopped, and the MPU 6 processes the data transferred by the DMA. After the processing is completed, the ST 17 is oscillated by the EN22 again.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention uses an isochronous method (in which a transmission clock generated by a local device is looped back by a counterpart device and becomes a reception clock of the local device). The present invention relates to a flow control method suitable for use in an asynchronous data transmission system (a method in which a clock is transmitted together with data).

(Prior Art) In conventional data transmission systems, when the interface speed between devices is low, flow control means using XON/X0FF codes, or flow control means that reduces the amount of transfer or lengthens the interval of transfer time. etc. were used.

(ynit to be solved by the invention) However, in the conventional transmission control means described above, when performing high-speed data transmission such as image transmission, for example, the amount of transmission until the control signal of XON/X0FF arrives is limited. It is necessary to estimate and determine the transfer threshold, and the processing speed is low, so it is not possible to increase the amount of transfer at one time.
Various inconveniences have occurred, such as difficulty in controlling a single character when using DMA.

This invention detects that there is no more data arriving from the other party's device, causes an interrupt to the local microprocessor, and at the same time stops the transmission clock that is being supplied to the other party's device. stop the data transfer, and in the meantime,
It is an object of the present invention to provide a flow control method that realizes efficient data transmission control by allowing a local microprocessor to efficiently process data.

[Structure of the Invention] (Means and Effects for Solving the Problems) An outline of a device that realizes the flow control method according to the present invention is shown in FIGS. 1 and 2.
This will be explained using figures.

The local device 15 converts the serial data (RD) received from the other device 14 into parallel data using 5IO2, and transfers it to the data buffer 3 according to a command from the DMA controller 5. When the DMA controller 5 completes the DMA processing, it sends a DMA service end signal (
EOP) 20 is output. In response to this, the clock control circuit 4 stops the transmission clock (ST) 17. During this time, the microprocessor (MPU) 8 processes the received data, and upon completion of the data processing, sends an enable signal (EN) 22 to the clock control circuit 4 to release the stoppage of the transmission clock (ST) 17 and send it to the other party. The transmission clock (ST) 17 is sent to the side device 14 again.

Furthermore, even when the mark detection circuit l detects a mark state, the clock control circuit 4 controls the transmission clock (
ST) 17 is stopped, and the microprocessor (MPU) 6 processes the data transferred by DMA. Then, upon completion of data processing, the transmission clock (ST) 17 is caused to oscillate again by the enable signal (EN) 22. The mark detection circuit l sets the enable signal (
This is when received data (RD) 23 is received for the first time after the occurrence of EN) 22.

By using the flow control means using lock control as described above, it is possible to control the transmission of the other station from the own station during large-capacity transmission and reception such as image transfer, so there is no buffer overflow and processing The load can be reduced.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the entire system targeted by the present invention.

In FIG. 1, 14 is the other party's device, 15 is the local device, 16 is the reception clock (RT) of the local device 15, and 17 is the receiving clock (RT) of the local device 15.
is the same transmission clock (ST). The partner device 14 operates in synchronization with the transmission clock (ST) 17 of the local device 115, and returns that clock as the reception clock (RT) 1B of the local device 15. The local device 15 has a built-in clock control circuit 4, and transmits a transmission clock (ST) 17 according to a clock control signal (EN/DIS) to be described later.
Control the output.

FIG. 2 is a block diagram showing the internal configuration of the local device 15 according to an embodiment of the present invention.

In the figure, ■ is a mark detection circuit, and the received data (RD)
23 is in a marked state.

2 is an SIO (Serial I10) which converts serial data into parallel data and passes it to the data buffer memory 3. 3 is a data buffer memory; 5 is a data buffer memory;
The received data obtained via 102 is stored.

4 is a clock control circuit, which receives a clock control signal (D
IS, EN) Controls the transmission clock (ST) 17 sent to the other party's device 14 in accordance with 21.22. 5 is D
MA controller (DIrect Memory Ac
cessController) and executes 5 DMA instructions.
It is sent to I02 and data buffer memory 3. A microprocessor (MPU) B processes data stored in the data buffer memory 3. Further, upon completion of processing, an enable signal (EN) 22 is sent to the clock control circuit 4. Reference numeral 19 is an interrupt signal (INT) output from the mark detection circuit l, and the received data (RD
)23 is output when it becomes a mark state. 20 is DMA
This is a DMA service end signal (EOP) output from the controller 5, indicating that the DMA service has ended. 21 is a disable signal (DIS) obtained through an OR gate (OR), and serves as a control signal for stopping the clock output of the clock control circuit 4. 2
2 is an enable signal (EN) that is output when the microprocessor (MPU) 6 completes processing, and serves as a control signal that prompts the clock control circuit 4 to output a clock. 2
3 is received data (RD), and when there is no data, it is in a marked state.

FIG. 3 is a block diagram showing the configuration of the mark detection circuit l.

In the figure, numeral 7 is a register in which a setting value for mark detection from a microprocessor (MPU) 8 is set. 8 is a counter that generates an interrupt signal (INT) 19 when the mark state is detected by the value set in the register 7.

FIG. 4 is a block diagram showing the configuration of the clock control circuit 4. As shown in FIG.

In the figure, IO is a synchronization flip-flop for outputting a signal (DIS) 21 for disabling the transmission clock (ST) 17 in synchronization with the clock (CLK).

11 is a flip-flop that outputs a signal (EN) 22 for enabling the transmission clock (ST) 17 in synchronization with the clock (CLK).

12 is a clock (which is the basis of the transmission clock (ST) 17)
CLK). Reference numeral 13 denotes a clock control gate that controls the output of a transmission clock (ST) 17 to be transmitted to the other party's device 14.

FIG. 5 is a time chart showing the states of various signals in the above embodiment.

Enable signal (EN) 22 is transmission clock (ST) 1
Microprocessor (MPU) to start sending out 7
This is the trigger signal from 6. Disable signal (Dis
)21 is a control signal output from the OR game (OR) for stopping the transmission clock (ST) 17. The enable (ENABLE) control signal 24 is a signal generated by ANDing the disable signal (DIS) 21 and the enable signal (EN) 22, and only when this signal is enabled (high level), the transmission clock (ST) 17
is output. The data reception (RD) detection signal 25 is a signal for detecting that the first character of data has arrived. The transmission clock (ST) 17 is a clock that synchronizes the operation of the partner device 14.

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 to 5.

First, the operation of the entire system will be explained using FIG.

While the local unit ft15 is processing data from the other party's device 14, the transmission clock (ST) 17 sent by the local device 15 is stopped. Along with this, the other party's device 1
4 stops operation because the clock supply is no longer available.

As a result, data no longer comes to the local device 14 from the other device 15.

When the transmission of the transmission clock (ST) 17 is restarted after the processing of the local device 14 is completed, data starts coming from the other device 14.

Then, once a certain amount of data has been accumulated, the transmit clock (
ST) 17 is stopped and the received data is processed.

Repeat these actions.

The specific operation at this time will be explained using FIG. 2.

Received data (RD) 2 sent from the other party's device 14
3 is input to 5I02, serial-to-parallel converted, and then transferred to data memory buffer 3 under the control of DMA controller 5.

After the DMA service ends, the DMA controller 5
An end of service signal (EOP) 20 is generated.

Accordingly, the clock control circuit 4 outputs the transmission clock 5T17.
Stop outputting.

When microprocessor B completes data processing, microprocessor B sends an enable signal (EN) 2.
2 is output, the same signal is sent to the clock control circuit 4, and the clock control circuit 4 outputs the transmission clock (ST) 1 again.
7 outputs.

Furthermore, when the received data (RD) 23 becomes marked, the mark detection circuit 1 operates and generates an interrupt signal (INT) 19. When an interrupt occurs due to the interrupt signal (INT) 19, the clock control circuit 4 transmits the transmission clock (ST) 17.
stop. And microprocessor B is idle (
IDLE) state and stops processing the data. Thereafter, when the resetting of the microprocessor 6 is completed and data can be received at any time, the microprocessor 6 outputs an enable signal (EN) 22. As a result, the clock control circuit 4 starts outputting the transmission clock (ST) 17. Then, when the mark state of the received data (RD) 23 is released and the first data arrives, the mark detection circuit 1 cancels the interrupt signal (INT) 19. This causes the microprocessor 6 to start processing the data.

Next, the operation of the mark detection circuit 1 will be explained using FIG.

A setting value for mark state detection is inputted into the register 7 from the microprocessor 6. The initial value of the counter 8 is set based on this set value. Counter 8 receives received data (
RD) 23 is not in the mark state, that is, at low level (L
OW), the low level data causes a reset. Also, when it becomes a mark state,
There is no low level data in the received data (RD) 23, and the counter 8 is no longer reset. Then, when the mark state is counted until the counter value reaches a predetermined maximum value (MAX), an interrupt signal (INT) 19 is generated.

Next, the operation of the clock control circuit 4 will be explained using FIGS. 4 and 5.

First, in FIG. 5, when the microprocessor 6 generates an enable signal (EN) 22, the flip-flop 11 shown in FIG. 4 generates a rising edge of the enable control signal 24 shown in FIG. Next, the interrupt signal (INT
) 19 or the DMA service end signal (EOP) 20, the disable signal (Dis) 21 in FIG.
falls, the synchronizing flip-flop lO of FIG.
The output of the input signal goes to a low level (LOW) state, and the flip-flop 11 generates the falling portion of the enable control signal 24 in FIG. Since this enable control signal 24 and the clock signal (CLK) from the clock generator 12 are input to the clock control gate 13 in FIG. 4, the output transmission clock (ST) 17 has a waveform output as shown in FIG. state. Then, the disable signal (DIS) 21 rises again in response to the signal 25 detecting that the mark state of the received data (RD) has been released, and returns to the original state.

With the device configuration having the transmission clock control function of the embodiment described above, the transmission of the other device 14 can be controlled by the local device 15 in large-capacity transmission and reception such as image transfer. Additionally, there is no buffer overflow, and the processing load can be reduced.

[Effects of the Invention] As detailed above, according to the flow control method of the present invention,
In a data transmission system, the transmission clock generated by the local device is looped back by the other device and becomes the reception clock.
A configuration in which the local device has a clock control means that stops the transmission clock while processing data from the other device and releases the suspension of the transmission clock when the local device finishes processing. By doing so, it is possible to control the transmission of the other station from the own station in large-capacity transmission and reception such as image transfer, thereby preventing buffer overflow and reducing the processing load.

[Brief explanation of the drawing]

1 to 5 are for explaining one embodiment of the present invention, respectively. FIG. 1 is a block diagram showing the configuration of the entire system targeted by the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. A block diagram showing the internal configuration of the local device 15 according to the embodiment,
FIG. 3 is a block diagram showing the configuration of the mark detection circuit l according to the same embodiment, FIG. 4 is a block diagram showing the configuration of the clock control circuit 4 according to the same embodiment, and FIG. 5 is a block diagram showing the signal state of each part according to the same embodiment. FIG. 1-=v-re detection circuit, 2-8 IO (Serial
l10), 3...Data buffer, 4...Clock control circuit, 5-DMA:ff controller (Direc
tMemory Access Controller)
, 8-Phycroprocessor (MPU), 7... Register, 8... Counter, to, tt... Flip-flop, 12... Clock generator, 13... Clock control gate, 14... - Opposite device, 15... Local device, 1B... Reception clock CRT), 17...
・Same transmission clock (ST), 19... interrupt signal (I
NT), 20...DMA service end signal (EOP)
, 21...disable signal (Dis), 22...
Enable signal (EN), 23... Received data (RD
), 24... Enable control signal. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] A data transmission system in which a transmission clock generated by a local device is looped back by the other device to become a reception clock,
The local device has a clock control means that stops the transmission clock while processing data from the other device, and releases the suspension of the transmission clock when the local device finishes processing. A flow control method characterized by: