JPH01286030A - Information processor - Google Patents

Abstract

PURPOSE:To realize the processing of a composite instruction without preparing a processing sequence for the composite instruction by decomposing the composite instruction to the instruction to execute plural fundamental processings and supplying it to an instruction decoding unit. CONSTITUTION:A composite instruction control circuit 3 is composed of a composite instruction detecting circuit 31 and a counter 32. A detecting circuit 31 detects that an instruction in an instruction register 2 is the composite instruction and the number of decomposing the instruction is set to the counter 32. The composite instruction control circuit 3 holes the contents of the instruction register 2 through a control line 301 at the time of the composite instruction and suppresses the taking-out of the succeeding instruction. An instruction decomposing decoder 4 decomposes from the contents of the register 2 and the contents of the counter 32 to plural instructions. An instruction selector 5 selects the decomposed instruction outputted through a signal line 401 and sends it to an instruction decoding unit 6. The unit 6 decodes the instruction, sends it to an instruction execution unit 7 and executes it.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing device.

(Prior Art) Conventional information processing devices decode individual instructions and perform individual processing for each instruction. That is, an instruction fetched into an instruction register from an instruction fetch unit is decoded by an instruction decoding unit that generates a processing sequence corresponding to each instruction, and then executed by an instruction processing unit.

(Problem to be Solved by the Invention) The conventional information processing device described above requires an instruction decoding unit that generates a processing sequence in response to each instruction. There are some instructions that can be shared with other instructions, and there are also compound instructions that can be realized by combining multiple other instructions (for example, load and store instructions for multiple registers, arithmetic instructions that can be broken down into four arithmetic operations, etc.). Possibly, generating separate instruction processing sequences for such complex instructions complicates the instruction decoding unit, increasing the amount of hardware, and increases circuit delay as the circuit becomes more complex. However, this will reduce the performance of the device.

In response to the above problems, in recent years the complexity of hardware has been limited by reducing the number of instructions that can be implemented by combining other basic instructions, such as compound instructions, and this has reduced circuit delay. Information processing devices using the concept of reduced instruction set (RlsC) are becoming available in order to reduce the size and improve the performance of information processing devices. However, RISC computers also have drawbacks, such as a decrease in descriptive performance due to the limited number of types of instructions, an increase in software load, and an increase in program size.

(Means for Solving the Problems) An information processing device of the present invention includes: a detection means for detecting that an instruction in an instruction register is a compound instruction that can realize the same processing by combining other instructions; and the detection means. A disassembly means that disassembles an instruction detected as a compound instruction into multiple instructions that implement the same process, and usually selects an instruction in the instruction register, and selects the disassembled instruction based on the detection output of the detection means. and has selection means for outputting to the instruction decoding means.

(Operation) Therefore, processing of compound instructions can be realized without having a circuit for generating a processing sequence for compound instructions.
The structure of the instruction decoding unit is simplified, the amount of hardware is limited, and the circuit delay is reduced.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of an information processing apparatus of the present invention.

The instruction fetching unit 1 fetches an instruction to be executed from a main memory (not shown) via a signal line 101 and stores it in an instruction register 2. The compound instruction control circuit 3 includes a compound instruction detection circuit 31 and a counter 32, and has a signal line 20.
The compound instruction detection circuit 31 detects that the instruction in the instruction register z supplied through the instruction register z is a compound instruction that can realize the same processing by combining other instructions, and also records the number of instruction decompositions in the counter 32. set. Furthermore, the compound instruction control circuit 3 holds the contents of the instruction register 2 via the control line 301 for compound instructions, and suppresses the fetching of subsequent instructions. The instruction disassembly decoder 4 includes a complex instruction detection circuit 31
When a compound instruction is detected, it is decomposed into a plurality of instructions that implement the same process based on the contents of the instruction register 2 and the contents of the counter 32 supplied via the signal line 303. The instruction selector 5 normally selects the instruction held in the instruction register 2 that is supplied via the signal line 201, and the signal line 3 indicates that the compound instruction detection circuit 31 has detected a compound instruction.
02, the disassembled instruction output via the signal line 401 is selected and sent to the instruction decoding unit 6 via the signal line 501. The instruction decoding unit 6 has a signal line 50
1 decodes the command sent by signal line 1i01
The instruction is sent to the instruction execution unit 7, and the instruction is executed.

Note that the counter 32 is decremented each time a disassembled instruction is sent to the instruction decoding unit 6. Completion of the instruction disassembly process is detected when the counter 32 becomes 0, the holding of the instruction register 2 is released via the control line 301, the instruction selector 5 selects the contents of the instruction register 2, and the signal line 501.

〔Effect of the invention〕

As explained above, the present invention decomposes a compound instruction in which the same process can be realized by a plurality of other instructions into instructions that perform a plurality of basic processes, and supplies the instructions to an instruction decoding unit. Accordingly, processing of the compound instruction can be realized without having a circuit that generates a processing sequence for the compound instruction, thereby simplifying the structure of the instruction decoding unit and reducing the amount of hardware. In addition, by making the structure M-single, circuit delay can be reduced and performance can be improved.
On the other hand, it is possible to add more types of instructions with the addition of less hardware, which improves the writeability of the program, reduces the software load, and reduces the size that the program occupies in the main memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention. DESCRIPTION OF SYMBOLS 1... Instruction fetch unit, 2... Instruction register, 3... Complex instruction control circuit, 31-... Complex instruction detection circuit, 32-... Counter, 4... Instruction disassembly decoder, 5... - Instruction selector, 6... Instruction decoding unit, 7... Instruction execution unit. Patent applicant Kofu NEC Co., Ltd.

Claims (1)

[Claims] 1. In an information processing device, detecting means for detecting that an instruction in an instruction register is a compound instruction that can realize the same processing by combining other instructions; A disassembly means that disassembles an instruction detected to be a compound instruction into multiple instructions that perform the same process; An information processing device comprising a selection means for selecting an instruction and outputting the selected instruction to an instruction decoding means.