JPH01285878A - Logical circuit tester - Google Patents

Abstract

PURPOSE:To perform wiring of the shortest distance, by constituting an adaptor satisfying the shortest wiring length and inserting a pin number converting circuit between a central processing unit and a test pattern control circuit. CONSTITUTION:An adaptor 30 is constituted so that the wiring length between a test pattern control circuit 1 and device under test 4 becomes shorter. A pin number converting circuit 7 is inserted between a central processing unit 5 and the test pattern control circuit 1. By this constitution, by the test data sent out from the circuit 1 arrives the device under test 4 at a high speed with high quality and the response data from the device under test 4 can be applied to the circuit 1 in the same way to perform response within the shortest time.

Description

[Detailed Description of the Invention] l Overview] The present invention relates to a logic circuit testing device that connects a slave pattern control port circuit and a test object with the shortest length of wiring5, and performs high-speed, high-quality 0 testing. The aim is to provide a logic circuit testing device that facilitates the shortest wiring distance by using an adapter that satisfies the shortest wiring length and a pin number conversion circuit. In a logic circuit testing device that tests a device under test by receiving a response signal to a test signal sent to the device under test via an adapter having corresponding wiring for coupling, the adapter has a configuration that satisfies the shortest wiring length, Further, the present invention includes a pin number conversion circuit inserted between the central processing unit and the dead pattern control circuit.

"Industrial Application Field" The present invention relates to a logic circuit testing device that connects a test pattern control circuit and a device under test with the shortest wiring length and performs high-speed, high-quality testing.

Conventionally, an adapter corresponding to the pin number was inserted between the test pattern control circuit and the device under test, but since the pin connection wiring inside the adapter was configured to correspond to the device under test, short-distance wiring was required. Since this had become difficult, there was a request to develop a step to solve the problem.

[Prior Art 1 Figure 5 ζ, L does not show the configuration of a conventional logic circuit testing device; In the 5th and 1st place, ■ is the kesu 1 pattern control [
1 and 2 are Pinelonics devices that give test signals to the test object and receive response signals, 3 is an adapter, 4 is a device under test (UUT), and 5 is a central processing unit (CP).
Ll), 6 is a pattern generator, 11 is a pattern lmori, 12 is a cheetah formatsuta, 13 is a fy-<
Detector 14 fails, not showing memo 1j. 17' loop of 11 volumes of PCI SONOMORI 14, 1 group of 1'X) on PINELEC I. RONIX 2, 1 response, 1 of the test subjects 4: Completed. Connect pin 9 and the corresponding output JI'3.

U-S I-hatashi system i1++ circuit 1. 6. [Pin] - Lectoshinics 1 and 2 are collectively referred to as a tester.

When testing the ΦII product of the test object 4, the data for the pattern L--T6 test is stored in advance, and the central processing unit 5 starts the test process. For exams, -, Q (Yubaturnji ふ L5-Even [from t)・Pattern 1; l] ill! Returned to 1st circuit l, U-1-kuformanota 12 Otsu, Maki, Q
Place 710 Tes i1-ta Otoko conversion (71, Pin lI Ha・
Two L・Shi! Ex 2 C) 1 From the adapter 3, apply 1. Since the device under test is becoming more dense and highly integrated, it is required to improve the transmission quality of the case 1-theta, and the wiring length from the Uino-1 and 2 to the device under test 4-〒F is required. is required to be connected as quickly as possible. However, the physical arrangement of the terminal numbers of the terminal number 2 and the physical arrangement of the terminal numbers of the test object 4 are as follows: 2. The physical distance between the corresponding numbers is the shortest. There are a lot of things like 3, 2, 2, and 3.

Mark 1) H+ was marked on test object 4.
7" f7 ÷ f7 ÷ test answer child - evening is transmitted from the terminal pin to the terminal pin, 3 is reversely transmitted, and the 1st bar L of 2 is input. Comparator B,
2, compared with a predetermined voltage, the output voltage is "'H""
■, ゛ are determined and input to the fail detector 13 of the tester 1. Compare with the test input signal at C and +, detect the right side of the error signal, and the call signal is the pin number of the fail memory 14 where the error occurred. Store in. Next, the pattern generator is incremented, and the next test pattern of the test object 4 is tested by applying the output of the pattern generator.

[Problems to be Solved by the Invention] The test process using the testing machine shown in Figure 5 has had no problems with test objects of low density and low integration circuits, but recently When the device 4 becomes highly integrated, it is necessary to have high-speed and high-quality transmission characteristics for pattern data. The adapter 3 is connected to the test pattern control circuit 1,
In order to satisfy the correspondence of pin numbers with respect to the test object 4, it was necessary to design and manufacture each case.

This is to perform a physical coupling operation in order to test many types of test objects 4. In reality, this condition is not always satisfied, and the two sides of the adapter 3 are often connected with a coaxial pull of, for example, number + Cl11, and even within the adapter 3, the wires connecting the terminals on both sides cross vertically. ,
The drawback was that it was difficult to wire the shortest distance. Inconsistencies that occur during test processing when long wiring is used can pick up external noise and degrade signal quality.Secondly, reflected waves can be generated due to impedance mismatch.1) Increased leakage signal and increased capacitance. etc.

The object of the present invention is to improve the above-mentioned drawbacks and to provide a logic circuit testing device that facilitates the shortest wiring distance by using an adapter that satisfies the shortest wiring distance and a pin number changing circuit.

[Means for Solving the Problems] FIG. 1 shows the basic configuration of the present invention. In Figure 1, ■ is the test pattern control circuit, 4 is the object under test, and 5 is the test pattern control circuit.
7 indicates a central processing unit, 7 indicates a pin number conversion circuit, and 301/J adapter.

Test pattern system controlled by central processing unit 5? &
11 In a logic circuit testing device that tests a device under test 4 by receiving a response signal to a test signal sent from the circuit 1 to the device under test 4 via an adapter 30 having corresponding wiring for pin coupling, The invention has the following configuration. That is, 1j; 1詑-j':9'7'Hi'30 is the configuration in which the shortest wiring length is added by 1. The pin number conversion circuit 7 inserted between L is found and configured.

[Function] Based on the configuration shown in Figure 1, the adapter >"30 solution, last matter system A11, shortest wiring length between circuit 1 and test object 4:, ,I-・')!, since the two configurations are constrained, test data (...) cannot be sent from the control circuit 1; , y)\4, answer data from the device under test 4 can be similarly responded to the test pattern control circuit 1 in the shortest time.At that time, the terminal pin number of the device under test 4 is Control f: f11 Since the terminal pin number υ and one pair in circuit 1 are not 61-2,
The pin number is converted by the pin number conversion circuit 7.

Hll, the central processing unit 5 tests the end pins of the test object 4, for example No. 0 and L2. Since data for terminal pin No. 0 does not necessarily exist at the output/terminal position of control circuit 1 in test pattern 2, which corresponds to No. Converting the data so that it exists.

Embodiment 1 FIG. 2 is a diagram showing a specific configuration of the pin number conversion circuit 7 in FIG. 1 as an embodiment of the present invention.

In the second M, 71 is a pin number counter, 72 is a pin number conversion table, and 73 is a control unit.

The pin number conversion table 72 is
The address is the terminal pin number of the test pattern control circuit, and the data content is the terminal pin number of the test pattern control circuit. The output of the pin number counter 71 is controlled by the control section 73 so that it becomes the address of the pin number conversion table 72. Soshi 7
Then, the test data is sent to the pin controller designated by the pin number indicated by the output signal of the pin number conversion circuit 7.

Therefore, for example, the pin numbers O and 1 of the test object 4.

When the test data is sent in the order of No. 2-, the pin number counter 71 is set to 1 (if the data of the conversion table 72 read at The test error data is sent from the end No. 74 of the test object 4 to the No. 0 pin of the test object 4. The data is applied to the No. 0 pin of the test object 4 via the pin electronics and the adapter 30 as necessary. Next, the pin number counter 71 is incremented, and the data for the address No. 1 of the ruble 72 is read out. Send out.

The table for converting pin numbers in this way stores data set in advance so that the adapter 30 can obtain the shortest wiring length.

Figure 3 shows central processing unit C during pin number conversion operation.
This is a diagram showing the flow of data from the PLi (which corresponds to the central processing unit 5 in Fig. 1). According to Fig. 3, data from the central processing unit CPtJ is
The data is sent in direct correspondence with the data corresponding to each bit number of the IUT. Pin number conversion--The pin number in the data is applied to Th7'. Then, the data in the table is searched using the value incremented by 4 using the pin number counter as an address. For example, the data read from the table is the pin number O, and the data ■ becomes the pin number after number conversion. Next, by converting the pin number, for example, ■, place the corresponding pin on the pin electronics - 2 U
'r's 0 pin data flows. As shown by the thin broken line at the bottom of the connection, the data transmitted to the output terminal of the pin electronics (data at the O pin of the UUT) reaches the 0 pin of the test object U U 'F via the adapter.

Figure 4 shows the time chart for pin number conversion.

FIG. 4A shows a signal for initializing pin number counter 71. FIG. 4B shows the output of the pin number counter 7I, that is, 7 traces of the pin number conversion table 72. FIG. 4C shows test data from the central processing unit 5. FIG. 41] shows a series of pin number conversion tables. FIG. 4E shows a data write strobe signal from the central processing unit 5.

Figure 4F.

G and II indicate the data for the built-in pin number 4.5.6 when the pin electronics is installed.

The address “0” according to the pin number counter “0” of the 41st FB
0" in the conversion table 72, as shown in the fourth diagram, the value is assigned to pin number 4, and for counter "1", number 5 is assigned to pin number 4.
For pins, counter 1-2 corresponds to number 6 pin. Then, as shown in FIG. 4C, the central processing unit 5
The test data for each pin is sent from the number pin obtained at that time to the pin Elec F Ronix adapter.

Test data for each terminal pin No. 0, No. 1, and No. 2 of the test object 4 is sent out at the times shown in 41'JF to 1 (41'JF to 1).

[Effects of the Invention] Thus, according to the present invention, by using an adapter that connects the logic circuit tester and the device under test at the shortest distance, the input/output terminals of the test pattern control circuit can be easily connected. Corresponding numbers for test and response data can be converted using a pin number conversion circuit. Therefore, by setting the pin number conversion circuit in advance, the logic circuit tester can be used effectively for a large number of test objects. 2. Since the logic circuit tester and the device under test are always connected at the shortest possible distance, tests can be performed quickly and accurately without any of the problems mentioned above. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing a specific configuration of a pin number conversion circuit as an embodiment of the present invention, FIG. 3 is a diagram showing the data flow of FIG. 2, Figure 4 is the second
The operation time chart 1 in the figure and FIG. 5 are M showing the configuration of a conventional logic circuit testing device. ■ -Tess;・Pattern control circuit 2 Pin electronics 3.30 Adapter 4 Test object 5 Central processing unit 7 Pin number conversion circuit Figure 1 of the present invention Figure 2

Claims (1)

[Claims] A test signal sent from a test pattern control circuit (1) controlled by a central processing unit (5) to a device under test (4) via an adapter (30) having corresponding wiring for pin coupling. In a logic circuit testing device that tests a device under test (4) by receiving a response signal to a device under test, the adapter (30) has a configuration that satisfies the shortest wiring length, and the adapter (30) has a configuration that satisfies the shortest wiring length, and is connected to the central processing unit (5) and the test pattern. A logic circuit testing device characterized by having a pin number conversion circuit (7) inserted between a control circuit (1).