JPH01284893A - Dot matrix system display device - Google Patents

Dot matrix system display device

Info

Publication number
JPH01284893A
JPH01284893A JP11556188A JP11556188A JPH01284893A JP H01284893 A JPH01284893 A JP H01284893A JP 11556188 A JP11556188 A JP 11556188A JP 11556188 A JP11556188 A JP 11556188A JP H01284893 A JPH01284893 A JP H01284893A
Authority
JP
Japan
Prior art keywords
potential
terminal
transistor
display
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11556188A
Other languages
Japanese (ja)
Inventor
Akiji Hisaoka
久岡 明次
Katsumasa Fujii
藤井 克正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP11556188A priority Critical patent/JPH01284893A/en
Publication of JPH01284893A publication Critical patent/JPH01284893A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

PURPOSE:To select a high definition display device by amplifying outputted results in case of reading out a test signal through an amplification circuit and discriminating the delicate difference of display luminance every picture element. CONSTITUTION:An invertor is constituted of a display body driving transistor Tr2, a readout Tr3, a column selection Tr4, a test signal output control Trsw and a load resistance Re. At such a time, the potential of the terminal T' of the invertor is determined according to the signals accumulated in a driving voltage accumulation capacity Cv if the circuit is normal. When the potential of the terminal T', determined thus, is inputted in the amplification circuit A, the potential of the terminal T' is a little lowered by the amount of the threshold voltage of a Trd and transmitted to a terminal Vv to be read by a tester T. Since the threshold voltage of the Trd can be controlled, the potential of the terminal T', that means, the potential of the accumulation capacity Cv, can be accurately read out if the Tr2, Tr3 and Tr4 accurately act.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、ドット・マトリックス状に配設した単位画素
毎に、表示体駆動トランジスタ、書き込みトランジスタ
および読み出しトランジスタを備えたテスト可能なドツ
トΦマトリックス方式表示装置の内、特IcLsI上に
蛍光体を付着して発光表示させる蛍光画像表示管に関す
るものである。
[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a testable dot Φ matrix having a display drive transistor, a write transistor, and a read transistor for each unit pixel arranged in a dot matrix. Among the type display devices, this invention particularly relates to a fluorescent image display tube in which a phosphor is attached to IcLsI to display light.

〈従来の技術〉 従来、ドット・マトリックス方式の表示装置のうち各単
位画素毎に表示体駆動トランジスタを有する表示装置に
おいて、各画素の良、不良を判断する手段としては、表
示装置を作製して実際に表示を行なってヤ1断する方法
によっていたが、特開昭57−99688号公報に記載
の技術における読み出しトランジスタを各画素毎に設け
る手段により電気的なテストが可能となった。しかしな
がら、この方法によると、各画素に駆動トランジスタの
1開“又は1閉#に対応するデータを書き込み、次に駆
動トランジスタの状態を検知するために読み出しトラン
ジスタを通じて外部の判定回路を駆動する時、外部との
接続線の容量や抵抗等の負荷が大きく、1画素当りの判
定に時間を要するという欠点がある。
<Prior Art> Conventionally, in a dot matrix type display device having a display drive transistor for each unit pixel, a method for determining whether each pixel is good or bad has been performed by manufacturing the display device. Although the conventional method was to actually perform display and then cut the image, electrical testing became possible by means of providing a readout transistor for each pixel in the technique described in Japanese Patent Application Laid-Open No. 57-99688. However, according to this method, when data corresponding to 1 open or 1 closed of the drive transistor is written in each pixel, and then an external determination circuit is driven through the read transistor to detect the state of the drive transistor, The disadvantage is that the load such as the capacitance and resistance of the connection line with the outside is large, and it takes time to make a determination for each pixel.

そこで、本願と同一出願人は、前記欠点を解消したドッ
ト・マトリックス方式表示装置を案出し、昭和60年7
月5日付けで既に出願している(特願昭60−1488
93.特開昭62−9393”l。
Therefore, the same applicant as the present applicant devised a dot matrix type display device that solved the above-mentioned drawbacks, and in 1985,
I have already filed the application on May 5th (Patent Application No. 1488-1488).
93. Japanese Patent Publication No. 62-9393”l.

この表示装置を第3図面の簡単な説明すると、ドット・
マトリックス状に配置された表示素子3が垂直走査回路
lおよび水平走査回路2によって駆動されるものにおい
て、各表示素子3毎に、書き込みトランジスタTri、
表示体駆動トランジスタTr2.読み出しトランジスタ
Tr3および入力信号蓄積容量Cvが設けられ、列選択
トランジスタTr4により選択される。ある画素をテス
トする場合、今仮に例示した第i列第j行の画素をテス
トする場合について考えると、各トランジスタTr2.
Tr3.Tr4.制御トランジスタTrsw、および負
荷素子Re によりインバータが形成される。この時、
回路が正常であれば、蓄積容量Cvに蓄積された信号に
応じてインバータの端子T′の電位が決まる。こうして
決定された端子T′の電位の高、低をインバータから成
る判定回路Invでヤ]定し、その結果を出力制御トラ
ンジスタTr ou tを通しで出力する0この時、′
l!1定回路Invの回路の設計において充分に外部を
駆動できるよう定数を決定する事で、外に接続される負
荷の、駆動を容易にする事ができ、テストが高速化され
るものである。
To briefly explain this display device in the third drawing, dots and
In a device in which display elements 3 arranged in a matrix are driven by a vertical scanning circuit 1 and a horizontal scanning circuit 2, each display element 3 has a write transistor Tri,
Display drive transistor Tr2. A read transistor Tr3 and an input signal storage capacitor Cv are provided and selected by a column selection transistor Tr4. When testing a certain pixel, considering the case where the pixel in the i-th column and j-th row is tested, each transistor Tr2.
Tr3. Tr4. An inverter is formed by the control transistor Trsw and the load element Re. At this time,
If the circuit is normal, the potential at the terminal T' of the inverter is determined according to the signal stored in the storage capacitor Cv. The determination circuit Inv consisting of an inverter determines whether the potential of the terminal T' is high or low determined in this way, and the result is outputted through the output control transistor Trout.
l! When designing the constant circuit Inv, by determining the constants so as to be able to sufficiently drive the external circuit, it is possible to easily drive the externally connected load, and the test speed can be increased.

〈発明が解決しようとする課題〉 前記表示装置は、単位画素の良、不良のヤ]定を高速化
できる顕著な効果を奏するものであるが、僅かに問題が
残る。即ち、前記装置では、各画素を構成するトランジ
スタの短絡や断線の判断は可能であるが、!PIJ定回
路Invの1良“及び1不良“の判定レベルが常に一定
であって変更不可能であるため、各トランジスタの駆動
能力の差、即ち各画素毎の表示の輝度の微妙な差を検出
するのが困難である。特に蛍光画像表示管においては輝
度の微妙な差が画質を悪くする。従って、前述の装置に
よるテストでは、画質品位が高いか低いかの判定ができ
なかった。
<Problems to be Solved by the Invention> Although the display device has the remarkable effect of speeding up the determination of whether a unit pixel is good or bad, a few problems remain. That is, with the above device, it is possible to determine whether the transistors constituting each pixel are short-circuited or disconnected, but! Since the 1-good and 1-bad judgment levels of the PIJ constant circuit Inv are always constant and cannot be changed, it is possible to detect differences in the driving ability of each transistor, that is, subtle differences in display brightness for each pixel. difficult to do. Particularly in fluorescent image display tubes, subtle differences in brightness deteriorate image quality. Therefore, in the test using the above-mentioned apparatus, it was not possible to determine whether the image quality was high or low.

く課題を解決するための手段〉 本発明は前記従来の問題点に鑑み、これを解消するため
になされたもので、ドット・マトリックス方式表示装置
、特に、蛍光画像表示管において、各表示画素毎の良、
不良を判定するものであって、読み出しの際の出力結果
を増幅回路に通して出力結果を増幅し、各画素毎の表示
輝度の微妙な差を判別することが可能な構成としたこと
を要旨とするものである。
Means for Solving the Problems> The present invention has been made in view of the above-mentioned conventional problems and in order to solve the problems. good,
The system is designed to determine defects, and the output result during readout is passed through an amplifier circuit to amplify the output result, making it possible to discern subtle differences in display brightness for each pixel. That is.

〈実施例〉 以下、本発明の一実施例を詳説する。<Example> Hereinafter, one embodiment of the present invention will be explained in detail.

第1図において、第3図と同−若しくは同等のものには
、同一の符号が付してあり、第3図においてインパーク
からなる判定回路Inv を、第1図においてはトラン
ジスタTrd  と抵抗Rdからなる増幅回路Aに置換
した点において相違している0 第1図に示す、本発明の実施例装置の動作について説明
する0 先ず、%i列第j行の画素をテストする場合を考える〇 入力制御トランジスタTrin、列選択用トランジスタ
Tr4、書き込みトランジスタTrl’iオンにするこ
とにより、Vv端子より入力された信号が、蓄積容量C
v に蓄積される。Cvに蓄積された信号は、表示体駆
動トランジスタTr2を制御して表示体3の輝度をコン
トロールする。この際、出力制御トランジスタTrou
t、負荷制御トランジスタ’l’r3w、読み出しトラ
ンジスタTr3はオフにしておく。ここまでの動作でテ
スト信号の表示体への書き込みを行う。
In FIG. 1, the same or equivalent components as in FIG. 3 are given the same reference numerals. 0 The operation of the embodiment device of the present invention shown in FIG. 1 will be explained. 0 First, consider the case where the pixel in column %i and row j is tested.〇 By turning on the input control transistor Trin, the column selection transistor Tr4, and the write transistor Trl'i, the signal input from the Vv terminal is transferred to the storage capacitor C.
It is stored in v. The signal accumulated in Cv controls the display drive transistor Tr2 to control the brightness of the display 3. At this time, the output control transistor Trou
t, the load control transistor 'l'r3w and the read transistor Tr3 are turned off. Through the operations up to this point, the test signal is written to the display body.

次に、入力制御トランジスタTrin、書き込みトラン
ジスタTriをオフにし、出力制御トランジスタTro
ut、  負荷制御トランジスタTrsw、読み出しト
ランジスタTr3をオンすると、第2図に示すような等
何回路を形成する。テスト信号読み出しの際の動作につ
いては、この第2図を用いて説明する。
Next, the input control transistor Trin and write transistor Tri are turned off, and the output control transistor Tro
When ut, load control transistor Trsw, and read transistor Tr3 are turned on, a circuit as shown in FIG. 2 is formed. The operation when reading the test signal will be explained using FIG. 2.

Tr2.Tr3.Tr4.TrswおよびReによりイ
ンバータを形成し、蓄積容量Cvに蓄えられたテスト信
号の電位と、Tr 2 + Try、Tr4の良・不良
に応じて、端子T′の電位が定まる0この点の電位を増
幅回路Aに入力すると、T′の電位はTrd のしきい
値電圧(FETの電流が流れ始める電圧)の分若干低下
してVv端子に伝えられ、テスクTで読み収られる。T
rdのしきい値電圧は、制御可能であるため、T r 
2 、T r 3 *Tr4が正しく動作していれば、
T′の電位、即ちCvの電位は正確に読み出せる。
Tr2. Tr3. Tr4. Trsw and Re form an inverter, and the potential of the terminal T' is determined depending on the potential of the test signal stored in the storage capacitor Cv and whether Tr 2 + Try and Tr4 are good or bad.0 Amplify the potential at this point. When input to circuit A, the potential of T' is slightly lowered by the threshold voltage of Trd (the voltage at which current starts flowing through the FET) and is transmitted to the Vv terminal, where it is read by test T. T
Since the threshold voltage of rd is controllable, T r
2, T r 3 *If Tr4 is working correctly,
The potential of T', ie, the potential of Cv, can be read accurately.

〈発明の効果〉 本発明の増幅回路を内蔵した目的は、電位の伝達を主と
するものではなく、特に蛍光画像表示管でいる。この動
作は、%3図におけるInv回路でも可能であるが、本
発明によれば、画素部分のトランジスタの駆動能力の差
やばらつきを検出することができ、高品位の表示装置の
選別を行なうことが可能となる0
<Effects of the Invention> The purpose of incorporating the amplifier circuit of the present invention is not primarily to transmit electric potential, but particularly to a fluorescent image display tube. This operation is also possible with the Inv circuit shown in Figure %3, but according to the present invention, it is possible to detect differences and variations in the driving ability of the transistors in the pixel portion, and it is possible to select high-quality display devices. 0 is possible

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のドット・マトリックス方式表示装置の
一実施例の構成図、第2図は本発明のテスト実行時の等
価回路図、第3図は従来装置の構成図である。 符号の説明 l:垂直走査回路 2:水平走査回路 Tr 1 :@き込みトランジスタ T r 2 :表示体駆動トランジスタTr3:読み出
しトランジスタ 3:表示素子 Tr4:列選択トランジスタ Cv :駆動電圧蓄積容量 Re :負荷抵抗 A:増幅回路 Trd  :増幅回路トランジスタ Rd :増幅回路抵抗 Trin  :映像信号入力制御トランジスタTrou
t  :テスト信号出力制御トランジスタTrsw  
:テスト信号出力制御トランジスタT:テスタ Rt :テスタ内部抵抗。 代理人 弁理士 杉 山 毅 至(他1名)窮1図
FIG. 1 is a block diagram of an embodiment of a dot matrix type display device of the present invention, FIG. 2 is an equivalent circuit diagram during test execution of the present invention, and FIG. 3 is a block diagram of a conventional device. Explanation of symbols l: Vertical scanning circuit 2: Horizontal scanning circuit Tr 1 : @ Reading transistor Tr 2 : Display element drive transistor Tr 3 : Read transistor 3 : Display element Tr 4 : Column selection transistor Cv : Drive voltage storage capacitance Re : Load Resistance A: Amplification circuit Trd: Amplification circuit transistor Rd: Amplification circuit resistance Trin: Video signal input control transistor Trou
t: Test signal output control transistor Trsw
:Test signal output control transistor T:Tester Rt:Tester internal resistance. Agent: Patent Attorney Takeshi Sugiyama (and 1 other person)

Claims (1)

【特許請求の範囲】[Claims] 1、単位画素をマトリックス状に配列し、各画素毎に、
表示体を駆動する駆動トランジスタと、駆動のための映
像信号を供給する書き込みトランジスタと、駆動トラン
ジスタの出力レベルを外部へ引き出すための読み出しト
ランジスタとを有し、各画素毎の画素を構成する回路の
テストを電気的に行えるようにしたドット・マトリック
ス方式表示装置であって、特にLSI上に蛍光体を付着
して発光表示させる蛍光画像表示管において、前記回路
の画素部分は微少電流で駆動しており、テスト信号読み
出しの際、出力結果を電流増幅し、各画素毎の表示輝度
の微妙な差を判別することが可能な構成となったことを
特徴とするドット・マトリックス方式表示装置。
1. Arrange unit pixels in a matrix, and for each pixel,
The circuit that constitutes each pixel has a drive transistor that drives the display, a write transistor that supplies a video signal for drive, and a read transistor that extracts the output level of the drive transistor to the outside. In dot-matrix display devices that allow tests to be performed electrically, particularly in fluorescent image display tubes that emit light by attaching phosphors to an LSI, the pixel portion of the circuit is driven by a minute current. A dot matrix type display device characterized in that, when reading a test signal, the output result is amplified by current, and the configuration is such that it is possible to discriminate subtle differences in display brightness for each pixel.
JP11556188A 1988-05-12 1988-05-12 Dot matrix system display device Pending JPH01284893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11556188A JPH01284893A (en) 1988-05-12 1988-05-12 Dot matrix system display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11556188A JPH01284893A (en) 1988-05-12 1988-05-12 Dot matrix system display device

Publications (1)

Publication Number Publication Date
JPH01284893A true JPH01284893A (en) 1989-11-16

Family

ID=14665591

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11556188A Pending JPH01284893A (en) 1988-05-12 1988-05-12 Dot matrix system display device

Country Status (1)

Country Link
JP (1) JPH01284893A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004055772A1 (en) * 2002-12-16 2004-07-01 Agilent Technologies, Inc. Active matrix display and its testing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004055772A1 (en) * 2002-12-16 2004-07-01 Agilent Technologies, Inc. Active matrix display and its testing method

Similar Documents

Publication Publication Date Title
KR100839808B1 (en) Inspecting method
JP4338131B2 (en) TFT array, display panel, and inspection method of TFT array
US7265572B2 (en) Image display device and method of testing the same
JP2003043945A5 (en)
JP3246704B2 (en) Wiring board inspection equipment
KR100845159B1 (en) Electrooptic apparatus substrate and method of examining such a substrate, electrooptic apparatus comprising such a substrate and electronic equipment comprising such an apparatus
US6972755B2 (en) Driver circuit for a display device
US20090096770A1 (en) Detecting defects in display panel pixels
JPH055866A (en) Method for checking active matrix substrate
KR20060037365A (en) Inspection method, semiconductor device, and display device
WO2020248861A1 (en) Display device and short circuit detection method therefor
JP2008052111A (en) Tft array substrate, inspection method for same, and display device
CN111833786A (en) Display panel, crack detection method thereof and display device
JP2004233715A (en) Active driving type pixel structure and its inspecting method
US20070158812A1 (en) Method of testing wires and apparatus for doing the same
US7053649B1 (en) Image display device and method of testing the same
JPH01284893A (en) Dot matrix system display device
JP3968713B2 (en) Flat display device and testing method of flat display device
JP2002258231A (en) Liquid crystal display board, information terminal apparatus, apparatus and method for inspecting liquid crystal displaying board and program
JP4128677B2 (en) Inspection method for liquid crystal display devices
JP2003157053A (en) Liquid crystal display device, and inspection method and device therefor
JP4239299B2 (en) Active matrix type liquid crystal display device
JP3177702B2 (en) Inspection method of liquid crystal display
JPS6267479A (en) Dot matrix system display unit
KR100543714B1 (en) Method and Apparatus for inspecting pixel of Display