JPH01281795A - Manufacture of ceramic board - Google Patents
Manufacture of ceramic boardInfo
- Publication number
- JPH01281795A JPH01281795A JP11107588A JP11107588A JPH01281795A JP H01281795 A JPH01281795 A JP H01281795A JP 11107588 A JP11107588 A JP 11107588A JP 11107588 A JP11107588 A JP 11107588A JP H01281795 A JPH01281795 A JP H01281795A
- Authority
- JP
- Japan
- Prior art keywords
- green sheet
- mask
- conductor
- via hole
- green
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title abstract description 21
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000004020 conductor Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 239000011889 copper foil Substances 0.000 abstract description 7
- 239000004033 plastic Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 description 17
- 229920002799 BoPET Polymers 0.000 description 4
- 239000005041 Mylar™ Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
各種電子機器の構成に広く使用されるプリント板のセラ
ミック回路基板に関し、
ビア用孔の周辺でマスクとグリーンシートとの隙間発生
を防止して、積層時に他の導体パターン等との短絡を皆
無とする信転性の高い回路基板が形成でき、且つグリー
ンシートにマスクを貼付ける作業を容易にすることを目
的とし、
延展性の優れた一定厚さの金属箔よりなるマスクを備え
、該マスクをグリーンシートの片面に貼付けて所定位置
にビア用孔を穿設し、該ビア用孔に導体ペーストを充填
して導体ビアを形成して、該マスクを剥離した該グリー
ンシートを積層して焼成する。[Detailed Description of the Invention] [Summary] Regarding ceramic circuit boards for printed boards widely used in the construction of various electronic devices, the present invention has been developed to prevent gaps between the mask and the green sheet around the via holes, and to prevent the formation of gaps during lamination. The purpose is to form a highly reliable circuit board with no short circuits with other conductor patterns, etc., and to make it easier to attach a mask to a green sheet. A mask made of metal foil is provided, the mask is pasted on one side of a green sheet, a via hole is bored at a predetermined position, the via hole is filled with conductive paste to form a conductive via, and the mask is attached. The peeled green sheets are stacked and fired.
本発明は、各種電子機器の構成に広く使用されるプリン
ト板のセラミック回路基板に関する。The present invention relates to a ceramic circuit board of a printed board widely used in the construction of various electronic devices.
最近特に、各種電算機等のプリント板に実装される半導
体チップはますます高集積化されて入出力端子が増加し
、一方では高密度実装が要求される回路基板は微細化さ
れた導体パターンが高密度に形成されている。そのため
、積層時にセラミックよりなる基板の導体ビアと他の導
体パターン等との短絡を皆無にして、信頗性の高い回路
基板を形成することができる新しいセラミック基板の製
造方法が必要とされている。In recent years, semiconductor chips mounted on printed circuit boards for various computers have become increasingly highly integrated and the number of input/output terminals has increased.On the other hand, circuit boards that require high-density mounting have miniaturized conductor patterns. It is densely formed. Therefore, there is a need for a new method for manufacturing ceramic substrates that can eliminate short circuits between the conductor vias of the ceramic substrate and other conductor patterns during lamination, thereby forming a highly reliable circuit board. .
従来より広く使用されているセラミック基板の製造方法
は第２図の側断面図に示すように、（ａ）セラミック基
板を形成するグリーンシート１の片面に、ポリエステル
マイラーフィルム（以下マイラーフィルムと略称する）
よりなるマスク２を一定温度１例えば４０〜５０＠Ｃで
加熱して、加圧することにより軟脆なグリーンシートｌ
を接着した状態、
（ｂ）マスク２を貼付けたグリーンシート１の所定位置
に、導体ビア１−１を形成するビア用孔１ａをポンチに
より穿設した状態、
（Ｃ）上記ビア用孔１ａに導体ペースト３を充填した状
態・
（ｄ）グリーンシート１からマスク２を剥離して導体ビ
ア１−１を表面より突出させた状態、（ｅ）上記のグリ
ーンシート１の導体ビア１−１ と、導体ビア１゛−１
の端面に導体ランド１゛−２を設けて周辺に導体パター
ン１゛−３を形成したグリーンシート１゛の導体ランド
１゛−２とを当接させて積層した状態、の工程順でセラ
ミック基板を製造している。As shown in the side cross-sectional view of FIG. 2, a method for manufacturing a ceramic substrate that has been widely used in the past is as follows: (a) A polyester Mylar film (hereinafter abbreviated as Mylar film) is coated on one side of a green sheet 1 forming a ceramic substrate. )
A soft and brittle green sheet is formed by heating the mask 2 at a constant temperature 1, for example 40 to 50@C, and applying pressure.
(b) A state in which a via hole 1a for forming a conductor via 1-1 is punched in a predetermined position of the green sheet 1 to which the mask 2 is pasted, (C) A state in which the via hole 1a is punched in the above-mentioned via hole 1a. A state in which the conductor paste 3 is filled, (d) a state in which the mask 2 is peeled off from the green sheet 1 and the conductor vias 1-1 protrude from the surface, (e) a state in which the conductor vias 1-1 of the green sheet 1 are Conductor via 1-1
A ceramic substrate is produced in the following process order: a green sheet 1'' with conductor lands 1''-2 provided on the end face thereof and a conductor land 1''-2 of a green sheet 1'' with a conductor pattern 1''-3 formed around it is brought into contact with and stacked. is manufactured.
以上説明した従来のセラミック基板の製造方法で課題と
なるのは、グリーンシート１のビア用孔１ａをポンチに
より穿設すると、第３図（ａ）に示すようにマスク２の
抵抗によりビア用孔１８周辺のマスク２とグリーンシー
トｌに“だれ”が生ずる。The problem with the conventional ceramic substrate manufacturing method described above is that when the via hole 1a of the green sheet 1 is punched, the resistance of the mask 2 causes the via hole to open as shown in FIG. 3(a). "Drops" occur on the mask 2 and the green sheet l around the mask 18.
しかし、軟脆な性質のグリーンシートｌに発生した“だ
れ”は復旧し７ないが、塑性変形を起こし難い性質を有
しているマイラーフィルムのマスク２は瞬時に平面状に
復旧してしまうので、ビア用孔１ａ周囲の貼付部分が剥
離してグリーンシー）１とマスク２との間に大きな径の
隙間が発生する。However, the "sag" that occurs in the soft and brittle green sheet 1 will not recover, but the mylar film mask 2, which has a property that does not easily undergo plastic deformation, will instantly recover to its flat shape. , the adhesive part around the via hole 1a peels off, creating a gap with a large diameter between the green sea) 1 and the mask 2.
そして、次工程により上記ビア用孔１ａに導体ペースト
３を充填すると前記隙間にその導体ペースト３が侵入し
て、（ｂ）図に示すようにマスク２を除去するとグリー
ンシー１−１の表面に前記隙間と同一径の導体が形成さ
れるために、（Ｃ）図に示すように上記グリーンシート
ｌと他のグリーンシートｌ゛を積層する時に、他のグリ
ーンシー目”の導体ビア１’−１と導通した導体ランド
ｌ°−２と上記導体ビア１−１の当接位置が少しずれる
と、導体ランド１′−２の周辺に形成された導体パター
ン１”−３と上記導体ビア１−１ とが短絡するという
問題が生じている。Then, in the next step, when the conductor paste 3 is filled into the via hole 1a, the conductor paste 3 enters the gap, and when the mask 2 is removed as shown in FIG. Since a conductor having the same diameter as the gap is formed, when the green sheet 1 and another green sheet 1 are stacked as shown in FIG. When the abutment position of the conductor land l°-2 which is electrically connected to the conductor land 1'-2 and the conductor via 1-1 is slightly shifted, the conductor pattern 1''-3 formed around the conductor land 1'-2 and the conductor via 1- 1 is causing a short circuit.
また、グリーンシート１に貼付けるマスク２はポリエス
テルマイラーフィルムより形成されているために、その
グリーンシートｌへの貼着力確保と、温度によるマスク
２の寸法変動を最小とする温度および加圧力の制御が必
要となって、貼付は作業が困難となるという問題も生じ
ている。In addition, since the mask 2 attached to the green sheet 1 is made of polyester mylar film, it is possible to ensure adhesion to the green sheet 1 and to control the temperature and pressure to minimize dimensional fluctuations of the mask 2 due to temperature. Another problem has arisen in that this makes the process of pasting difficult.
本発明は上記のような問題点に鑑み、ビア用孔の周辺で
マスクとグリーンシートとの隙間発生を防止して、積層
時に他の導体パターン等との短絡が皆無となって信頼性
の高い回路基板が形成でき、且つグリーンシートにマス
クを貼付ける作業が容易となるセラミック基板の製造方
法の提供を目的とする。In view of the above-mentioned problems, the present invention prevents the generation of gaps between the mask and the green sheet around the via holes, and eliminates short circuits with other conductor patterns during lamination, resulting in high reliability. The purpose of the present invention is to provide a method for manufacturing a ceramic substrate, which enables the formation of a circuit board and facilitates the work of attaching a mask to a green sheet.
本発明は、第１図に示すように延展性の優れた一定厚さ
の銅箔よりなるマスク１２を加圧によりグリーンシート
１の片面に貼付けて、図示していないポンチによりグリ
ーンシート１の所定位置にビア用孔１ａを設け、そのビ
ア用孔１ａに導体ペースト３を充填して導体ビア１−１
を形成して他のグリーンシート１゛を積層することによ
り、信鯨性の高い回路を形成したセラミック基板が製造
される。As shown in FIG. 1, the present invention involves attaching a mask 12 made of a copper foil of a constant thickness with excellent ductility to one side of a green sheet 1 under pressure, and using a punch (not shown) to form a mask 12 on one side of the green sheet 1. A via hole 1a is provided at the position, and the via hole 1a is filled with conductor paste 3 to form the conductor via 1-1.
By forming a green sheet and laminating another green sheet 1, a ceramic substrate on which a circuit with high reliability is formed is manufactured.
本発明では、銅箔よりなるマスク１２を貼付けたグリー
ンシート１にビア用孔１ａを形成すると、延展性の優れ
たマスク１２の銅箔はポンチによりグリーンシート１と
同じように塑性変形の“だれ”が発生するので、ビア用
孔１ａの周辺はマスク１２とグリーンシート１とが密着
して隙間の発生が皆無となり、そのビア用孔１ａに導体
ペースト３を充填して導体ビア１−１は形成すると、グ
リーンシート１の表面に露出する導体ビア１−１はビア
用孔１ａと同一となって、各種のグリーンシートと積層
しても他の回路と短絡がなくなって信頼性の高いセラミ
ック基板を製造することができる。In the present invention, when the via hole 1a is formed in the green sheet 1 to which the mask 12 made of copper foil is pasted, the copper foil of the mask 12, which has excellent ductility, undergoes plastic deformation by punching, similar to the green sheet 1. ” occurs, the mask 12 and the green sheet 1 are in close contact with each other around the via hole 1a, and there is no gap.The via hole 1a is filled with the conductive paste 3, and the conductive via 1-1 is formed. When formed, the conductor vias 1-1 exposed on the surface of the green sheet 1 become the same as the via hole 1a, and even when laminated with various green sheets, there is no short circuit with other circuits, resulting in a highly reliable ceramic substrate. can be manufactured.
また、銅箔よりなるマスク１２をグリーンシート１に貼
付けているので、温度および加圧力等の貼付は条件によ
りマスク１２の貼付力が制御できるため貼付は作業が容
易となり、且つマスク剥離後のグリーンシート寸法変動
を最小限に抑えることが可能となる。In addition, since the mask 12 made of copper foil is attached to the green sheet 1, the adhesion force of the mask 12 can be controlled depending on the conditions such as temperature and pressure, making it easy to apply. It is possible to minimize sheet size fluctuations.
以下図面に示した実施例に基づいて本発明の詳細な説明
する。The present invention will be described in detail below based on embodiments shown in the drawings.
第１図は本実施例によるセラミック基板製造方法の工程
順側断面図を示し、図中において、第２図と同一部材に
は同一記号が付しであるが、その他の１２は片面に貼付
けて加工時に軟脆なグリーンシートを保持するマスクで
ある。FIG. 1 shows a cross-sectional side view of the process order of the ceramic substrate manufacturing method according to this embodiment. In the figure, the same members as in FIG. 2 are given the same symbols, but the other 12 are pasted on one side. This is a mask that holds soft and brittle green sheets during processing.
マスク１２は、延展性および密着力が有りすぎると剥Ｍ
後のグリーンシートの寸法変化が大き過ぎるので、表面
を滑らかに形成した金属箔１例えば１０〜２０μ龍の銅
箔を、ビア用孔１ａを穿設する時に塑性変形を起こし易
いようにアニールにより軟質にしたものである。If the mask 12 has too much spreadability and adhesion, it will peel off.
Since the dimensional change of the subsequent green sheet is too large, the metal foil 1 with a smooth surface, for example, copper foil with a thickness of 10 to 20μ, is annealed to make it softer so that it is more likely to undergo plastic deformation when forming the via holes 1a. This is what I did.
上記部材を使用したセラミック基板の製造は第１図に示
すように、
（ａ）セラミック基板を形成するグリーンシート１の片
面にマスク１２を常温で加圧することにより貼付けて、
軟脆なグリーンシートｌをマスク１２により保持した状
態、
（ｂ）マスク２を貼付けたグリーンシート１の所定位置
に、導体ビア１−１を形成するビア用孔１ａをポンチに
より穿設した状態、
（Ｃ１従来と同様に導体ペースト３を上記ビア用孔１ａ
に充填した状態、
（ｄ）グリーンシート１からマスク２を剥離して、ビア
用孔１ａの径に形成された導体ビア１−１を表面より突
出させた状態、
（ｅ）は従来と同様に、他のグリーンシート１″を積層
してセラミック基板を製造している。As shown in FIG. 1, the production of a ceramic substrate using the above-mentioned members is as follows: (a) A mask 12 is attached to one side of a green sheet 1 forming a ceramic substrate by applying pressure at room temperature.
(b) A state in which a soft brittle green sheet 1 is held by a mask 12; (b) a state in which a via hole 1a for forming a conductor via 1-1 is punched in a predetermined position of the green sheet 1 to which a mask 2 is attached; (C1 As before, apply the conductor paste 3 to the via hole 1a.
(d) A state in which the mask 2 is peeled off from the green sheet 1 and the conductor via 1-1 formed at the diameter of the via hole 1a protrudes from the surface; , and other green sheets 1'' are laminated to manufacture a ceramic substrate.
その結果、ビア用孔１ａの周辺は延展性の優れたマスク
１２によりグリーンシート１と密着した状態で塑性変形
による“だれ”が生じ、それによりビア用孔１ａの周辺
には隙間の発生が皆無となって、表面には小さな径の導
体ビア１−１が露出するので他のグリーンシートと積層
しても回路との短絡がなくなり、信頼性の高い基板を形
成することができる。As a result, "sag" occurs around the via hole 1a due to plastic deformation while being in close contact with the green sheet 1 due to the mask 12 having excellent ductility, and as a result, no gap is generated around the via hole 1a. Since the conductor via 1-1 with a small diameter is exposed on the surface, there is no short circuit with the circuit even if it is laminated with other green sheets, and a highly reliable board can be formed.
また、温度および加圧力等の貼付は条件によりマスク１
２の貼付力が制御できるため貼付は作業が容易となり、
且つマスク剥離後のグリーンシート寸法変動を最小限に
抑えることができる。In addition, depending on conditions such as temperature and pressure, mask 1
The pasting force of 2 can be controlled, making pasting work easier.
In addition, dimensional variations in the green sheet after mask peeling can be minimized.
以上の説明から明らかなように本発明によれば極めて簡
単な方法で、導体ビアは他の回路との短絡がなくなって
信頼性の高いセラミック基板が形成でき、且つマスクの
貼付は作業が容易となる等の利点があり、著しい経済的
及び、信頼性向上の効果が期待できるセラミック基板の
製造方法を提供することができる。As is clear from the above explanation, according to the present invention, a highly reliable ceramic substrate can be formed by eliminating short circuits with other circuits in the conductor vias using an extremely simple method, and the work of attaching the mask is easy. It is possible to provide a method for manufacturing a ceramic substrate, which has the following advantages and can be expected to have significant economical and reliability improvement effects.
第１図は本発明の一実施例によるセラミック基板の製造
方法を示す工程順側断面図、
第２図は従来のセラミック基板の製造方法を示す工程順
側断図、
第３図は課題を示す側断図である。
図において、
１、１’はグリーンシート、
１ａはビア用孔、
■−１は導体ビア、
３は導体ペースト、
１２はマスク、
を示す。
／￥−発明遁−欠′方ヒ？Ｊ♂；Ｊｔウミζり ａ
ｎ右ラうッ刀Ｅ陵−壓、遣幻憂を秒喪【遺じイ充ヒセ末
すｉＢｔθ貢ばｎ 木すイ列♂乍σゴ７−ヘシ
。
第１図 第２ｖＡ
躍題を末イ利＃図
第３図FIG. 1 is a step-by-step side sectional view showing a method for manufacturing a ceramic substrate according to an embodiment of the present invention. FIG. 2 is a step-by-step side sectional view showing a conventional method for manufacturing a ceramic substrate. FIG. 3 shows problems. It is a side sectional view. In the figure, 1 and 1' are green sheets, 1a is a via hole, 1-1 is a conductor via, 3 is a conductor paste, and 12 is a mask. /￥-Invention - Missing way? J♂；Jt sea ζri a
n Right La Utto Eryo - 壓, I'm going to mourn for a second time. Figure 1 Figure 3
Claims (1)
）を備え、 該マスク（１２）をグリーンシート（１）の片面に貼付
けて所定位置にビア用孔（１ａ）を穿設し、該ビア用孔
（１ａ）に導体ペースト（３）を充填して導体ビア（１
−１）を形成して、該マスク（１２）を剥離した該グリ
ーンシート（１）を積層・焼成してなることを特徴とす
るセラミック基板の製造方法。[Claims] A mask (12
), the mask (12) is pasted on one side of the green sheet (1), a via hole (1a) is bored at a predetermined position, and the via hole (1a) is filled with conductive paste (3). conductor via (1
-1), and the green sheets (1) from which the mask (12) has been peeled off are laminated and fired.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11107588A JPH01281795A (en) | 1988-05-07 | 1988-05-07 | Manufacture of ceramic board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11107588A JPH01281795A (en) | 1988-05-07 | 1988-05-07 | Manufacture of ceramic board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01281795A true JPH01281795A (en) | 1989-11-13 |
Family
ID=14551750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11107588A Pending JPH01281795A (en) | 1988-05-07 | 1988-05-07 | Manufacture of ceramic board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01281795A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287620A (en) * | 1991-06-18 | 1994-02-22 | Fujitsu Limited | Process of producing multiple-layer glass-ceramic circuit board |
| WO2001095678A1 (en) * | 2000-06-05 | 2001-12-13 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing printed-circuit board |
-
1988
- 1988-05-07 JP JP11107588A patent/JPH01281795A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5287620A (en) * | 1991-06-18 | 1994-02-22 | Fujitsu Limited | Process of producing multiple-layer glass-ceramic circuit board |
| WO2001095678A1 (en) * | 2000-06-05 | 2001-12-13 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing printed-circuit board |
| EP1229770A1 (en) * | 2000-06-05 | 2002-08-07 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing printed-circuit board |
| EP1229770A4 (en) * | 2000-06-05 | 2004-09-29 | Matsushita Electric Ind Co Ltd | Method for manufacturing printed-circuit board |
| US6890449B2 (en) | 2000-06-05 | 2005-05-10 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing printed-circuit board |
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