JPH01280333A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a semiconductor device having a higher withstand voltage by increasing a withstand voltage between a silicon island and a silicon substrate in the formation of a dielectric separation substrate by a method wherein a secondary conductive type semiconductor layer is formed between a semiconductor layer having a primary conductive type principal face and a silicon oxide film under the condition that the secondary conductive type semiconductor film is formed just below the semiconductor layer having the primary conductive type principal face. CONSTITUTION:Ion oxides are injected onto the principal face of a substrate 1 and is annealed so that a buried oxide silicon layer 3 is formed in the silicon substrate. Nextly, a first monocrystal silicon layer 4, which is a primary conductive type and has a first impurity density, is formed on the substrate by a epitaxial growth method. Then, onto that substrate, a secondary conductive type impurity is injected in a second impurity density to form a second conductive type impurity layer 5 on the buried oxide silicon layer 3. After that, on the first monocrystal silicon layer 4, a second monocrystal silicon layer 6, which is a secondary conductive type and has a third impurity density lower than the second impurity density, by the epitaxial growth method. Then, the first and the second monocrystal silicon layers 4 and 6 forms a semiconductor layer.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a substrate for a semiconductor device having a high isolation voltage and a semiconductor layer formed thereon. It is about the method.

[Prior art] To improve electrical insulation between electrical components on a board,
It has long been known that it is desirable to form a thin layer of silicon on a dielectric substrate to avoid surface irregularities of the substrate. For this purpose, a method of forming a silicon layer on a substrate having an insulating layer was studied from around 1964, and J.
, I': lecLrochem, Soc, Vol.
124 No. 1. (1977) pp5c
-12c, the dielectric separation method (Di
A method called elecLric l5olation) has been developed.

[Related technology] However, since the above dielectric separation method has various problems,
New methods of forming semiconductor substrates that solve these problems and reduce costs have been developed.

4a to 4th figure are diagrams showing a method of forming the semiconductor substrate.

First, as shown in FIGS. 4a and 4b, 150% of oxygen ions are placed on a p-type silicon substrate 1 whose main surface is (001).
Inject 2.3×10”/cm2 at keV. After forming silicon oxide film 2 as a protective layer, inject at 1350°C for 30
By annealing for a minute, a medium-crystalline silicon layer 1' of 700 nm can be obtained on the surface and a buried oxide film 500083 below it. Further, the silicon oxide layer 2 on the surface is removed, and high-concentration antimony is ion-implanted and then diffused to form an n+ diffusion layer 5 on the surface (FIG. 4C). Next, after cleaning the surface thoroughly,
95 in Shihun (H2S iH2CQ2) gas atmosphere
The wafer is heated to 0°C, and the n-type silicon layer 6 is heated to 50 μm.
m (Figure 4d).

Through the above steps, a silicon layer on the insulating film having a breakdown voltage of 400 to 500 V with respect to the substrate is formed, and thereafter, semiconductor processing steps shown in FIGS. 4e to 4 are performed to obtain a silicon island. That is, FIGS. 4e and 4f show the silicon oxide layer 7 formed, the trench 8 opened by photolithography and silicon oxide layer etching, and selective etching performed with an etching solution containing KOH as the main component. show.

Next, an n+ diffusion layer 9 is formed on the walls of the groove 8, and the bottom and side surfaces of the region where the element is to be formed are surrounded by the n+ type layer.

After that, the silicon oxide layer 10 is removed once, and the entire surface is coated with a thickness of 2
A silicon oxide layer 11 with a thickness of 80 μm is formed, and a polysilicon layer 12 is further grown with a thickness of 80 μm, as shown in FIG. 41. This is mechanically polished to make the surface flat, and when the silicon oxide layer 11 is exposed, the polishing is stopped and the silicon oxide layer 11 is chemically removed to reveal an undamaged silicon layer 13 on the crystal surface (Figure 4j). . Further, this is subjected to a semiconductor processing step to obtain a fourth semiconductor integrated circuit as shown in the figure, which is equipped with a high breakdown voltage element.

In the above processing steps, the surface of the silicon layer 13 on which the semiconductor element is formed is not polished and is not damaged, so that it has good crystallinity. Since the film thickness is determined by epitaxial growth, it is characterized by extremely excellent reproducibility and controllability.

However, the above-described method has the problem that the thickness of the buried oxide film cannot be made very long, so that it can only be used with semiconductor elements having a withstand voltage of 500V at most.

This invention has been made to solve the above-mentioned problems, and in forming the dielectric isolation substrate, the withstand voltage between the silicon island and the substrate silicon is improved, and a semiconductor element having a higher withstand voltage is formed. The present invention aims to provide a method for manufacturing a semiconductor device that enables the formation of a semiconductor substrate and a semiconductor layer thereon.

[Means for Solving the Problems] In the method for manufacturing a semiconductor device according to the present invention, a semiconductor layer of a second conductivity type is formed by forming a silicon oxide film adjacent to a lower part of a semiconductor layer having a main surface of a first conductivity type. It was formed between

[Function] The second conductivity type semiconductor layer in this invention functions as an insulating layer.

[Embodiments of the invention] An embodiment of the present invention will be described above with reference to the drawings.

1a to 1Q are diagrams showing each step of the method for manufacturing a semiconductor device according to the present invention.

1a and 1b, similar to FIGS. 4a and 4b, show that a buried oxide film 3 and a surface silicon layer 1' are formed in a silicon substrate 1 by implanting oxygen ions at a high concentration and annealing.

The characteristic process of this invention appears in FIGS. 1C to 1e. In FIG. 1C, a p- epitaxial growth layer is first formed to a thickness of about 10 μm. The impurity concentration and epitaxial layer thickness at this time are determined by the breakdown voltage desired to be increased. That is, in the conventional structure, the withstand voltage between the silicon layer and the silicon substrate 1 was provided only by the withstand voltage of the buried oxide film 3, whereas in this structure, the withstand voltage of the depleted p-epitaxial layer 4 and the buried oxide film 3 are the same. The breakdown voltage of the oxide layer 3 is added, and an improvement in breakdown voltage of several hundreds of volts is obtained. When a region of a certain thickness is depleted, a strong electric field is applied, and the withstand voltage when dielectric breakdown occurs is BV, -E, ψW.

It is expressed as erlt epl. Here, Ecrit is the critical electric field, which is ~30 V/μm in the case of silicon. W again.

epl is in this case the thickness of the p-epitaxial layer.

Experimentally, as shown in Figure 3, p-? of about 1015/cm3. Is there a breakdown voltage of about 250V for an epitaxial layer with a thickness of 10μm at f degree? Being ignored.

(Source: "Physics and Technology of Semiconductor Devices" by A, S, Groove, Physics and Tec
hnology or semiconductor D
evice' P2O0) Here p-concentration 10''
/cm3, the epitaxial layer thickness is 10 .mu.m, and then arsenic is diffused at a high concentration to form an n+ layer 5 of 3 .mu.m, so that the p- layer is 7 .mu.m, and the increase in breakdown voltage is about 200V. In forming the n+ layer, the same effect can be obtained by epitaxially growing the n+ layer with arsenic doping after forming the p- layer.

After the process of Figure 1d is completed, the relatively thin l degree 10
A 50 .mu.m thick n-epitaxially grown layer with a thickness of "/cm3 to 10"/cm3 is formed to obtain FIG. 1e. By doing this, after the subsequent semiconductor processing process,
Since the n" low resistance region at the bottom of the silicon island can be used as a wiring region, it is convenient for device layout, and the depleted p-
By laminating the region 4 and the buried oxide layer 3, the dielectric strength voltage can be increased to 1.5 to 2. This is a 0x improvement.

The subsequent semiconductor device manufacturing process is shown in Figures 4a to 4.
As explained in the figure.

[Effects of the Invention] As described above, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor layer of a second conductivity type is formed as a silicon oxide layer adjacent to the lower part of a semiconductor layer having a main surface of a first conductivity type. Since it is formed between the silicon oxide layer and the second conductivity type layer, not only the silicon oxide layer but also the second conductivity type layer acts as an insulating layer. Therefore, there is an effect that the breakdown voltage is greater than that in the case of only a silicon oxide layer.

[Brief explanation of the drawing]

Figures 1a to 1fL are diagrams showing the manufacturing process at each stage of the method for manufacturing a semiconductor device according to the present invention, and Figure 2 shows the relationship between the amount of oxygen ions implanted, the thickness of the buried silicon oxide film, and the breakdown voltage. FIG. 3 is a diagram showing the relationship between breakdown voltage and doping concentration, and FIGS. It is a figure which shows the manufacturing process of each stage by the manufacturing method of a device. In the figure, 1 is a p-type silicon substrate, 1' is a surface silicon layer, 2 is a silicon oxide layer, 3 is a buried oxide film, 4 is a p- epitaxial layer, 5 is an n+ diffusion layer, 6 is an n- epitaxial layer, 7 1 is a silicon oxide layer, 8 is a trench, 9 is an n+ diffusion layer, 10 is a silicon oxide layer, 11 is a silicon oxide layer, 1
2 is a polysilicon layer, and 13 is a silicon layer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. ++i+++ 剟30 7F 剘品儂辰(.nee 3) 11i /13 0+ p+ n+

Claims (7)

[Claims] (1) providing a silicon substrate having a major surface and having a predetermined impurity concentration of a conductivity type, such that a buried silicon oxide layer is formed within the substrate;
implanting oxygen ions onto the main surface of the substrate and annealing it; and forming a first single crystal silicon layer of a first conductivity type and having a first impurity concentration on the annealed substrate by epitaxial growth. and implanting a second conductivity type impurity at a second impurity concentration onto the first single crystal silicon layer, thereby forming a second conductivity type impurity layer adjacent to the top of the buried silicon oxide layer. forming a second silicon layer of the second conductivity type on the first single crystal silicon layer;
forming a second single crystal silicon layer having a third impurity concentration lower than the impurity concentration by an epitaxial growth method, the first single crystal silicon layer and the second single crystal silicon layer forming a semiconductor layer. A method for manufacturing semiconductor devices. (2) The semiconductor layer has a main surface, and further includes the step of forming an element isolation region on the main surface of the semiconductor layer for isolating a plurality of elements formed thereon. A method for manufacturing a semiconductor device according to item 1. (3) The step of forming the element isolation region includes forming a mask layer on the main surface of the semiconductor layer, and forming a window in a portion of the mask layer where the element isolation region is to be formed; 3. The method of manufacturing a semiconductor device according to claim 2, comprising: removing the semiconductor layer through the semiconductor layer; and forming an element isolation portion in the portion where the semiconductor layer is removed. (4) The step of forming the mask layer includes the step of forming a silicon oxide layer, and the step of forming the window includes the step of removing the silicon oxide layer by photolithography. A method of manufacturing the semiconductor device described above. (5) The method for manufacturing a semiconductor device according to claim 4, wherein the step of removing the semiconductor layer includes the step of removing the semiconductor layer by selective etching. (6) The step of forming the element isolation portion includes forming the second conductivity type diffusion layer in the portion where the semiconductor layer has been removed, and forming a silicon oxide layer on the diffusion layer. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of forming a polysilicon layer on top of the silicon oxide layer so that the silicon oxide layer does not form a recess in the element isolation portion. (7) The main surface of the semiconductor layer formed on the substrate includes the silicon oxide layer formed on the main surface, the silicon oxide layer formed on the part where the semiconductor layer has been removed, and the polysilicon layer. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of removing the silicon oxide layer from above until the silicon oxide layer is exposed.