JPH01278051A - Package structure - Google Patents
Package structureInfo
- Publication number
- JPH01278051A JPH01278051A JP63105494A JP10549488A JPH01278051A JP H01278051 A JPH01278051 A JP H01278051A JP 63105494 A JP63105494 A JP 63105494A JP 10549488 A JP10549488 A JP 10549488A JP H01278051 A JPH01278051 A JP H01278051A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder
- base
- package
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 229910000679 solder Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 238000003780 insertion Methods 0.000 claims abstract description 7
- 230000037431 insertion Effects 0.000 claims abstract description 7
- 230000002265 prevention Effects 0.000 claims description 9
- 239000000919 ceramic Substances 0.000 abstract description 12
- 238000005476 soldering Methods 0.000 abstract description 11
- 239000004020 conductor Substances 0.000 abstract description 10
- 238000007639 printing Methods 0.000 abstract description 7
- 239000012212 insulator Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 230000005496 eutectics Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- BUADUHVXMFJVLH-UHFFFAOYSA-N 7-chloro-3-imidazol-1-yl-2H-1,2,4-benzotriazin-1-ium 1-oxide Chemical compound N1[N+](=O)C2=CC(Cl)=CC=C2N=C1N1C=CN=C1 BUADUHVXMFJVLH-UHFFFAOYSA-N 0.000 description 1
- 241000405147 Hermes Species 0.000 description 1
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- 238000003854 Surface Print Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002055 nanoplate Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- -1 that is Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野］
本発明は、絶縁基板パッケージ構造体に関し、特に、絶
縁基板の底部をハンダ接合φ−るときに好都合な基板パ
ッケージ構造体に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulating substrate package structure, and particularly to a substrate package structure convenient for soldering the bottom of an insulating substrate.
［従来の技術］
従来、電ｆ部品パッケージ構造において、絶縁基板上に
ＩＣなどを搭載し、その絶縁基板をメタルパッケージベ
ースに接合し、ハーメチックパッケージするものである
。この場合、絶縁基板をロウ付けしたり、はんだ付けで
、ベースに取り付ける方法がある。[Prior Art] Conventionally, in an electronic component package structure, an IC or the like is mounted on an insulating substrate, and the insulating substrate is bonded to a metal package base to form a hermetic package. In this case, there is a method of attaching the insulating substrate to the base by brazing or soldering.
このようなパッケージ混成集積回路の構造としては、そ
の絶縁基板（裏）表面を、Ｍｏ−Ｍｎ法或いは活性金属
法などにより、ロウ付は可能にしたり、或いはペーパー
コーディングを用いたり、或いはＡｇペーストを焼き付
けて、はんだ付は可能な状態にし、その−ヒにロウ付け
（或いははんだ付け）するＪｊ法が、取られ実用されて
いる。As for the structure of such a packaged hybrid integrated circuit, the surface of the insulating substrate (back side) may be brazed by Mo-Mn method or active metal method, or paper coating may be used, or Ag paste may be applied. The Jj method has been adopted and put into practical use, in which the material is baked to a solderable state and then brazed (or soldered) to the material.
このような従来法では、リードピンとパッケージのベー
スが、はんだ付けにより短絡したり、また、短絡しない
ようにはんだ付は個所を、充分に分離する必要があった
。その結果、充分な接合面積をとれなかったり、７行性
がとれない場合があり、接合層の厚さがバラツキ、基板
の端部に隙間が生じるおそれがあった。。In such conventional methods, the lead pins and the base of the package may be short-circuited by soldering, and it is necessary to separate the soldering points sufficiently to prevent short-circuiting. As a result, there were cases where a sufficient bonding area could not be obtained or heptadality could not be achieved, the thickness of the bonding layer would vary, and there was a risk that gaps would occur at the edges of the substrate. .
また、作業に習熟を必要とする等の短所があった。゛し
留りや信頼性も［−分なものがなかった。：ｌた、放熱
特性のバラツキも、良くなかった。In addition, there were disadvantages such as the need for proficiency in the work. There was nothing in terms of retention and reliability. :Also, the variation in heat dissipation characteristics was also not good.
［発明が解決しようと４゛る問題点コ
本発明は、セラミックス基板に絶縁体を厚膜印刷するこ
とにより、メクルパ／ケージとの間のはんだ付けによる
接合を行なう時に、リードピンとパンゲージ間の短絡の
歩留りと信頼性と放熱特性と、基板端の′ツイヤーボン
ディング特性を向トできる絶縁基板パッケージ構造体を
提供するものである。[4 Problems to be Solved by the Invention] The present invention prevents short circuits between lead pins and pan gauges when soldering them to a mechanical board/cage by printing a thick film of insulator on a ceramic substrate. The present invention provides an insulated substrate package structure that can improve the yield, reliability, heat dissipation characteristics, and twer bonding characteristics of the substrate edge.
［発明の構成］
［問題点を解決４るための手段］
本発明は、リード挿込用穴を有する絶縁基板を有４゛る
メタルハーメチックパッケージ構造体において、該絶縁
基板の底表面の該リード挿込用穴の周囲にハンダ流れ防
＋Ｌ西条部を設け、ハンダで該絶縁基板の底面をメタル
ハーメブックベース而に接合した構造を有４−ることを
特徴とする絶縁ノ、（板を有１−るメタルバーメチ／ク
パｙゲーン構造体である。[Structure of the Invention] [Means for Solving the Problem] The present invention provides a metal hermetic package structure having an insulating substrate having holes for inserting leads, in which the leads on the bottom surface of the insulating substrate are An insulating board characterized in that it has a structure in which a solder flow prevention +L stripe is provided around the insertion hole, and the bottom surface of the insulating board is joined to a metal herme book base with solder. This is a metal barmetal/kupaygen structure.
［作用］
本発明によると、混成集積回路において、セラミ／ラス
基板をメタルバーメチ／クパッケージのベースにハンダ
付けで接合４°る場合に、セラミックス基板の接合面に
厚膜導体を印刷形成し、焼成し、史に、絶縁体のハンダ
の流れ防止ガイドを印刷形成し、焼成し、その後に、ハ
ンダ接合するような構造を用いる混成集積回路である。[Function] According to the present invention, in a hybrid integrated circuit, when a ceramic/laser substrate is soldered to the base of a metal bar metal/metallic package, a thick film conductor is printed on the bonding surface of the ceramic substrate, This is a hybrid integrated circuit using a structure in which an insulating solder flow prevention guide is printed, fired, and then soldered.
本発明による混成集積回路構造体は、リード挿込用穴を
有１−る絶縁基板を有するメタルハーメチックパッケー
ジ構造体において、該絶縁基板の底表面の該リード挿込
用穴の周囲にハンダ流れ防１１凸条部を設け、ハンダで
該絶縁基板の底面をメタルハーメチックベース面に接合
した構造を有４るものである。A hybrid integrated circuit structure according to the present invention is a metal hermetic package structure having an insulating substrate having lead insertion holes, in which solder flow is prevented around the lead insertion holes on the bottom surface of the insulating substrate. It has a structure in which 11 convex stripes are provided and the bottom surface of the insulating substrate is joined to the metal hermetic base surface with solder.
即ら、混成集積回路におけるヒラミックス基板即ら、絶
縁基板をハンダでメタルハーメチックパ・ゲージベース
に接合もる製造ノｊ法において、リードピンの通る基板
側の穴の周囲にハンダの流れを防ぐガイドを設けたもの
である。In other words, in the manufacturing method in which a Hiramix board in a hybrid integrated circuit, that is, an insulating board is bonded to a metal hermetic pad/gauge base with solder, a guide is used to prevent solder from flowing around the hole on the board side through which the lead pin passes. It has been established.
絶縁基板の接合面に厚膜導体を印刷し、焼成することに
加え、絶縁基板の底面での接合゛するためのハンダの流
れを防止する防止ガイドを印刷焼成し、その後に、ハン
ダ接合できるような構造にしたものである。In addition to printing and baking a thick film conductor on the bonding surface of the insulating substrate, we also printed and baked a prevention guide to prevent the flow of solder for bonding on the bottom surface of the insulating substrate, and then printed and baked it to prevent solder bonding from occurring on the bottom surface of the insulating substrate. It has a unique structure.
本発明の混成集積回路は、セラミ／ラス基板に、即ち、
絶縁基板に厚膜印刷することにより、メタルバッリ°−
ジとのハンダ接続するときに、リードピンとバフケージ
ベース間の短絡を完全に防止し、メタルハーメチソクパ
ノゲージの歩留りと信頼性を向卜し、それにより、得ら
れたパンケージの放熱特性と、ノ、（板端のツイヤ−ボ
ンディング性（接着性）が向［二℃きる。The hybrid integrated circuit of the present invention is mounted on a ceramic/glass substrate, that is,
Metal burr °− is achieved by thick film printing on an insulating substrate.
It completely prevents short circuit between the lead pin and the buff cage base when soldering to the pan gauge, improving the yield and reliability of the metal hermetic pan gauge, thereby improving the heat dissipation characteristics of the resulting pan cage. (The bonding properties (adhesive properties) of the board edges are below 2°C.
本発明は、混成集積回路における（・ラミックス基板を
メタルバーメチ／クパッケージベースにハンダで客筋に
かつ簡便に接合することのできるパンケージ構造体を提
供１°るものである。即ち、ｌテラミックスフ１（板の
接合面に厚膜導体を印刷し、焼成する、−とに加λ、絶
縁基板の接合面一１−でのハンダ流れを防１トするガイ
ドを、印刷焼成して、形成し、その後、ハンダ接合する
構造のものである。The present invention provides a pancage structure in a hybrid integrated circuit (a lamic board can be easily and easily joined to a metal vermetic package base by soldering). 1 (Print a thick film conductor on the bonding surface of the board and bake it, add λ to -1), print and bake a guide to prevent solder flow on the bonding surface of the insulating substrate 1-1. , and then solder-bonded.
本発明で使用するヒラミックス基板即ち絶縁基板は、通
常のヒラミックス基板、例えば、アルミナノ、（板など
を利用する。The Hiramix substrate, that is, the insulating substrate used in the present invention is a normal Hiramix substrate, such as an aluminum nanoplate (plate, etc.).
また、本発明によるハンダ流れ防止凸条部（即ちガイド
部）は、面記のように厚膜印刷技術で容易に作製できる
。Further, the solder flow prevention protruding portion (i.e., the guide portion) according to the present invention can be easily produced using a thick film printing technique as in the case of surface printing.
更に、本発明により用いられるハンダは、電り部品或い
は混成集積回路用として広く使用され、人りしや′４−
いソルダーペーストやプリフォームハンダである。１例
を示ずと、Ｐｂ−３ｎ共晶ハンダ、Ａｇ入りＰ ｂ −
Ｓ ｎ ハンダ、Ａｇ入りＰｂ−３ｎ共晶ハンダ等のＰ
ｂ−３ｎ系ハンダ或いはこれにＡｇを微！ｉｌ：加えた
組成のものであり、厚膜印刷技術やディスペンス或いは
ブリッオーｌ、ハンダをリフ１１−ハンダ付けするもの
である。Furthermore, the solder used in the present invention is widely used for electrical parts or hybrid integrated circuits, and is widely used by people and people.
solder paste or preform solder. To give an example, Pb-3n eutectic solder, Ag-containing P b -
P such as S n solder, Ag-containing Pb-3n eutectic solder, etc.
Add a little Ag to b-3n solder or this! il: Added composition, thick film printing technology, dispensing or brio l, soldering 11-soldering.
次に、本発明の絶縁ノ、（板構造を、具体的な実施例に
より、説明す゛るが、本発明は、その説明により限定さ
れるものではない。Next, the insulating plate structure of the present invention will be explained using specific examples, but the present invention is not limited by the explanation.
［実施例１］
第１図（ａ）は、本発明によるガイド（凸状部）付きセ
ラミックス基板の接合面の正面図であり、第１図（ｂ）
は、接合された状態の断面図である。[Example 1] FIG. 1(a) is a front view of a bonding surface of a ceramic substrate with a guide (convex portion) according to the present invention, and FIG. 1(b)
is a sectional view of the bonded state.
即ち、リードピン３の通る六８を複数有するセラミック
ス基板１は、その面の大部分が、メタライズ導体又はハ
ンダパターン２で覆われる。そして、リードピン穴８の
周囲に絶縁ガイド５を設ける。第１図（ｂ）に示される
ように、絶縁ガイド５があるために、ハンダ２がはみだ
して、リードピン３と接触４−ることが防１トされる。That is, most of the surface of the ceramic substrate 1 having a plurality of pins 8 through which the lead pins 3 pass is covered with the metallized conductor or the solder pattern 2. Then, an insulating guide 5 is provided around the lead pin hole 8. As shown in FIG. 1(b), the presence of the insulating guide 5 prevents the solder 2 from protruding and coming into contact with the lead pins 3.
また、絶縁基板１の表面の殆どに、このハンダ２を載せ
ることができるために、絶縁基板１０周辺においても、
ベース９と絶縁基板１との間に隙間が生じず、構造的に
故障の生じ難いものが得られる。Furthermore, since the solder 2 can be placed on most of the surface of the insulating substrate 1, even around the insulating substrate 10,
There is no gap between the base 9 and the insulating substrate 1, and a structure that is less prone to failure can be obtained.
これに対して、従来のパッケージでは、第２図に示す構
造である。即ち、第２図（ａ）は、従来のセラミックス
基板の裏表面の接合面の正面図である。第２図（ｂ）は
、それの接合された状態の断面図である。即ち、セラミ
ックス基板１は、リードピン３の通る六８を複数有し、
メタライズ導体又はハンダパターン２は、表面の一部に
だけ形成される。そして、第２図（ｂ）の断面図に示す
ように、ハンダが、流れ、リードピンとメタルパッケー
ジベース間に短絡を起こし易いものである。また、絶縁
基板１の周辺部ではベースとの間に隙間があるので、ワ
イヤーポンディングがし難いものになるおそれがある。In contrast, the conventional package has a structure shown in FIG. That is, FIG. 2(a) is a front view of the bonding surface on the back surface of a conventional ceramic substrate. FIG. 2(b) is a sectional view of the bonded state. That is, the ceramic substrate 1 has a plurality of sixes 8 through which the lead pins 3 pass,
The metallized conductor or solder pattern 2 is formed only on part of the surface. As shown in the cross-sectional view of FIG. 2(b), the solder tends to flow and cause a short circuit between the lead pin and the metal package base. Further, since there is a gap between the peripheral part of the insulating substrate 1 and the base, it may be difficult to perform wire bonding.
次に、このような構成の本発明の絶縁基板の構造の製造
方法を第３図（ａ）、 （ｂ）、 （ｃ）により、更に
説明する。Next, the method for manufacturing the structure of the insulating substrate of the present invention having such a configuration will be further explained with reference to FIGS. 3(a), 3(b), and 3(c).
即ち、第３図（ａ）に示すようなセラミックス基板１の
分離面に、厚膜導体ペースト［デュポン（Ｄｕｐｏｎｔ
）６５０２ ］を乾燥膜厚２５μｍに印刷し、厚膜メタ
ライズ導体４を形成し、２５℃、１０分間レベリングし
、１５０℃でＬＯ分間乾燥した後に、絶縁体ペースト［
デュポン（Ｄｕｐｏｎｔ）５７０４］を乾燥膜厚４０μ
ｍ以上に印刷形成し、ハンダ防止絶縁ガイド５を形成し
、２５°Ｃで１０分間レベリングし、１５０℃で１０分
間乾燥した後に、８５０℃で１０分間ピークの全部で１
時間の焼成プロフィルで焼成した。That is, a thick film conductor paste [DuPont
) 6502 ] to a dry film thickness of 25 μm to form a thick film metallized conductor 4 , leveled at 25°C for 10 minutes, and dried at 150°C for LO minutes, then insulator paste [
DuPont 5704] to a dry film thickness of 40μ
m or more, forming a solder prevention insulating guide 5, leveling at 25°C for 10 minutes, drying at 150°C for 10 minutes, and then heating the peak at 850°C for 10 minutes.
Fired with a firing profile of 30 minutes.
次に、第３図（ｂ）に示Ｖように、ソルダーペースト（
千住金属５Ｐ−６０−ＯＦ−２０６３：５ｎ６３ Ｐｂ
３５ Ａｇ２固相１７８°Ｃ液相１９２℃又は日本ゲン
７６２２０ＳＭＴ２６２５ｎ６２ Ｐｂ３５ Ａｇ２共
晶１７９℃）のＡｇ入り共晶ハンダを印刷し、ハンダ層
４を形成した。Next, as shown in FIG. 3(b), solder paste (
Senju Metal 5P-60-OF-2063:5n63 Pb
35 Ag2 solid phase 178°C, liquid phase 192°C or Nippon Gen 76220SMT2625n62 Pb35 Ag2 eutectic 179°C) Ag-containing eutectic solder was printed to form solder layer 4.
史に、第３図（Ｃ）に示すように、メタルハーメチンク
パ７ゲージベース上に、Ｆ記のような構造の絶縁基板を
截置し、接合部が液相温度以上になるように、加熱し、
はんだ層２が溶融した箇所で、基板の−にから押さえ、
絶縁体のハンダ流れ防止ガイド５がメタルバック゛−ジ
ベース９に接触するようにした状態で２５℃で冷却４゛
る。Historically, as shown in Figure 3 (C), an insulating board with a structure as shown in F was placed on a metal hermetically sealed 7-gauge base, and the temperature of the joint was above the liquidus temperature. , heated,
At the point where the solder layer 2 has melted, press it against the − of the board,
The insulating solder flow prevention guide 5 is cooled at 25 DEG C. with the metal bag base 9 in contact with the solder flow prevention guide 5.
［発明の効果］
本発明による絶縁基板構造体では、セラミックス基板接
合面に厚膜導体を印刷、焼成することに加えて、絶縁体
のハンダ流れ防止ガイドを印刷、焼成し、その後、ハン
ダ接合することができるもので、
第１に、リードピンとパッケージベース間が短絡しない
構造を提供すること、
第２に、従来のように、リードピンとパッケージベース
間を距離をとって分離する必要がないこと、
第３に、絶縁基板とパッケージベースの間に、大きな接
合面積を確保でき、また十分な平行度をとれ、そして、
基板端に隙間のできない絶縁基板の構造が得られること
、
第４に、リードピンとバツウーージベース間の構造体の
製造の信頼性と歩留りを向」二きせ、絶縁基板構造の放
熱特性を向上させ、基板端のワイヤーボンディング特性
を向上させることなどの顕著な技術的効果が得られた。[Effects of the Invention] In the insulating substrate structure according to the present invention, in addition to printing and firing a thick film conductor on the bonding surface of the ceramic substrate, a guide for preventing solder flow of the insulator is printed and fired, and then solder bonding is performed. First, it provides a structure that prevents short circuits between the lead pins and the package base. Second, there is no need to separate the lead pins and the package base by a distance as in the past. Thirdly, a large bonding area can be secured between the insulating substrate and the package base, and sufficient parallelism can be achieved.
Fourthly, it improves the reliability and yield of manufacturing the structure between the lead pin and the batten base, and improves the heat dissipation characteristics of the insulated substrate structure. This resulted in significant technical effects such as improved wire bonding characteristics at the edge of the substrate.
第１図（ａ）、（ｂ）は、本発明による絶縁基板の接台
面の正面図と接合された状態の断面図である。
第２図＜８）、（ｂ）は、従来の絶縁基板の接合面の正
面図と接合された状態の断面図である。
第３図（ａ）、（ｂ）、（ｃ）は、本発明による絶縁基
板パッケージの製造方法を説明する断面図である。
［主要部分の符号の説明コ
ｉ、、、、絶縁基板
２、、、、ハンダ層
３、、、、リードビン
４、、、、メタライズ導体層
５、、、、ハンダ流れ防ＩＬガイド
６、、、、ＩＣチップ
？、、、、ワイヤーボンディング
８、、、、リードビン用穴
９、、、、メタスパッケージベース
特許出願人 三菱斌業セメント株式会社代理人 弁理
士 倉 持 裕（外１名）第３図
（ｂ）
第１因
（ｂ）
第２図FIGS. 1(a) and 1(b) are a front view of the contact surface of the insulating substrate according to the present invention and a sectional view of the joined state. FIGS. 2<8) and (b) are a front view of a bonding surface of a conventional insulating substrate and a sectional view of the bonded state. FIGS. 3(a), 3(b), and 3(c) are cross-sectional views illustrating a method of manufacturing an insulated substrate package according to the present invention. [Explanation of symbols of main parts i, Insulating substrate 2, Solder layer 3, Lead bin 4, Metallized conductor layer 5, Solder flow prevention IL guide 6, , IC chip? ,,,,Wire bonding 8,,, Lead bin hole 9, Metas package base patent applicant Mitsubishi Bingyo Cement Co., Ltd. agent Patent attorney Hiroshi Kuramochi (one other person) Figure 3 (b) Cause 1 (b) Figure 2
Claims (1)
メチックパッケージ構造体において、該絶縁基板の底表
面の該リード挿込用穴の周囲にハンダ流れ防止凸条部を
設け、ハンダで該絶縁基板の底面をメタルハーメチック
ベース面に接合した構造を有することを特徴とする前記
パッケージ構造体。In a metal hermetic package structure having an insulating substrate having a lead insertion hole, a solder flow prevention protrusion is provided around the lead insertion hole on the bottom surface of the insulating substrate, and the bottom surface of the insulating substrate is covered with solder. The package structure has a structure in which the metal hermetic base is joined to the metal hermetic base surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63105494A JPH0821643B2 (en) | 1988-04-30 | 1988-04-30 | Package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63105494A JPH0821643B2 (en) | 1988-04-30 | 1988-04-30 | Package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01278051A true JPH01278051A (en) | 1989-11-08 |
| JPH0821643B2 JPH0821643B2 (en) | 1996-03-04 |
Family
ID=14409152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63105494A Expired - Lifetime JPH0821643B2 (en) | 1988-04-30 | 1988-04-30 | Package structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821643B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110098172A (en) * | 2018-01-30 | 2019-08-06 | 深圳市振华微电子有限公司 | A kind of thick film hybrid pin connection structure and connection method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748643U (en) * | 1980-09-04 | 1982-03-18 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS522642A (en) * | 1975-06-24 | 1977-01-10 | Tatsunoshin Takemi | Foldable safety cap |
-
1988
- 1988-04-30 JP JP63105494A patent/JPH0821643B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748643U (en) * | 1980-09-04 | 1982-03-18 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110098172A (en) * | 2018-01-30 | 2019-08-06 | 深圳市振华微电子有限公司 | A kind of thick film hybrid pin connection structure and connection method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0821643B2 (en) | 1996-03-04 |
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