JPH01276775A - Manufacture of insb planar photovoltaic device - Google Patents

Abstract

PURPOSE:To obtain a practical PV element by coating a substrate of B face of a specified face orientation with a diffusion mask film and then performing thermal treatment. CONSTITUTION:A face orientation (211) B face is selected as a substrate 11, thermal CVD temperature is set below 250 deg.C, and an SiO2 film 12 film is selected to 1000-2000Angstrom as a practical range. Then, a substrate 22 after coating SiO2 is selected to the diffusion temperature or up to 500 deg.C in inactive gas or vacuum, and then thermal treatment is performed for 5 minutes or more. As a result, an InSb planar PV element is formed by the mask diffusion method of Cd with an SiO2 film 12 which is the easiest as a semiconductor process being as a mask material.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing an InSb planar photovoltaic element, which is a photovoltaic rectangular element applied to the detection of infrared rays in the 3-5 μm band. Applied to device manufacturing.

(Prior Art) Conventionally, as a method for manufacturing an InSb planar photovoltaic element (hereinafter, a photovoltaic square element is abbreviated as a PV element), I
A technique is known in which impurities are thermally diffused into an nSb substrate by a sealed tube method to form a p-type semiconductor layer. The impurity atoms include Cd and Zn, but Cd is often used because it has better diffusion control and less surface roughness.

The so-called planarization technique, which selectively forms ρ-n junctions in the same plane by mask diffusion, has not been perfected for Cd diffusion. This is because the films used to prevent Cd diffusion include Sin, SiO2. Although there are SiN, etc., in the case of thermal CVD SiO□ film, which is the easiest when considering the film deposition process and hole processing technology, the lateral diffusion is abnormally large and the variation is large, making it difficult to control the bonding area. This is because there is no In addition, in the case of SiO, the deposition process is vacuum evaporation or sputtering, but a film deposited directly on the semiconductor surface in the above process cannot maintain sufficient cleanliness, resulting in undesirable problems during the subsequent thermal diffusion process. It has the disadvantage of introducing some impurities. Furthermore, in the case of SiN, it is currently very promising because it is possible to deposit a film at low temperatures using photo-CVD technology, but there are problems in the technology for forming holes in the film. In other words, selective etching using a hydrofluoric acid-based photoresist at room temperature like Sin cannot be performed, and the film structure is SiN/SiO□, and the upper SiO□ is selectively etched using a hydrofluoric acid-based etching agent. Using SiO□ as a mask, remove the lower SiN using hot phosphoric acid.
However, in the case of InSb,
A stain film is formed on the exposed InSb surface by hot phosphoric acid, and in dry etching methods such as CD[E (chemical dry etching) and RIE (reactive ion etching), etching radicals damage the crystal. It has the disadvantage that thermal annealing cannot fully recover the damage, and the history remains until the final stage.

Therefore, currently commercially available InSb with Cd diffusion
The infrared detection Pv element has a mesa type structure.

However, in the case of a mesa-type structure, problems often arise in subsequent processes due to unevenness after mesa etching.

This problem is even more serious in photodiode arrays, which are infrared imaging devices formed using the same Pv elements.
Planarization using ion implantation has been extensively studied mainly in the United States.

By the way, to date, although planarization using the ion implantation method has been completed structurally, the R8A value (product of diode resistance at zero bias and junction area, unit: Ω-d), which is the figure of merit of the PV element, has been completed. is a Cd diffused mesa type 10
10'Ω-d level (77k) compared to 6Ω-d level (77k)
), the reality is that it is an order of magnitude worse.

The reason why the R6A value of this ion-implanted planar type element is poor is that the InSb crystal is brittle and soft.

In other words, the damage to the crystal that occurs during ion implantation to form the p-layer is much greater than that of Si, GaAs, etc., and the damage is not completely eliminated during post-implantation annealing, resulting in a reduction in carrier lifetime within the crystal. It is something. The decrease in R8A value due to the above phenomenon is the result of selecting Be, which has the smallest mass, as the ion species forming the p-layer, and in order to make the RoA value equivalent to that of the Cd diffused mesa type,
Furthermore, it requires expense and time, and is a heavy economic burden.

(Problems to be Solved by the Invention) When forming a planar type Pv element as described above,
The RoA value was worse than that of the mesa type PV element, and it was difficult to obtain a practical element.

Therefore, the present invention aims to eliminate the above-mentioned drawbacks and to obtain a practical Pv element.

[Structure of the invention]

(Means for Solving the Problems) The present invention relates to a method for manufacturing an InSbnSb brainer element, in which Cd is thermally diffused into an n-type InSb substrate and selectively p
When forming an in-junction, a step of preparing an n-type InSb substrate with a main surface having a B-plane orientation (211).

The film thickness is too~20℃ at 250℃ or less by CVD method.
The method includes a step of depositing a diffusion mask film of SiO2 within the range of QO2, and a step of performing heat treatment at a temperature higher than the diffusion temperature and lower than 500° C. in an inert gas atmosphere or in a vacuum after depositing the diffusion mask film.

(Function) This invention has the following advantages: firstly, the plane orientation of the InSb substrate is selected; secondly, the deposition conditions and film thickness of the Si film formed by the thermal CVO method are selected; and thirdly, the SiO , after membrane deposition.

By applying heat treatment to the substrate and selecting the conditions, S
The present invention provides an improved method for manufacturing an InSbnSb brainer element that takes advantage of the simplicity of the iO□ film and the excellent diffusion performance of Cd.

(Example) Hereinafter, the progress and results of various experiments and studies that led to the achievement of this invention will be described first.

(1) Examination of the plane orientation of the InSb substrate.

Generally, the plane orientation of an InSb substrate is (111), and the B plane is often used. Regarding the above-mentioned surface, in the case of a ■-■ group compound semiconductor, it is a compound of two types of elements. Character is strongly expressed. In this case, side A is the group III side.

Side B means the ■ group side. The plane orientation (111) is A plane.

The characteristics of the B-plane are the most obvious, and for example, when an epitaxial layer is formed using this substrate by the liquid phase epitaxial method, an epitaxial layer with good surface morphology can be obtained for both the A and B-planes. and.

The three surfaces have the characteristic that scratches are less likely to occur in each direction when polished during the substrate formation stage than the A side.

Furthermore, when a Pv element is formed using three surfaces, 1/f
Another feature is that there is less noise.

Therefore, it is clearly advantageous to use three planes, but there is no particular advantage in using the (111) plane orientation in an element that does not use an epitaxial layer formed by a liquid phase method.

According to the inventor's experiments, a substrate temperature of 30°C was applied on an InSb substrate.
In Cd sealed tube diffusion at 400°C using a thermal CVD SiO□ film deposited at 0°C as a mask, when the diffusion depth XJ into the substrate was set to 0.5 μm, the SiO□ mask opening The diffusion length XL that penetrates from the end in the lateral direction was as large as 18 to 150 μm for three (111) planes, and the variation was large. In the same comparison, the surface orientation (100
), it was 13 to 15 μm for one plane orientation (211), and 8 to 9 μm for three planes. Also, the surface orientation (100
), plane orientation (211) For three planes, it was found that G's law is approximately followed when the diffusion time t is changed.

([1) Examination of deposition conditions and film thickness of SiO□ film by thermal CVD method.

Next, the relationship between the deposition conditions of the SiO2 film by the thermal CVD method and the lateral diffusion of Cd with respect to the film thickness was investigated, and the following results were obtained.

(i) CVD S deposited at a substrate temperature around 300°C
In the iO2 film, even if the film thickness is changed in the range of 4,000 to 4,000, the XL during Cd diffusion hardly changes.

In addition, in a film with a thickness of 4000, SiO□ during Cd diffusion
Cracks occur in the membrane.

(i) In the case of film formation conditions of 250°C or less, which is called low-temperature CvD, no change is observed in XL during Cd diffusion when the film thickness is 2000 Å or more, but when the film thickness is 2000 Å or less, the plane orientation (211) Under the same diffusion conditions as above only for three sides, XL is reduced to 5-6 μm.

However, it must be said that this XI value is still too high. In other words, if you just decide on the bonding area, 5~6μ
The value m is not a problem for relatively large-area Pv elements, but the large lateral diffusion means that when considering the cross section of a planar junction, the junction depth increases toward the junction termination (terminating at the surface). This means that the p-n boundary at the end of the junction becomes unclear, which becomes a cause of deterioration of the junction characteristics. Therefore, the lateral diffusion length xL and the diffusion depth
The ratio of J, XI/XJ, must be made as small as possible. Here, XJ is 0.5μm and X15~6μa+ is XI/X
J is over 10, so it cannot be said that planarization has been completed.

The reason why xL decreases only for the three planes with the above-mentioned plane orientation (211) is not determined at present, but it is probably due to thermal strain due to the difference in thermal expansion coefficient between the InSb and SiO2 films depending on the orientation and plane. be interpreted as different.

(1) Consideration of substrate heat treatment temperature range after SiO□ film deposition.

A Sin2-adhered substrate under the same conditions as I (b) above was
, heat treatment was attempted at a stage prior to the formation of pores.

From this experiment, we found that the temperature is the same as or higher than the Cd diffusion temperature (however, the melting point of InSb is 525°C, so it is 500°C).
(limited to below), the surface orientation (21
1) Le xL for 3 sides is 2 μm, XL/X, y ratio 5
It was found that the reduction was as follows. This effect is also observed in other orientations, but it is not as pronounced as in the 1-plane orientation (211) B-plane. In addition, the above-mentioned high-temperature CVD film and low-temperature C
Even VD and those with a film thickness of more than 2,000 people have an effect, but it is not great.

Note that the heat treatment atmosphere is not limited to argon, and similar effects can be obtained using other inert gases or vacuum.

Moreover, the heat treatment is not performed immediately after the SiO□ deposition.

It was sufficient that the heating time was 5 minutes or more.

Also, the explanation so far is based on one diffusion condition (XJ = 0.5μ
As explained in terms of m group 1), since the XJ and XL co-coarticulation laws are followed, even if the diffusion conditions and XJ are changed, Xt, /
There is no loss of X, y ratio.

Figure 5 (a) is a reproduction of an enlarged photograph of the above results.
- Shown in (d).

Figure 5(a) shows a SiO2 film with a thickness of 3 at a substrate temperature of 300°C.
Surface orientation (111) covered on 000 people Approximately 100 on 3 surfaces
An example of lateral diffusion is shown at a magnification of 250 times, where a μm square opening is provided and Cd is diffused from the hole. a is the lateral diffusion length.

FIG. 5(b) shows an example of lateral enlargement at a magnification of 500 times, with the other conditions being the same as in (a) above, except that the substrate has three planes with a (211) plane. The lateral diffusion length Q2 is the above (a
) is extremely small compared to the Ql (250 times) for the magnification.

Figure 5(c) shows Sun, film 1750 at a substrate temperature of 225°C.
An example of lateral diffusion is shown at 500x magnification, with 42 μm square openings provided on 8 sides (211) and Cd diffusion applied thereto. υ3 is the lateral diffusion length.

Figure 5(d) shows the deposition of a SiO2 film at a substrate temperature of 225°C (same as above (C)), followed by deposition at 420°C in argon.
Surface orientation (211) heat treated for 30 minutes 38 on 8 surfaces
An example of lateral diffusion is shown at a magnification of 500 times, where a μm square opening is provided and Cd is diffused therein. Q4 is the lateral diffusion length, which is extremely small compared to Q3 above.

As explained above, it is necessary to select 8 planes with (211) orientation as the substrate, to set the thermal CvD temperature to 250°C or less, to select 1000 to 2000 SiO□iO□ as the practical range, and to select SiO□ After adhesion, the adhered plate is heat-treated in an inert gas or vacuum at a temperature equal to or higher than the diffusion temperature of 500°C for 5 minutes or more.

It has become possible to form an InSb planar Pv element by a Cd mask diffusion method using a SiO2 film, which is the easiest in semiconductor processing, as a mask material.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In order to simplify the explanation, this embodiment will be described as a single-element InSb planar Pv element.

FIGS. 1(a) to (i) are cross-sectional views showing the manufacturing method of this example in the order of steps, and FIG. 2 is a top view of the element obtained by dividing after electrode formation.

First, eight surfaces of an n-type (211) oriented substrate 11 with a carrier concentration of 1014 to 10''/cj are polished and etched by a known method (FIG. 1(a)).

Next, the substrate temperature was 225°C using a bell jar type low temperature CVD device.
1750 SiO2 films 12 were deposited on eight surfaces under the conditions of 100 cc/min, 0.10 cc/In1n, 5% 5iH4 (N2 base), 5 R/min, and 5%5iH4 (N2 base) (FIG. 1(b)).

Next, heat treatment is performed at 420° C. for 30 minutes in a horizontal furnace in an argon atmosphere.

Next, the SiO2 film 12 is
Apertures 13 are selectively provided in (FIG. 1(C)). In this embodiment, the effective light-receiving area is an aperture with a diameter of 111 m, and as shown in the top view of FIG. 2, it is shaped like a teardrop to provide an electrode extraction portion. Further, the selective etching of the 5iOzl sample 12 uses a commonly used NH4F.I-IF solution.

Next, in a sealed quartz ampoule 21 provided with a source partition 21a as shown in FIG. It is sealed and diffused at 400° C. for 1.5 hours to form a p-type region 14 (FIG. 1(d)). The degree of vacuum at the time of sealing the ampoule is 5×10 −4 Pascal or less. In addition, the diffusion depth XJ under the above diffusion conditions is 2
There are 500 people.

After the diffusion, the ampoule is opened and the SiO□ film 12 used as a mask material is removed with hydrofluoric acid (FIG. 1(e)).

Next, a passivation film is provided on the bonding surface (meaning the bonding end portion of the surface) (FIG. 1(f)). As an example of a passivation film, an anodic oxide film 15 having a thickness of 200 yen was used. Further, as a protective film for the anodic oxide film, a film 16 of Sin was deposited to a thickness of 2,000 to 2,500 layers by low-temperature CVD at 200°C.

Next, an electrode opening 17 is provided by photolithography in the electrode extraction portion shown in the top view of FIG. 2 (FIG. 1(g)).

Next, the electrode 1 is
8 (Fig. 1(h)). The electrode metal layers here were made of Cr-Au, and the film thickness was 300 and 1 μm, respectively.

Next, the device is divided and mounted on a sapphire chip carrier 30 provided with electrodes 19, 20 using silver paste, and the wiring 31 and external leads 32, 33 are led out from the device electrodes by ultrasonic bonding of gold wire. This process completes the sensing element (FIG. 1(i)).

Thereafter, the sensing element is assembled into a dual-type test container, passed through cooling means, and the diode resistance and infrared characteristics of the element are evaluated.

FIG. 4 shows a comparison of the R6A temperature characteristics of the InSbnSb brainer element fabricated in this example and the InSbnSb brainer element implanted with [3e ions.

As can be seen from FIG. 4, in the practical temperature range of 77 to 100 K as an infrared detector, the Cd diffused planar element of this example has a higher R0A than the Be ion-implanted planar element.
The value is one order of magnitude better. Furthermore, the R, A values, and infrared characteristics of the device of this example were comparable to those of commercially available CD diffusion mesa type devices.

〔Effect of the invention〕

As described above, according to the present invention, a planar element can be easily obtained without introducing new equipment, and has great economic value.

Although the above embodiment has been explained using a single element, it can naturally be applied to a photodiode array, which is an infrared imaging element, and the features of the present invention can be fully demonstrated by applying it to a photodiode array. be.

[Brief explanation of the drawing]

In FIG. 1, (a) to (i) are p of an embodiment according to the present invention.
All are sectional views showing the manufacturing method of the V element in order of steps. Figure 2 is a top view of the Pv element, Figure 3 is a cross-sectional view of a sealed ampoule for explaining Cd diffusion, Figure 4 is a diagram showing the temperature characteristics of the R6A value, and Figures 5 (a) to ( d) is a top view for explaining the lateral diffusion length in the element. 11--------- N-type (211) substrate 12-
1--------5iO□ film 13-------m--(SiO□ film) opening 14
------------- P-type region 15 --------- One anodic oxide film (passivation film) 16 -------- SiO, film (passivation film) 18 ------------ One electrode 21 --------- One sealed tube ampoule 23 ---
−−−−−Alloy Sauce Agent Patent Attorney Norihiro Ogo
Husband 11: n type (xuyL↑6 and 72: 5L (72 month Mo/3: (sio February 61) Open 3 Lip/4:
Type F @ Engineering/Kuni (N1) I7: Rai J & Development Department (L) f'l, 20: 'tk 31: mLa3Z, 33
:! 'rJrp+)-B30: Dimensions Fufianaup b Lie&i 1 1! l ('1*Z) 2nd
Evil 21: Kei 1 no tube ampoule 2/cL: Somatazu earth blade stand 22: Layer weight gL 23: ?
o E source Figure 3 Figure 4 Figure 5 (￥t)rl) <d) ItzE+: J direction 4 Hirotsu Figure 5 (Z of A)

Claims (1)

[Claims] Selectively p-n by thermally diffusing Cd onto an n-type InSb substrate
When forming a bond, an n-type InSb substrate with a (211) B-plane main surface is used, and 2
A step of depositing a diffusion mask film of SiO_2 with a film thickness in the range of 1000 to 2000 Å at 50°C or less, and a step of depositing a diffusion mask film of SiO_2 with a film thickness in the range of 1000 to 2000 Å, and after depositing the diffusion mask film, a temperature higher than the diffusion temperature and less than 500°C in an inert gas atmosphere or in vacuum. A method for manufacturing an InSb planar photovoltaic device, including a step of performing heat treatment.