JPS63108729A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPS63108729A JPS63108729A JP25431086A JP25431086A JPS63108729A JP S63108729 A JPS63108729 A JP S63108729A JP 25431086 A JP25431086 A JP 25431086A JP 25431086 A JP25431086 A JP 25431086A JP S63108729 A JPS63108729 A JP S63108729A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- oxygen
- circuit elements
- metal
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 230000001590 oxidative effect Effects 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 abstract description 34
- 229910052760 oxygen Inorganic materials 0.000 abstract description 34
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 32
- 239000013078 crystal Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 229910052719 titanium Inorganic materials 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 51
- 238000010438 heat treatment Methods 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005247 gettering Methods 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 150000002926 oxygen Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004566 IR spectroscopy Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical group 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000013528 metallic particle Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体、ウェー７７、特に酸素濃度上充分に低
位化せしめてなるシリコンウエーファに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor wafer 77, and particularly to a silicon wafer having a sufficiently low oxygen concentration.
従来、半導体結晶体、特にシリコン結晶体の製造方法と
して、チックラルスキー法（Ｃ２法）がとられている。BACKGROUND ART Conventionally, the Chickralski method (C2 method) has been used as a method for manufacturing semiconductor crystal bodies, particularly silicon crystal bodies.
最近、結晶体内の酸素濃度勿制御するために、磁界中で
結晶？引き上げるＭＣＺ法が普及されている。これらの
方法により作成されｔ結晶は棒状であり、次の段階で厚
さ数百μｍのウェー７７として切り出される。ここに切
り出され九つェーファは不純物拡散等の処理工８を経て
ＬＳＩチップに加工されるわけであるが、この処理工程
中の熱処理によって基板表面の酸素がウェーファの外方
に拡散して％酸素の少ない表面領域が自然に形成される
０しかしながら、ウェーブァ内部の酸素は外方に拡散で
きないので、内部では酸素濃度が高く残される。この場
合、ウェーファ内部の酸素はＬＳＩチップ形図の九めの
処理工程中の熱処理により３ｉ０１に形取する。この時
、酸素の量が少いと、５ｉＯｚｋ形収した結果鋳起され
る二次的な格子欠陥の歪場がウェー７７表面活性領域の
重金属汚染ｔゲッタリングする友め、有効に作用する。Recently, crystals in a magnetic field have been used to control the oxygen concentration within the crystal body? The MCZ method for pulling up is becoming popular. The t-crystals produced by these methods are rod-shaped and are cut into wafers 77 with a thickness of several hundred μm in the next step. The nine wafers cut out here are processed into LSI chips through processing steps 8 such as impurity diffusion, but due to the heat treatment during this processing step, oxygen on the substrate surface is diffused to the outside of the wafer, reducing the percentage of oxygen. However, since the oxygen inside the waver cannot diffuse outward, a high oxygen concentration remains inside. In this case, the oxygen inside the wafer is shaped into 3i01 by heat treatment during the ninth processing step of the LSI chip shape. At this time, if the amount of oxygen is small, the strain field of secondary lattice defects created as a result of the 5iOzk formation acts effectively to getter the heavy metal contamination in the active region of the surface of the wafer 77.
即ち、ウェーブァ表面の１金属原子の汚染に起因する素
子のリーク電流を減少させるために、無酸素状態よりも
有効に働くことが実証されている。反面、ウェーブァ内
部のように酸素の量が多い場合には、酸素は熱処理によ
って活発化し、多量の５ｔＣｈ ｋ形成する。この５ｌ
ｏｎの形成量が成る限度を越すとウェーファ自体の機械
的強度が減少し、スリップの発生ｔきたす。ウェー７１
内部の酸素はこれがちる限度内に於てはゲッタリング効
果を強くするとともに結晶内部の酸素は転位の運動全抑
制するいわゆる転位の固着作用がある丸め転位は伝播し
ない０つまり熱応力による結晶自体のスリップｔとめる
止めくぎの作用をすることによって、温度が上って結晶
の転位上容易にしてくることの防止機能上乗していると
考えられる。しかし、この酸素濃度が高すぎる場合には
、転位そのものの密度が増大し、かえってスリップを起
しやすい状態となるのである。勿論、こ次に、かかる不
合壇上なくシ、適性な菫の酸素上ウェー７７内に保持し
ておこうとする従来の技術の一例？第２１Ｎ’に参照し
て説明する。１はウェーファ、２Ｈそ、の一方の表面部
分で、ここに回路素子が形成される。厚みに１０乃至２
０μｍで、時として、この部７＞４ハエビタキシヤル成
長によジ形成される場合もある。３げウェーファ１の裏
面である０４はこのウェーファ１の裏面に人工的、機械
的に与えられた傷で、これにより裏面の面積を大にし、
プロセス中の熱処理によりてかかる傷（バックダメジ）
？介して酸素を外方に発散せしめようとするものである
。In other words, it has been demonstrated that this is more effective than the oxygen-free state in reducing the leakage current of the device caused by the contamination of one metal atom on the surface of the waver. On the other hand, when the amount of oxygen is large, such as inside the waver, oxygen is activated by heat treatment and forms a large amount of 5tCh k. This 5l
When the amount of wafer formed exceeds the limit, the mechanical strength of the wafer itself decreases, causing slippage. Way 71
Oxygen inside the crystal strengthens the gettering effect within a certain limit, and oxygen inside the crystal completely suppresses the movement of dislocations. Rounding dislocations do not propagate due to thermal stress. It is thought that by acting as a locking nail to stop the slip t, it has an additional function of preventing crystal dislocation due to temperature rise. However, if this oxygen concentration is too high, the density of dislocations themselves increases, making slips more likely to occur. Of course, this is an example of the prior art technique of trying to keep the violet in a proper violet oxygen top way 77 without having to do this. This will be explained with reference to the 21st N'. Reference numeral 1 designates one surface portion of the wafer 2H, on which circuit elements are formed. 10 to 2 in thickness
0 μm, this part is sometimes formed by 7>4 fly taxial growth. 04, which is the back side of the wafer 1, is a scratch artificially and mechanically given to the back side of the wafer 1, thereby increasing the area of the back side.
Scratches caused by heat treatment during processing (back damage)
? The purpose is to diffuse oxygen outward through the gas.
ウェーハ表面は回路素子が配置されているために酸素の
少ない結晶スリップがない鏡面に保たれていなければな
らない。その為には、何等の損傷も許されない。しかし
、その内部には酸素が存在し、これが結晶スリップの原
因７作り、ＩＪ−り電流の起因にも関連がある。これｔ
救済するのはウェーファ裏側に細工？するしか許されな
い。そこで折角エツチングにより鏡面化された裏面に偽
金つけることによって酸素濃度の調節？！−ハかってい
るのであるが、これは傷の深さがまちまちであって必ず
しも均一な酸素濃度の調整が出来でいるとは限らない。The wafer surface must remain mirror-like, free of oxygen-poor crystal slips, on which circuit elements are placed. For this reason, no damage of any kind is allowed. However, oxygen exists inside it, and this is the cause of crystal slippage and is also related to the cause of IJ current. This is t
Is it the work on the back side of the wafer that will help? I'm only allowed to do it. Therefore, the oxygen concentration can be adjusted by attaching fake gold to the back surface that has been made into a mirror surface by etching. ! - This is because the depth of the scratches varies, and it is not necessarily possible to adjust the oxygen concentration uniformly.
結晶化にとっては単純なもの程均晶質が得られるという
原則からすれば、かかるバックダメジは好ましくない。Based on the principle that the simpler the crystallization, the more homogeneous the crystallization can be obtained, such back damage is not preferable.
本発明によれば、半導体ウェーファの回路素子形成面と
は反対の面にアルミニウム、チタン、ボロン等の強酸化
性金属業薄く被着し、しかる後に熱処理により強酸化性
金Ｊｆ４ｙｔ半褥体つェーファの内部に拡散せしめて、
半導体ウェーファ内部の酸素濃度音制御する半導体ウェ
ーファを得る。According to the present invention, a thin layer of strongly oxidizing metal such as aluminum, titanium, boron, etc. is deposited on the surface opposite to the surface on which circuit elements are formed of a semiconductor wafer, and then heat treatment is applied to form a strongly oxidizing gold Jf4yt semi-wafer. spread inside the
A semiconductor wafer is obtained in which the oxygen concentration sound inside the semiconductor wafer is controlled.
次に、図面を参照して本発明紮より詳細に説明する。第
１図（ａ）〜（ｃ）は本発明の一実施例七七の製造工程
順に示した断面因で、同図（ａ）では、ウェーブア１の
一方の表面部７）２に回路素子が配置される。この表面
部７）２の厚みは１０〜２０μｍで。Next, the present invention will be explained in detail with reference to the drawings. FIGS. 1(a) to 1(c) are cross-sectional views of an embodiment 77 of the present invention shown in the order of manufacturing steps. In FIG. Placed. The thickness of this surface portion 7) 2 is 10 to 20 μm.
時としてこの部分２はエピタキシャル成長により形成さ
れ得る。３はウェーファの裏面である。５はウェーファ
裏面３にプレデポジットされたアルミニウム、チタン、
或はボロン等強酸化性の金属である０この厚さはＣＶＤ
等により一つの分子の厚さから数μｍまで調整できる。Sometimes this part 2 can be formed by epitaxial growth. 3 is the back side of the wafer. 5 is aluminum, titanium, pre-deposited on the back side 3 of the wafer.
Or strong oxidizing metal such as boron.This thickness is CVD.
etc., the thickness can be adjusted from one molecule to several μm.
しかし、この状態でに酸素の制御はまだ極めて不充分で
ある。酸素の活性化は温度に関連する九めに、第１図（
ｂ）に示されるように１次の工程として１１００〜１３
００℃の高温にすることにより１強酸化性金属５はウェ
ーファ１の内部に拡散し、５′の如く分布される０この
ような状態では第１図（Ｃ）に示す如く、酸素Ｏｓ ｋ
ウェーファ１内の各所からウェーブァ裏面側に分布した
強酸化性金属５′に取り込むことによってつゐ−ファ１
内の酸素濃度を制御できる。However, in this state, oxygen control is still extremely insufficient. The activation of oxygen is related to temperature.
1100 to 13 as the primary step as shown in b)
By raising the temperature to a high temperature of 00°C, the strongly oxidizing metal 5 diffuses into the inside of the wafer 1 and is distributed like 5'.
The wafer 1 is absorbed by the strong oxidizing metal 5' distributed on the back side of the wafer 1 from various places inside the wafer 1.
You can control the oxygen concentration inside.
この酸素濃度の制御は被層する強酸化性金属５の量や熱
処理温度によって安定に制御できる。これによりウェー
フッ１内の活性領域の金属汚染ｔゲッタリングすると同
時に、結晶スリップの殆んどナイウェーファが得られる
。This oxygen concentration can be stably controlled by adjusting the amount of the strong oxidizing metal 5 to be coated and the heat treatment temperature. As a result, metal contamination in the active region in the wafer 1 can be gettered, and at the same time, a wafer with almost no crystal slip can be obtained.
次に、本発明の２，３の具体例紫説明する。Next, a few specific examples of the present invention will be explained.
直径５インチの（１１１）表面ｔもつウェーファを用い
、このウェーファ展面に１０−’ 〜１０’ Ｔｏｒｒ
の真空中で、電子ビーム蒸滑法により、約１μｍのアル
ミニウム薄膜で堆積し次。次いでとのウェ−フｙｋ１３
００’０．３時間、Ｎ２中で熱処理ｒ施した０熱処理さ
ｆｌたウェーファのアルミニウム濃度分布を二次イオン
質量分析計（ＳＩＭＳ）で測定したところ、ウェーファ
裏面から約２０μｍに亘ってアルミニウム原子が検出さ
れ、その最大値は２Ｘ１０ 個／備３であった。一方、
酸素濃度分布會赤外分光法で測定したところ、アルミニ
ウム堆積前の値は１．５Ｘ１０”個／帰３でおり九が。A wafer with a diameter of 5 inches and a (111) surface t is used, and a pressure of 10-' to 10' Torr is applied to the developed surface of the wafer.
A thin aluminum film of approximately 1 μm is deposited by electron beam evaporation in a vacuum. The next wafer YK13
When the aluminum concentration distribution of the wafer heat-treated in N2 for 00'0.3 hours was measured using a secondary ion mass spectrometer (SIMS), it was found that aluminum atoms were present over approximately 20 μm from the back surface of the wafer. The maximum value was 2×10 cells/3. on the other hand,
When the oxygen concentration distribution was measured by infrared spectroscopy, the value before aluminum deposition was 1.5 x 10'' pieces/3.
アルミニウム拡散瞬け１．ｌＸ１０”個／ ｃｍ ”で
あることが分りた０アルばニウム盆堆積せずに。Aluminum diffused blink 1. lx10” pieces/cm” was found to be 0 Albanium basins without deposition.
１３００℃、３時間の熱処理を施しｆｃ場合には酸素は
外方拡散によ＃）Ｌ４Ｘ１０”個／ ｃｐｎ”であッ九
〇つまりアルミニウムの拡散、酸化効果にょυα３Ｘ
１０ ” １１Ｍ ／ ｃｍ ３の低位化が認められた
〇このようにして酸素濃度のｔ［ｔｌＪ御され九つェー
ブァにＡｓ埋込み後、エピタキシャル防長を行い、バイ
ポーラ素子【形薦しｙｃｏバイポーラ素子の特性業示す
一項目であるエミッタΦコレクタ間のリーク電流は、本
発明によジ大幅に低減した。例えば１μＡ以下の頻度分
布は改良前に比べて３０％増太し九〇更にＸ線トポグラ
フ法により結晶スリップで評価し次。通常の裏面バック
ダメージ奮施したウェーファに比べて１本発明になるウ
ェー７７のスリップフリー率は著しく低減され、前者が
６５チであるのに対して本発明になるウェーブァはぐチ
であっ九。これは強酸化性金属物質であるアルミニウム
と酸素が反応し、ウェーブァ内部の酸素濃度が低位化し
、このバイポーラ素子の熱処理プロセスでは過飽和度よ
り僅かに高い値となり、酸素に対する固看効来が働いて
スリップの発生が抑えられたものと考えられる。爽にア
ルミニウムの酸化物は重金属のゲッタリング源として有
効に働いているものと考えられる。次に、他の具体例で
は、直径５インチの（１００）表面ｔもつウェー々を用
い、このウェーファ裏面に１０″″ｓ〜１０−’Ｔｏｒ
ｒの真空中で電子ビーム蒸着法により約５００ＯＡのチ
タニウム薄膜？堆積し九。次いで、このウェーファ１１
３００℃、９時間％Ｎｚ中で熱処理を施した。熱処理さ
れたウェーファのチタニウム濃度分布上ｓＩＭｓにより
測定したところ、ウェーファ裏面から約１０μｍに亘っ
てチタニウム原子が検出され友。一方、酸素濃度は堆積
前の値が１．５ Ｘ １０”個／ｃｍ” であっ九の
に対し、チタニウム拡散後は１．０Ｘ１０”個／ ｃｍ
”であっ九。このようにして酸素濃度が制御されたウェ
ーブァに２５６ＫＳＲＡＭ素子？形成し、デバイスの歩
留ｖｋ通常の裏面重付けのウェーファと比較した。本発
明によるウェーファの歩留りは裏面重付けのウエーブア
に比べて ・２５％向上した０更にＸ線トポグラフによ
りスリップの発生を評価し九。スリップフリー率は裏面
重付けのウェーファが７２％であるのに対して本発明に
なるウェーファは９４％であったｏ ＳＲＡＭの製造は
高温プロセス？必要とするが、その場合にはスリップの
低減が重要である。Heat treatment is performed at 1300℃ for 3 hours. In the case of fc, oxygen is caused by outward diffusion.
A reduction of 10" to 11M/cm3 was observed. In this way, the oxygen concentration t The leakage current between the emitter and Φ collector, which is an item that indicates the characteristics, has been significantly reduced by the present invention.For example, the frequency distribution of 1 μA or less has increased by 30% compared to before the improvement. The slip-free rate of the wafer 77 according to the present invention was significantly reduced compared to the conventional wafer with back damage, and the slip-free rate of the wafer 77 according to the present invention was 65 cm compared to 65 cm for the former. This is due to the reaction between aluminum, which is a strong oxidizing metal substance, and oxygen, and the oxygen concentration inside the waver becomes low, and in the heat treatment process of this bipolar element, it reaches a value slightly higher than the supersaturation level, and the oxygen It is thought that the hardening effect worked to suppress the occurrence of slips.It is thought that aluminum oxide is working effectively as a gettering source for heavy metals.Next, in other specific examples, , using 5-inch diameter wafers with (100) surface t, and applying 10''s to 10-'Tor on the back side of the wafer.
Titanium thin film of approximately 500OA by electron beam evaporation method in a vacuum of r? Nine deposits. Next, this wafer 11
Heat treatment was performed at 300° C. for 9 hours in %Nz. When the titanium concentration distribution of the heat-treated wafer was measured using sIMs, titanium atoms were detected over a distance of approximately 10 μm from the back surface of the wafer. On the other hand, the oxygen concentration before deposition was 1.5 x 10"pieces/cm", while after titanium diffusion it was 1.0 x 10"pieces/cm".
A 256K SRAM element was formed on the wafer with the oxygen concentration controlled in this way, and the device yield vk was compared with that of a normal back-weighted wafer.The yield of the wafer according to the present invention was -25% improvement compared to waver 0Furthermore, the occurrence of slip was evaluated using X-ray topography9.The slip-free rate was 94% for the wafer of the present invention, compared to 72% for the back-weighted wafer. The manufacture of SRAM requires high-temperature processes, in which case reduction of slip is important.
以上、強酸化性金属？プレデポジットする工程によジ説
明し友がプレデポジットの代りにプレ拡散或はプレイン
プランティシランにより強酸化性金属音ウェーファ裏面
に装備することも容易に出来る０
〔発明の効果〕
以上説明し友ように、本発明は、ウェーブァ裏面に強酸
化性金ＰＡ″４！ｌ：Ｊ質？接着せしめ、しかる後に高
温処理により強酸化性金属物質ｔウェーファ内部に拡散
せしめ、ウェーファ内部の酸素ａ度ヶ充分に低位化せし
め、半導体回路素子の歩留りを著しく同上できる効果が
ある。Is this a strong oxidizing metal? By explaining the pre-depositing process, it is also possible to easily equip the back side of the wafer with strong oxidizing metallic particles by pre-diffusion or plain plantisilane instead of pre-depositing. In the present invention, strongly oxidizing gold PA''4!L:J quality? is bonded to the back surface of the waver, and then a strongly oxidizing metal material T is diffused into the inside of the wafer by high temperature treatment, thereby reducing oxygen inside the wafer. This has the effect of significantly lowering the yield of semiconductor circuit elements.
暖、 図面のｔｆＪ４Ｌな説明
第１図（ａ）〜（Ｃ）に本発明の−実り例による半導体
ウェーファ勿その製造工程順に示した断面図、第２図框
従米の半導体ウェーファの製造方法を説明する半導体ウ
ェー７１の断面図である。Warm, tfJ4L explanation of the drawings. Figures 1 (a) to (C) are cross-sectional views showing the manufacturing process of a semiconductor wafer according to a practical example of the present invention, and Figure 2 illustrates a method of manufacturing a semiconductor wafer according to the present invention. FIG. 7 is a sectional view of a semiconductor wafer 71.
１・・・・・・半導体ウェーフア、２・・・・・・回路
素子が形成されるウェーファの表面近傍ｗｉ城、３・・
・・・・ウェー７ア炎面、４・・・・・・バックダメジ
饋域、５・・・・・・強−゛パ・」1... Semiconductor wafer, 2... Near the surface of the wafer on which circuit elements are formed, 3...
・・・Way 7a flame side, 4...back damage area, 5...strong-upa.''
Claims (1)
性金属物質が拡散せしめられていることを特徴とする半
導体ウェーファ。A semiconductor wafer characterized in that a strongly oxidizing metal substance is diffused on a surface of the semiconductor wafer opposite to a surface on which circuit elements are arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25431086A JPS63108729A (en) | 1986-10-24 | 1986-10-24 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25431086A JPS63108729A (en) | 1986-10-24 | 1986-10-24 | Semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63108729A true JPS63108729A (en) | 1988-05-13 |
Family
ID=17263214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25431086A Pending JPS63108729A (en) | 1986-10-24 | 1986-10-24 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63108729A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001067503A1 (en) * | 2000-03-03 | 2001-09-13 | Midwest Research Institute | A1 processing for impurity gettering in silicon |
| EP1174918A2 (en) * | 2000-07-19 | 2002-01-23 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of copper transport prevention by a sputtered gettering layer on backside of wafer |
| JP2002313795A (en) * | 2001-04-18 | 2002-10-25 | Shin Etsu Handotai Co Ltd | Silicon single crystal wafer with high-melting-point metallic film and its manufacturing method, and method for impurity gettering in silicon single crystal |
| JP2003007709A (en) * | 2001-06-26 | 2003-01-10 | Shin Etsu Handotai Co Ltd | Silicon single crystal wafer having gettering capability and its manufacturing method |
| WO2007096996A1 (en) * | 2006-02-24 | 2007-08-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and process for producing the same |
-
1986
- 1986-10-24 JP JP25431086A patent/JPS63108729A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001067503A1 (en) * | 2000-03-03 | 2001-09-13 | Midwest Research Institute | A1 processing for impurity gettering in silicon |
| US6852371B2 (en) | 2000-03-03 | 2005-02-08 | Midwest Research Institute | Metal processing for impurity gettering in silicon |
| EP1174918A2 (en) * | 2000-07-19 | 2002-01-23 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of copper transport prevention by a sputtered gettering layer on backside of wafer |
| EP1174918A3 (en) * | 2000-07-19 | 2004-12-22 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of copper transport prevention by a sputtered gettering layer on backside of wafer |
| JP2002313795A (en) * | 2001-04-18 | 2002-10-25 | Shin Etsu Handotai Co Ltd | Silicon single crystal wafer with high-melting-point metallic film and its manufacturing method, and method for impurity gettering in silicon single crystal |
| JP2003007709A (en) * | 2001-06-26 | 2003-01-10 | Shin Etsu Handotai Co Ltd | Silicon single crystal wafer having gettering capability and its manufacturing method |
| WO2007096996A1 (en) * | 2006-02-24 | 2007-08-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and process for producing the same |
| KR101023666B1 (en) * | 2006-02-24 | 2011-03-25 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device and process for producing the same |
| US8329563B2 (en) | 2006-02-24 | 2012-12-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a gettering layer and manufacturing method therefor |
| JP5151975B2 (en) * | 2006-02-24 | 2013-02-27 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
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