JPH0127610B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a semiconductor device, and particularly to an integrated circuit device having a current switch type logic circuit. Conventionally, when configuring a current switch type logic circuit, all the transistors had the same emitter area. In the case of a multi-input logic circuit consisting of multiple transistors,
When attempting to set a high-level potential by turning off all input-side transistors and cutting off the collector current of the input-side transistors, the input-side transistors do not turn off sufficiently, causing the output high-level potential to drop due to leakage current. Also, there was a drawback that the output low level potential of the opposite phase increased. As integrated circuit devices become larger and the logic amplitude tends to be reduced, this drawback becomes even more problematic. An object of the present invention is to minimize the influence of these defects, improve the electrical characteristics of a semiconductor device, and improve manufacturing yield. As a means for achieving this object, the present invention calculates the total emitter area of the transistors that are supplied with a comparison reference potential among a group of transistors that constitute a current switch in which the emitters of the transistors are commonly connected to a constant current source. is set equal to the square root of the product of the sum of the emitter areas of a plurality of transistors to which is supplied and the minimum emitter area of the plurality of transistors, and the transistor to which a comparison reference potential is supplied and the input potential. A load resistor having the same resistance value is connected to the collector of the transistor to which the transistor is supplied. The principle of the present invention will be explained using a current switch type logic circuit having N input potentials, the common emitter of which is connected to a constant current source. Among the transistors on the input side, the smallest emitter area is S, the sum of the emitter areas of the input transistors is A, the emitter area of the transistors on the comparison reference potential side is B, and the constant current value is I, flowing through the transistor on the input potential side. Let I _A be the current, I _B be the current flowing through the comparison reference potential side transistor, and make the potential drop of the high level potential of the logic circuit output determined from I _A and I _B the same under all input potential conditions. Minimum. Find the relational expression between A, B, and S. Also, the input potential is O(v) at high level and -Vl at low level.
(v), the comparison reference potential is -1/2Vl (v), and the emitter added resistance value inside the transistor of the transistor with the emitter area S is R _E. According to the rectification equation, the relationship between current density J and applied voltage V is It is expressed as

In the case of [Equation], Equation (1) is simplified as shown below. Here, Js represents the saturation current density. Solving equation (2) for V gives V=kT/qlnJ/Js...(3). When all N inputs are at a low level, the current flowing through the comparison reference transistor is (I-I _AL ), where I _AL is the sum of the currents flowing through the N input transistors. At this time, the current density of the input side transistor is I _AL /A, and the current density of the comparison reference side transistor is (I - I _AL )/B. When the comparison reference side transistor is on, the voltage between the base and emitter of the comparison reference side transistor is V _B
Then, V _B can be expressed as follows using equation (3). V _B = kT/qln {(I-I _AL )/B・1/Js} ...(4) At this time, due to the emitter added resistance R _EB of the transistor on the comparison reference side, V _B appears to be V′ _B = kT/qln {(I-I _AL )/B・1/Js}+R _EB・(
I-I _AL ) ...(5) becomes. Here, R _EB is considered to be inversely proportional to R _E with respect to the emitter area, and can be expressed as R _EB = S/BR _E ...(6). From equations (5) and (6), V' _B is V' _B = kT/qln {(I-I _AL )/B・1/Js}+S/BR
_E・(I− I _AL ) ……(7) becomes. At this time, a voltage of V' _B - Vl/2 is applied between the base and emitter of the input transistor, and if the emitter added resistance R _EA on the input side is R _EA = S/A R _E ...(8) , the following relational expression holds true. V′ _B −Vl/2=kT/qln {I _AL /A・1/Js}+S
/AR _E・I _AL (9) From equations (7) and (9), the following equation is obtained. Vl/2=kT/qln {(I-I _AL )/I _AL・A/B}+{S
/B(I-I _AL )-S/AI _AL }R _E (10) Next, consider the case where the transistor on the comparison reference potential side is turned off. As a condition for the base-emitter voltage of the transistor on the comparison reference side to be maximum, consider the case where a high level potential is applied to only one transistor on the input side with the minimum emitter area and the transistor is turned on. The current flowing through the comparison reference potential side transistor is
When I _BL , the current flowing through the input transistor receiving the high-level potential input is (I-I _BL ), and the current flowing through the other input transistors receiving the low-level potential input is ignored because it is extremely small. The current density of the turned-on transistor on the input side is
(I-I _BL )/S, and the current density of the comparison reference transistor is I _BL /B. When the voltage between the base and emitter of the turned-on transistor on the input side is V _A , using equation (3), V _A
is V _A = kT/qln {(I-I _BL )/S・1/Js} ...(11), and the emitter added resistance of the input transistor
Due to R _E , the apparent V _A is V′ _A = kT/qln {(I-I _BL )/S・1/Js}+R _E・(
I-I _BL ) ...(12) becomes. At this time, the base of the comparison reference side transistor
A voltage of _V'A - Vl/2 is applied between the emitters, and by adding R _EB in equation (6), the following equation is obtained. V′ _A −Vl/2=kT/qln {I _BL /B・1/Js}+S/
BR _E・I _BL ...(13) From equations (12) and (13), the following equation is obtained. Vl/2=kT/qln {(I-I _BL )/I _BL・B/S} + {(I-I _BL )-S/BI _BL }R _E ……(14) I _AL and I _BL are both This is a leakage current that originally flows through the off-side transistor, and the output high-level potential is I _AL・R I _BL・R, respectively, where the output resistance value is R.
The potential will drop by . Since we want to equalize this potential drop, we set I _AL = I _BL (15). From equations (10), (14), and (15), the following equation is obtained. kT/qlnAS/B ² +R _E {S/B(I-I _AL )-S/AI _AL-
(I-I _AL )+S/BI _AL }=0...(16) Normally, the term I _AL・R _E is extremely small and can be ignored, so equation (16) is simplified as equation (17). be done. kT/qlnAS/B ² +R _E・I (S/B−1)=0……(17) Normally R _E・I is small, kT/q is about 26 mV at room temperature, and q/kT・R _E - I(S/B-1) becomes extremely close to 0, and equation (17) can be simplified to equation (18). B=√・ ...(18) Equation (18) is the total emitter area of the transistors to which the comparison reference potential is supplied, the total emitter area of the transistors to which the input potential is supplied, and the total emitter area of the transistors to which the input potential is supplied. This means that the drop in high-level potential output due to leakage current of the off-side transistor can be balanced out by taking the square root of the product of Even if the emitter area value is used, the same effect as the emitter area value obtained by equation (17) can be obtained. By using the present invention, in a current switch type multi-input logic circuit, a transistor supplied with a comparison reference potential and a plurality of transistors supplied with an input potential are combined, and a current flows through a common collector of the input side transistors. When complementary outputs are generated by the current flowing through the collector of the transistor on the comparison reference side, the drop in the high level potential of the output can be minimized for all combinations of multiple inputs. Since the rise in the low-level potential output of the device can be minimized at the same time, the noise margin of the logic circuit is improved, the circuit is stabilized, and the manufacturing yield is improved compared to conventional devices. The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a first preferred embodiment of the present invention, which is a basic current switch type logic circuit with five inputs. R ₁ and R ₂ are the 100Ω output resistances, and Q ₁
Q ₂ to _{Q 6} are transistors whose base terminals are supplied with a comparison reference potential of -200 mV, and input potentials of high level potential 0 (mV) and low level potential -400 (mV) are supplied to base terminals 2 to 6, respectively. Supplied transistors are shown. Q ₇ is a transistor that supplies a constant voltage potential of −1800 mV to the base terminal 9 to flow a constant current of 4 mA determined by a resistor R ₃ of 100 Ω. Terminal 7 shows the collector output terminal of transistor Q ₁ , terminal 8 shows the output terminal of the common collector of transistors Q ₂ to _{Q 6} , and terminal 10 shows the highest potential terminal.
0 mV and the lowest potential of -3000 mV is applied to the terminal 11. Further, the internal emitter added resistance value of each transistor is 5Ω with an area of 60 μ ² . When a generally used method is used, the emitter area of transistors Q ₁ to Q ₆ is uniformly 60 μ ² . When a low level is supplied to all the terminals 2 to 6, and the current flowing through the transistors Q ₂ to Q ₆ is I _AL1 , the following relationship is obtained from the previous equation (10). 200 (mV) = kT/qln {(4-I _AL1 )/I _AL1・300/60}
+{60/60 (4-I _AL1 )-60/300I _AL1 }・5...(19) Simplify equation (19) by ignoring the I _AL1 component of the second term, and calculate the temperature of 85℃ as kT/q. Substituting _the value of _31mV at
), and I _AL1 becomes 5.93×10 ^-2 mA. Since the value of resistor R ₂ is 100Ω, the high level potential of terminal 8 is
This results in a drop of 5.93 (mV). When using the present invention, by substituting each numerical value into equation (17) (substituting 31mV for kT/q), 31・ln300・60/B ² 5・4・(60/B-1)=0 …(twenty one
), and the emitter area B of transistor _Q1 is
It becomes ^115μ2 . If calculated from equation (18), B=134μ ²
However, this difference is due to the large 1·R _E value. The emitter area of transistor _Q1 is
Calculate the leakage current again as ^115μ2 . terminal 2
When low level is supplied to all ~6 transistors
The current I _AL2 flowing through Q ₂ to Q ₆ is 200 (mV) = kT/qln {(4-I _AL2 )/I _AL2・300/115 from equation (10).
}+{60/115 (4−I _AL2 )−60/300I _AL2 }5(22), which is simplified by ignoring the I _AL2 component of the second term,
Substituting 31 (mV) for kT/q as before, 189.6 (mV) = 31 (mV)・ln{300/115・(4−I _AL2 )
/I _AL2 } ...(23) Therefore, I _AL2 becomes 2.29×10 ^-2 mA. Since the value of the resistor R ₂ is 100Ω, the high level potential at the terminal 8 will drop by 2.29 (mV), but the high level potential drop is improved by about 3.6 (mV) compared to the conventional system. Next, calculate the case where transistor _Q1 is turned off. Now, when only transistor Q ₂ is turned on, the current I _BL2 flowing through transistor Q ₁ is from equation (14): 200 (mV) = kT/qln {(4-I _BL2 )/I _BL2・115/60}
+{(4-I _BL2 )-60/115I _BL2 }・5...(24), which is simplified by ignoring the I _BL2 component of the second term,
By substituting 31 (mV) for kT/q as before, 180 (mV) = 31 (mV) ln {(4-I _BL2 )/I _BL2・115/60
…(25) and I _BL2 becomes 2.29×10 ^-2 mA. Since the value of resistor R ₁ is 100Ω, the high level potential at terminal 7 will drop by 2.29 (mV), making it possible to equalize the high level potential drops at terminals 7 and 8 under the worst input conditions. Ta. Even if equation (18) is used instead of equation (17) and the emitter area of transistor Q ₁ is set to 134μ ² , the drop in the high level potential at terminal 7 is 2.67 (mV), and the drop in the high level potential at terminal 8 is 2.67 (mV).
The drop in high-level potential is 1.88 (mV), and the drop in high-level potential is improved without much difference from the result using equation (17). FIG. 2 is a second embodiment of the present invention, and shows a two-stage current switch type logic circuit as an application example of this method. A first comparison reference potential is commonly supplied to the base terminals 12 and 16 of the transistors Q ₈ and Q ₁₂ , and this value is the same as that of the transistors Q ₉ to _{Q 11} ,
Base terminals ₁₃ to 15, 17 to 19 of Q 13 to Q ₁₅
This is the average potential of the high level potential and the low level potential supplied to the. Base terminal 2 of transistor Q ₁₆
0 is supplied with a second comparison reference potential, and this value is the base terminal 21 of the transistors _Q17 to _Q21 .
It is the average potential of the high level potential and the low level potential supplied to ~25. A constant voltage is supplied to the terminal 26, and the transistor _Q22 and the resistor _R6 constitute a constant current source. In addition, the common collectors of transistors Q ₈ and Q ₁₂ on the comparison reference potential side use the terminal 27 connected to resistor R ₄ as one output terminal, and the common collectors of transistors Q ₉ to Q ₁₁ and Q ₁₃ to _{Q 15} connect to the resistor. _R5
The terminal 28 connected to is used as the other output terminal. The highest potential voltage is supplied to the terminal 29, and the lowest potential voltage is supplied to the terminal 30. When the emitter areas of transistors other than transistors Q ₈ , Q ₁₂ , and Q ₁₆ are uniformly set to 60 μ ² , the emitter areas of transistors Q ₈ , Q ₁₂ , and Q ₁₆ are determined using this method. The transistors targeted by the current switch of transistor Q ₈ are Q ₉ , Q ₁₀ , and Q ₁₁
Therefore, the emitter area of transistor _Q8 is √60・3・60= ^104μ2 . Similarly, the emitter area of transistor _Q12 is also ^104μ2 . Next, calculate the emitter area of transistor _Q16 : √60・
5・60= ^134μ2 . Considering the emitter internal additional resistance component R _E and the convenience of pattern design, the emitter area of each transistor is 100 μ ² for transistors Q ₈ and Q ₁₂ , 130 μ ² for transistor Q ₁₆ ,
By setting the other transistors to ^60μ2 , the drop in output high level potential is improved. Next, an embodiment will be described in which the present invention is applied to a master slice method in which the emitter area is already determined for each transistor. In this case, as is clear, the transistor configuration closest to the calculation result is constructed by connecting the wiring system. now,
In a current switch type logic circuit configured with a substrate having a transistor array consisting only of transistors whose emitter area is S, the optimum number of transistors to be connected in parallel as comparison reference transistors for the number of input transistors is determined using the present invention. It will look like the following table.

[Table] The meaning of the present invention is that the emitter area of the relative reference side transistor does not match the minimum emitter area of the input side, and the present invention is actually effective because:
In the master slice method, this can be said to be an area where the number of inputs is 3 or more. As explained above, by using the present invention, in the case of a current switch type multi-input logic circuit that uses a comparison reference voltage, the drop in the high level potential of the output and the rise in the low level potential can be reduced in total. Since the noise margin of the logic circuit can be set to the minimum value under all input conditions, the noise margin of the logic circuit is improved, and in particular, the electrical characteristics of a large-scale integrated circuit device are improved, and a semiconductor integrated circuit device with a high manufacturing yield can be obtained.

[Brief explanation of drawings]

1 and 2 are diagrams each showing a current switch type logic circuit used in an embodiment of the invention. Q ₁ to _{Q 22} in the diagram are each transistor, R ₁ to _{R 6}
...It's resistance. 1, 12, 16, 20...Comparison reference potential supply terminal, 2-6, 13-15, 17-
19, 21-25...input potential supply terminal, 7,
8, 27, 28...Logic circuit output terminal, 9, 26
... Constant voltage supply terminal for constant current generation, 10, 29...
...highest potential voltage supply terminal, 11,30...lowest potential voltage supply terminal.

Claims (1)

[Claims] 1 a constant current source, and at least one source whose emitter is connected to the constant current source and whose base receives a reference potential for comparison.
a first load resistor connected to the collector of the comparison reference side transistor; and at least two input sides each having an emitter connected to the constant current source and each receiving a separate input signal at its base. a transistor, and a second load resistor connected to the collector of the input transistor and having the same resistance value as the first load resistor,
A semiconductor device characterized in that the total emitter area of the comparison reference side transistors is set equal to the square root of the product of the total emitter area of the input side transistors and the smallest emitter area of these input side transistors.