JPH01274246A - Interruption processing system for microprocessor - Google Patents

Abstract

PURPOSE:To execute first and second interruption programs in parallel by selecting and executing first and second interruption processing programs in time division. CONSTITUTION:A CPU circuit 14 controls the operation of a processor based on the output of a timing generator 11 and an instruction sent from a program ROM 1. An interruption control circuit 15 accepts interruption request signal from terminals 20 and 21, and makes first and second programmable counters 12 and 13 select and execute the first interruption processing program and the second interruption processing program stored in the ROM 1 time divisionally. Control signals from the CPU circuit 14 and the interruption control circuit 15 are supplied to each block via a control bus 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an interrupt processing method for a microprocessor.

BACKGROUND OF THE INVENTION In recent years, Neumann type microprocessors have been widely used in various fields, and their configurations include a program storage unit that stores a program consisting of a group of instructions to be executed sequentially, and a data storage unit that can read and write digital data. a data path connecting the input/output terminals of the data storage means and the input/output terminals of the calculation means; control means for controlling the operations of the data storage means and the arithmetic means based on instructions; a timing generator for generating an instruction execution timing signal; A word is characterized in that it is provided with an instruction selection means for selecting an instruction.

Further, a typical configuration thereof is shown in Japanese Patent Publication No. 58-33584 (hereinafter abbreviated as Document 1).

By the way, the Neumann type microprocessor as shown in the above-mentioned document 1 executes data processing according to a predetermined order, so as the program becomes huge, it becomes difficult to import external data that is input asynchronously. It has 1@ while the cycle of data processing based on it becomes longer. Interruption is often used to detect such problems.

Problems to be Solved by the Invention However, in conventional interrupt processing methods, if a new interrupt request for a different system is issued while interrupt processing is already being executed, the request is completely ignored, or the request is ignored until then. The current interrupt processing is interrupted and a new interrupt processing is started. For this,
There was a problem that one of the built-in processing programs was interrupted or not executed.

For example, if a master processor sends serial data with an identification signal (uniform number) unique to each processor to a large number of slave processors via a common processor, each slave processor will In order to determine whether the content should be received or not, a receiving routine must be executed during each period in which serial data is being sent from the master processor and interrupt processing, and other processing cannot be performed during that period. Therefore, each slave processor placed in such an environment has a problem in that it is essentially only capable of receiving serial data.

SUMMARY OF THE INVENTION In view of this, an object of the present invention is to realize an interrupt processing system for a microprocessor that allows processing programs for multiple systems to be executed without delay even if multiple systems of interrupts occur at the same time.

Means for Solving the Problems In order to solve the above-mentioned problems, in the microprocessor imprint processing method of the present invention, when an interrupt of another system occurs while an interrupt processing program is being executed, the interrupt processing The interrupt control means is provided for causing the first instruction selection means and the second instruction selection means to time-wise select and execute the program and the new interrupt processing program, respectively.

According to the present invention, the above-described configuration provides a microprocessor that can execute the first interrupt processing program and the second JFtlD interrupt processing program in parallel.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a microprocessor in an embodiment of the present invention, and includes a program ROM 1 in which a program consisting of a group of instructions to be executed sequentially is stored, and a RAM (also an IO port) for reading and writing digital data. ) 2, a first address register 3, a second address register 4, and an arithmetic logic unit (LU) 5 that executes digital data arithmetic and logical operations.
and a first register 6 that stores the calculation result at MU Lσ6.
, the second register 7, a data path 8 connecting the common input/output terminal of the RAM 2 and the input/output terminal of the mu LU 5, and an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10. a first programmable counter 12 that selects a specific instruction stored in the program ROM 1 based on the output of the timing generator 11, a second programmable counter 13, and the output of the timing generator 11 and the program. The CtPU control circuit 14, which controls the operation of the processor based on instructions sent from the ROM 1, accepts the interrupt request signal applied to the first interrupt signal input terminal 20 and the second interrupt signal input terminal 21, and executes the program. an interrupt control circuit 16 that causes a first programmable counter 12 and a second programmable counter 13 to select and execute a first interrupt processing program and a second interrupt processing program stored in a ROM 1 in a time-sharing manner;

A control bus 9 is provided for supplying control signals from a CPU control circuit 14 and an interrupt control circuit 16 to each block.

Regarding the microprocessor configured as above,
The operation will be explained with reference to the block diagram shown in FIG. 1 and the timing chart of the main parts shown in FIG.

First, FIGS. 2A and 2B show timing signal waveforms output from the timing generator (TG) 11 based on the clock signal waveforms supplied to the external clock input terminal 10 of FIG. , FIG. 2C shows the interrupt request signal waveform applied to the second interrupt signal input terminal 21, and the second diagram shows the interrupt request signal waveform applied to the second interrupt signal input terminal 21.
This is the waveform of the multiple cutting mode generation signal generated inside the second. FIG. E and FIG. 2F show control signal waveforms sent from the interrupt control circuit 15 to the control bus 9. In addition, FIG. 2G shows the CPU control circuit 14.
This shows the execution cycle of the instructions executed by the command, and the cycle marked with the N symbol in the waveform diagram is the normal interrupt processing cycle, and the cycle marked with the ENG symbol is the second interrupt processing cycle. This is an interrupt processing cycle.

Now, in the timing chart of FIG. 2, time t1
Previously, the first programmable counter 12 and the CPU control circuit 14 selected eight instructions stored in the program ROM 1 and executed them sequentially, but at time t, the second interrupt signal input terminal 21 received #! When the ID interrupt request signal is applied, the 1 interrupt control circuit 15 initiates the multiple interrupt processing mode.

This state is maintained until the delayering command is executed at time t2. As can be seen from Fig. 2G, K, time t,
In the multiple interrupt processing mode from t2 to time t2, the signal waveform of FIG.
The first programmable counter 12
, first address register 3. When the operation of the first register 6 is enabled and the first interrupt processing that has been executed up to that point is intermittently executed, and the signal waveform of FIG. The operations of the counter 13, second address register 4, and second register 7 are enabled, and the second interrupt processing program is executed.

In this way, when multiple interrupt request signals are generated in the microprocessor shown in FIG. Therefore, even during the interrupt processing period, the interrupt processing program does not completely stop, making it possible to construct a system with high real-time performance.

Note that FIG. 3 shows that the 211th
Each figure shows a specific example of the configuration for generating the signal waveforms D, IC, and F, and the signal waveforms shown in FIGS. 2C and B are applied to the input terminals 21 and 30, respectively. , when the signal waveform generated by the return command executed from the second Zuji clock t1 is applied to the input terminal 41, the signals of the 21st diagram, E, and F are output from the output terminals 50, 60, and 70, respectively. A waveform is obtained.

By the way, in the embodiment shown in FIG. 1, the program ROM1 and RAM2 are provided separately, but they can also be allocated to the same memory space, similar to a microprocessor with a conventional deletion processing mechanism. The first programmable counter 12 and the second programmable counter 13 are stored in RAM as registers.
or save it to the stack area in the first register 6.
Alternatively, any of the second registers 7 can be similarly saved in the stack area.

In addition, in this embodiment, when transitioning to interrupt processing mode, parallel interrupt processing is possible by time-sharing switching between the first interrupt processing and the second interrupt processing every machine cycle. However, Micro RO
In a processor with M or a processor that performs pipeline processing, it is more convenient to switch at the break point of a macro instruction and to switch immediately before the conditional branch instruction, rather than switching every machine cycle. Sometimes it's good.

Effects of the Invention As is clear from the above description, the microprocessor interrupt processing method of the present invention includes a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a specific instruction stored in the program storage means. 1st to choose
and a second instruction selection means, a timing generator that generates an instruction execution timing signal, a CPU control means that controls the operation of the processor based on the output of the timing generator, and a second instruction selection means that receives an interrupt request signal.
In addition to executing the interrupt processing program stored in the program storage means, when an interrupt of a different system occurs while the interrupt processing program is being executed, the previous interrupt processing program and the new IN) interrupt processing program are respectively executed. A program storage means comprising: an interrupt control means for causing the first instruction selection means and the second instruction selection means to select and execute the instruction in a time-sharing manner; first and second instruction selection means for selecting a specific instruction stored in the means; data storage means capable of reading and writing digital data; and first and second instruction selection means for selecting one specific address of the data storage means. Address selection is half-immersed,
A calculation means for performing calculations on digital data, first and second registers for storing the calculation results, a data path connecting the input/output terminals of the data storage means and the input/output terminals of the calculation means, and instruction execution timing. a timing generator for generating signals; a CPU control means for controlling the operation of the processor based on the output of the timing generator; The second interrupt processing program is selected and executed by the first instruction selection means and the second instruction selection means in a time-sharing manner, respectively, and the first and second add selection hands and the first and second registers are selected and executed. By providing interrupt control means for switching between the two interrupts, it is possible to obtain a microprocessor that enables parallel processing of the first interrupt processing and the second interrupt processing, which has a considerable effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprocessor in an embodiment of the present invention, FIG. 2 is a timing chart of the main parts of FIG. 1, and FIG. 3 is a circuit diagram showing a specific example of an interrupt control circuit. It is. 1...Program ROM, 2...RA
M, 3...first address register, 4...
...Second address register, 5...MLU
, 6...first register, 7...second register
Register, 8... Data path, 11...
-Timing generator, 12...First programmable counter, 13...Second programmable counter, 14...CPU control circuit, 1
5...8 interrupt-based circuits. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3

Claims (2)

[Claims] (1) A program storage means for storing a program consisting of a group of instructions to be executed sequentially, first and second instruction selection means for selecting a specific instruction stored in the program storage means, and an instruction execution timing signal a timing generator that generates a timing generator; a CPU control means that controls the operation of a processor based on the output of the timing generator; When an interrupt of another system occurs during the execution of a processing program, the previous interrupt processing program and the new interrupt processing program are selected in a time-sharing manner by the first instruction selection means and the second instruction selection means, respectively. An interrupt processing method for a microprocessor, comprising an interrupt control means for at least executing the interrupt. (2) a program storage means for storing a program consisting of a group of instructions to be executed sequentially; first and second instruction selection means for selecting a specific instruction stored in the program storage means; and a means for reading and writing digital data. first and second address selection means for selecting a specific address of said data storage means; arithmetic means for performing arithmetic operations on digital data; and first and second address selection means for storing arithmetic results. a register, a data path connecting the input/output terminal of the data storage means and the input/output terminal of the calculation means, a timing generator for generating an instruction execution timing signal, and an operation of the processor based on the output of the timing generator. a CPU control means for receiving at least two systems of interrupt request signals, and transmitting a first interrupt processing program and a second interrupt processing program stored in the program storage means to the first instruction selection means and the second interrupt processing program, respectively; A microprocessor comprising an interrupt control means for causing a second instruction selection means to select and execute the instruction in a time-sharing manner, and for switching the first and second address selection means and the first and second registers, respectively. Interrupt handling method.