JPH01273357A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent an erroneous erasing by connecting a first voltage limiter to the sheathed electrode of an FET and a row line at a first node to a drain electrode and inputting an erasing control signal by a gate while connecting a second voltage limiter to the row line at the first node. CONSTITUTION:A first diode D1 represents a voltage limiter at VL1 to approximately 16V and a second diode D2 a voltage limiter at VL2 to approximately 12V. A MISFETQ2 is turned ON on writing operation, and a writing power supply VPP1 is transmitted over a row line Y. Since an erasing control signal EC is brought to a high level, however, a MISFETQ4 is turned ON, and row-line potential is clamped at VL2 by the second diode D2. The erasing control signal EC (an over-bar) is brought to the high level, a MISFETQ 3 is turned ON and an erasing power supply VPP2 is transmitted over the row line on erasing operation, but the row-line potential is clamped at VL1 by the first diode D1.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to an electrically erasable and rewritable read-only memory (hereinafter referred to as EEPR).
OM).

[Prior Art] EEFROMs have various structures and operating principles depending on their uses, and among them, the so-called FLASHEEPROM is the most suitable for large-scale integration (for example, 15SCC1987WPM7.4). This F is shown in Figure 4.
A cross-sectional structural diagram of a memory transistor of LASHEEPROM is shown.

1 is a P-type semiconductor substrate, 2 is an N-type drain, 3 is a source, 4 is a thin first gate oxide film with a thickness of 200 gin or less,
5 is a floating gate, 6 is a second gate oxide film, and 7 is a control gate. For writing, a voltage of about 20 V is applied to the control gate 7, a voltage of about 10 V is applied to the drain 2, and the semiconductor substrate 1 and source 3 are grounded, thereby injecting hot electrons generated near the train into the floating gate 5. Accumulates negative charge as . For erasing, ground the control gate 7, source 3, and semiconductor substrate 1, and apply approximately 19V to the drain 2.
Fowler-N.

rdheim) electrons are released from the floating gate 5 to the drain 2 by tunneling, and as a result, positive charges are accumulated.

FIG. 5 shows a circuit diagram when a nonvolatile semiconductor device is constructed using this memory transistor. Q2 is an N input that receives the write control signal PGM (over par) and the data signal.
Q3 is an MIS field effect transistor whose gate input is the output of the OR circuit N0RI, and Q3 is an M whose gate input is the erase control signal EC (over par), which is an erase extra high level signal.
IS field effect transistor, Ml, M2.・・・
・Mn is a memory transistor whose drain is connected to the column line Y, whose source is connected to the source line, and whose control gate is connected to the row line Xi.
, X2. ...Connected to Xn.

[Problems to be Solved by the Invention] The conventional nonvolatile semiconductor device described above has the following serious drawbacks. In Fig. 6, curves A, B, and C are the IV curves of the memory transistor, and A is the point at which writing starts;
B and C show the ■-v curves at the point in time when writing progresses and electrons are injected into the floating gate of the memory transistor and the on-current decreases. The curved line shows the load curve, and VA, VB, and VC represent the column line potential at each point in time. VE indicates a column line potential during an erase operation, and VEi indicates the lowest potential of an erasable column line. VBDI and VBD2 indicate the drain-semiconductor substrate breakdown (avalanche breakdown) voltage of the written memory transistor. During write operation, the column line potential changes to VA as the write progresses.
From there, it goes up to VB and then to VC. At this time, if the column line potential exceeds the lowest erasable column line (ffVEi), other memory transistors connected to the same column line will start erasing. During writing, if the writing progresses and the column line potential exceeds VEi, the memory transistor M2
. . .M(1) erase starts, resulting in a decrease in the write margin and erroneous erasure.

Next, we will discuss problems during erasing operations. The drain-to-semiconductor substrate breakdown voltage of the written memory transistor is lowered by the negative charge of electrons injected into the floating gate. Therefore, it varies depending on the write level of the memory transistor. In FIG. 6, when the breakdown voltage between the drain and the semiconductor substrate is VBD, since it is higher than the erase time line potential VE, erasing proceeds without causing a 7-balancier breakdown between the train and the semiconductor substrate, but the breakdown voltage between the drain and the semiconductor substrate occurs. When the voltage is VBD2, it is lower than VE, which causes avalanche breakdown. Avalanche breakdown damages the gate oxide film near the drain, resulting in deterioration of write characteristics, read characteristics, erase characteristics, and rewritability. causing a decrease in the number of times.

It has been extremely difficult to take into account manufacturing variations and to optimize the problems during writing and erasing described above.

[Differences between the invention and the prior art] In contrast to the conventional non-volatile semiconductor memory device described above, the present invention scrubs the potential of the column line during a write operation with a voltage lower than the lowest potential of the column line that can be erased. The difference is that the column line potential at the time is clamped at a potential lower than the breakdown voltage between the memory transistor train and the semiconductor substrate.

[Means for Solving the Problems] The present invention provides a first field effect transistor (memory transistor) having a floating gate in which a drain electrode is connected to a column line, a source electrode is connected to a source line, and a gate electrode is connected to a row line. ), a second field effect transistor having a drain electrode connected to the first power supply, a source electrode connected to the column line at the first connection point, and having a write control signal as a gate input;
a third field effect transistor having a drain electrode connected to a second power supply, a source electrode connected to the first connection point, and having an erase control signal as a gate input; a first voltage limiter; and a drain electrode connected to the first connection point. The fourth field effect transistor has a source electrode connected to the first voltage limiter and receives erase control progress as a gate input, and a second voltage limiter connected to the first connection point.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

VPPI is the write power supply, Q2 is the MIS field effect transistor whose gate power is the output of the NOR circuit NOR1 which uses the write control signal and data signal, VPP2 is the erase power supply, and Q3 is the gate input of the erase control signal EC (over par). where J is the first connection point, Dl is the first diode, D2 is the second diode, and EC is the erase control signal EC (over par).
Q4 is the MIS field effect transistor with EC as the gate power, Y is the column line, Ml, M2...Mn is the memory transistor, S is the source line, Xl, X2...
Xn is a row line.

The first diode DI is a voltage limiter from VLI to about 16V, and the second diode D2 is a voltage limiter from VL2 to about 2V. During a write operation, the MIS field effect transistor Q2 turns on and transmits the write power supply VPPI to the column line Y. However, since the erase control signal EC is at a high level, the MIS field effect transistor Q4 turns on and the column line potential changes to the second column line. It is clamped at VL2 by diode D2.

Next, during the erase operation, the erase control signal EC (over par) becomes high level, the MIS field effect transistor Q3 is turned on, and the erase power supply VPP2 is transmitted to the column line, but the column line potential is clamped at VLI by the first diode D1. Ru. At this time, since the erase control signal EC is at a low level, the MIS field effect transistor Q4 is turned off, so that the second diode D2
does not operate as a voltage limiter.

Next, explanation will be given according to FIG. Curves A and C are the IV curves of the memory transistor, A indicates the writing start point,
C shows the I-7 curve at the time when writing has progressed. L
is the load curve. When writing starts, the column line potential becomes V
The voltage rises from A, but VL increases due to the second diode D2.
It is clamped at 2 to about 2 to V and does not rise any higher. VL
2 is lower than the lowest potential VEi of the erasable column line - about 14 V, so there is no problem of lowering the write level or erroneous erasing. During the erase operation, the column line potential is set to V by the first diode.
It is clamped at about 16V from LI. VLl is the drain-semiconductor substrate breakdown voltage VBD~1 of the memory transistor
Since it is lower than 8V, no avalanche breakdown occurs. Therefore, there is no damage to the gate oxide film in the vicinity of the drain, and there is no problem such as deterioration of write characteristics, erase characteristics, read characteristics, and possible number of rewrites, and a highly reliable nonvolatile semiconductor memory device can be obtained.

Furthermore, it can be easily inferred that even if the first connection point J and the column line Y are connected via a selection transistor whose gate input is a column line selection signal, the invention is also included.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

Q6 is an MIS field effect transistor whose gate electrode is connected to the drain electrode and whose threshold value is approximately 16V, and operates as an erase special voltage limiter, and Q5 is an MIS field effect transistor whose gate electrode is connected to the drain electrode and whose threshold value is approximately 12V. It is an effect transistor and operates as a voltage limiter during writing.

[Effects of the Invention] As explained above, the present invention includes a first voltage limiter, a source electrode connected to the first voltage limiter, a drain electrode connected to a column line at a first connection point, and an erase control signal. The structure includes a field effect transistor as a gate input, and a second voltage limiter connected to the column line at the first connection point, so that the column line potential can be erased at the lowest level of the column line during a write operation. By clamping at a voltage lower than the potential, it is possible to completely prevent a decrease in the write level and erroneous erasing.Furthermore, the column line potential during erase operation is clamped at a potential lower than the breakdown voltage between the memory transistor train and the semiconductor substrate, resulting in avalanche break. Write characteristics, erase characteristics,
This has the effect of preventing deterioration of read characteristics, number of rewrites, etc., and providing a highly reliable nonvolatile semiconductor memory device.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the first embodiment of the present invention, Fig. 2 is a graph showing the characteristics of the first embodiment, Fig. 3 is a circuit diagram of the second embodiment of the invention, and Fig. 4 is a memory transistor. Cross-sectional structural diagram of
FIG. 5 is a circuit diagram of a conventional example, and FIG. 6 is a graph showing problems with the conventional example. VPPI, VPP2...power supply, PGM (over par)...write control signal, EC
(over par), EC... erasure control signal, Q2. Q
3. Q4゜Q5. Q6...MIS field effect transistor, D
I, D2...Diode, J...First connection point, Y...Column line, XI, X2. ...Xn... row line, S...
...source line, Ml, M2. ...Mn...memory transistor,
1... Semiconductor substrate, 2... Drain, 3... Source, 4... First gate oxide film, 5... Floating gate, 6... ...Second gate oxide film, 7...Control gate. Patent Applicant: NEC Corporation Representative, Patent Attorney Kiyoshi Kuwai - "Figure 5Figure 4" Figure 5

Claims (1)

[Claims] a first field effect transistor of a first conductivity type having a memory function, the drain electrode being connected to the column line, the source electrode being connected to the source line, and the gate electrode being connected to the row line; and the drain electrode being connected to a first power source. a first conductivity type second field effect transistor having a source electrode connected to the column line at a first connection point and having a write control signal as a gate input; a drain electrode connected to a second power source and a source electrode connected to the column line; a first voltage limiter;
a fourth field effect transistor of a first conductivity type, the drain electrode of which is connected to the first connection point, the source electrode of which is connected to the first voltage limiter, and whose gate input is an erase control signal; 1. A nonvolatile semiconductor memory device comprising: a second voltage limiter;