JPH0127306Y2 - - Google Patents

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Publication number
JPH0127306Y2
JPH0127306Y2 JP1984095236U JP9523684U JPH0127306Y2 JP H0127306 Y2 JPH0127306 Y2 JP H0127306Y2 JP 1984095236 U JP1984095236 U JP 1984095236U JP 9523684 U JP9523684 U JP 9523684U JP H0127306 Y2 JPH0127306 Y2 JP H0127306Y2
Authority
JP
Japan
Prior art keywords
signal
input
terminal
relay contact
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1984095236U
Other languages
Japanese (ja)
Other versions
JPS6114546U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984095236U priority Critical patent/JPS6114546U/en
Publication of JPS6114546U publication Critical patent/JPS6114546U/en
Application granted granted Critical
Publication of JPH0127306Y2 publication Critical patent/JPH0127306Y2/ja
Granted legal-status Critical Current

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  • Monitoring And Testing Of Transmission In General (AREA)

Description

【考案の詳細な説明】 (技術分野) 本考案は信号折り返し回路の改良に関するもの
である。
[Detailed Description of the Invention] (Technical Field) The present invention relates to an improvement of a signal folding circuit.

(従来技術とその問題点) 従来この種の信号折り返し(以下ループと略
す)回路は第2図に示すように、非ループ中はリ
レーが不動作で、ループ監視用リレー接点7が開
放できる。よつて負論理素子5にはプルアツプ抵
抗9により電圧Eが入力され、ループ監視出力端
子11に論理信号“0”が出力される。一方ルー
プ中はリレーが動作中であり、リレー接点7がア
ースに接続されて負論理素子5にOVが入力さ
れ、ループ監視出力端子11に論理信号“1”が
出力される。以上のようにループ監視を行なうに
は、ループ回路用のリレー接点6,8の他にリレ
ー接点7が必要となり、リレーが高価でかつリレ
ーが大きくなる欠点があつた。また、ループ回路
用リレー接点6,8とリレー接点7が別々のた
め、ループ用リレー接点6,8が動作し、リレー
接点7が不動作となる場合、誤まつたループ監視
出力信号を出力する可能性があつて信頼性に乏し
いものであつた。
(Prior art and its problems) Conventionally, as shown in FIG. 2, in this type of signal return (hereinafter abbreviated as loop) circuit, the relay is inactive during the non-loop period, and the loop monitoring relay contact 7 can be opened. Therefore, the voltage E is input to the negative logic element 5 through the pull-up resistor 9, and a logic signal "0" is output to the loop monitoring output terminal 11. On the other hand, during the loop, the relay is in operation, the relay contact 7 is connected to the ground, OV is input to the negative logic element 5, and a logic signal "1" is output to the loop monitoring output terminal 11. In order to monitor the loop as described above, a relay contact 7 is required in addition to the relay contacts 6 and 8 for the loop circuit, which has the disadvantage that the relay is expensive and large. In addition, since the loop circuit relay contacts 6 and 8 and the relay contact 7 are separate, if the loop relay contacts 6 and 8 operate and the relay contact 7 does not operate, an erroneous loop monitoring output signal is output. It was a possibility, but it was unreliable.

(目的) 本考案は、ループ回路用接点にてループ監視信
号を出力することを特徴とし、その目的はループ
回路を小さくし、安価に、かつ高信頼で実現する
ことにある。
(Purpose) The present invention is characterized by outputting a loop monitoring signal at a loop circuit contact, and its purpose is to reduce the size of the loop circuit and realize it at low cost and with high reliability.

(構成) そのために本考案は、入力信号切替リレー接点
で入力線路を切り離し、出力信号切替リレー接点
で出力線路を切り離すと共に信号入力端子と信号
出力端子とを接続する信号折り返し回路におい
て、前記入力信号切替リレー接点のコモン端子と
接地間に抵抗R1を設け、前記入力線路が切り離
されたときに前記コモン端子と接触するメーク端
子と電源Eとの間に抵抗R2を設け、また前記コ
モン端子に入力しきい値電圧VTHなる負論理素子
の入力端を接続して構成し、前記入力線路を切り
離したときの前記メーク端子のVio=E/
{(R2/R1)+1}がVio<VTHとなるように、各素
子を選定した信号折り返し監視回路を具備させる
ようにしたものである。
(Structure) To achieve this, the present invention provides a signal return circuit in which an input signal switching relay contact disconnects an input line, an output signal switching relay contact disconnects an output line, and a signal input terminal and a signal output terminal are connected. A resistor R 1 is provided between the common terminal of the switching relay contact and ground, a resistor R 2 is provided between the power source E and a make terminal that comes into contact with the common terminal when the input line is disconnected, and the common terminal is configured by connecting the input end of a negative logic element having an input threshold voltage V TH to the input line, and when the input line is disconnected, the make terminal V io =E/
Each element is provided with a signal return monitoring circuit selected so that {(R 2 /R 1 )+1} satisfies V io <V TH .

(実施例) 第1図に本考案のループ回路の一実施例を示
す。1は信号出力端子、2は信号入力端子、3は
信号出力回路、4は信号入力回路、5は負論理素
子、6は信号出力切替リレー接点、8は信号入力
切替リレー接点、9はプルアツプ抵抗(以下R1
と略す)、10は信号入力終端抵抗(以下R2と略
す)、11はループ監視出力端子である。リレー
が不動作中は信号出力回路3からの信号が、信号
出力切替リレー接点6を経由して信号出力端子1
へ出力され、信号入力端子2からの信号が信号入
力切替リレー接点8を経由し、R2抵抗10にて
終端されて信号入力回線4に入力される。このと
き信号入力切替リレー接点8が不動作であるた
め、負論理素子5にはR1抵抗9を介して負論理
素子5のしきい値電圧より高い電圧Eが入力さ
れ、ループ監視出力端子11には信号入力端子2
から信号出力端子1へループされていないことを
示す論理信号“0”が出力される。リレーが動作
中は信号入力端子2からの信号が信号出力切替リ
レー接点6を経由して信号出力端子1へ出力され
る。このとき信号入力切替リレー接点8が動作し
ているため、負論理素子5へ入力される電圧Vio
はE/(R1/R2)+1となる。ここで負論理素子のし きい値電圧VTHとE/(R1/R2)+1の比がVTH> E/(R1/R2)+1となるように、R1及びR2を選定 しておけば、負論理素子5はVioをLOWと判別し、
ループ監視出力端子11には信号入力端子2から
信号出力端子1へループされていることを示す論
理信号“1”が出力される。
(Embodiment) FIG. 1 shows an embodiment of the loop circuit of the present invention. 1 is a signal output terminal, 2 is a signal input terminal, 3 is a signal output circuit, 4 is a signal input circuit, 5 is a negative logic element, 6 is a signal output switching relay contact, 8 is a signal input switching relay contact, 9 is a pull-up resistor (Hereafter R 1
10 is a signal input termination resistor (hereinafter abbreviated as R2 ), and 11 is a loop monitoring output terminal. When the relay is not operating, the signal from the signal output circuit 3 is sent to the signal output terminal 1 via the signal output switching relay contact 6.
The signal from the signal input terminal 2 passes through the signal input switching relay contact 8, is terminated at the R2 resistor 10, and is input to the signal input line 4. At this time, since the signal input switching relay contact 8 is inactive, a voltage E higher than the threshold voltage of the negative logic element 5 is input to the negative logic element 5 via the R1 resistor 9, and the loop monitoring output terminal 11 has signal input terminal 2
A logic signal "0" indicating that looping is not performed is outputted from the signal output terminal 1. While the relay is in operation, a signal from the signal input terminal 2 is outputted to the signal output terminal 1 via the signal output switching relay contact 6. At this time, since the signal input switching relay contact 8 is operating, the voltage V io input to the negative logic element 5
becomes E/(R 1 /R 2 )+1. Here, R 1 and R 2 are set so that the ratio of the threshold voltage V TH of the negative logic element and E/(R 1 /R 2 )+1 is V TH > E/(R 1 /R 2 ) +1 . If selected, the negative logic element 5 determines V io as LOW ,
A logic signal "1" indicating that the signal is looped from the signal input terminal 2 to the signal output terminal 1 is output to the loop monitoring output terminal 11.

(効果) 以上説明した如く本考案によれば、ループ回路
用のリレー接点でループ状態の監視を行なうこと
が可能となるため、リレー接点回路の数を減らす
ことによつて、リレーの価格及び大きさを大幅に
低減でき、またループ回路用のリレー接点信号が
直接ループ監視出力信号となるため、監視出力信
号の信頼度を増すことができる。
(Effects) As explained above, according to the present invention, it is possible to monitor the loop status using the relay contacts for the loop circuit, so by reducing the number of relay contact circuits, the cost and size of the relay can be reduced. Furthermore, since the relay contact signal for the loop circuit directly becomes the loop monitoring output signal, the reliability of the monitoring output signal can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のループ回路、第2
図は従来のループ回路である。 1……信号出力端子、2……信号入力端子、5
……負論理素子、6……信号出力切替リレー接
点、8……信号入力切替リレー接点、9……プル
アツプ抵抗、10……受信信号終端抵抗、11…
…ループ監視信号出力端子。
Figure 1 shows a loop circuit according to an embodiment of the present invention;
The figure shows a conventional loop circuit. 1...Signal output terminal, 2...Signal input terminal, 5
...Negative logic element, 6...Signal output switching relay contact, 8...Signal input switching relay contact, 9...Pull-up resistor, 10...Receiving signal terminating resistor, 11...
...Loop monitoring signal output terminal.

Claims (1)

【実用新案登録請求の範囲】 入力信号切替リレー接点で入力線路を切り離
し、出力信号切替リレー接点で出力線路を切り離
すと共に信号入力端子と信号出力端子とを接続す
る信号折り返し回路において、前記入力信号切替
リレー接点のコモン端子と接地間に抵抗R1を設
け、前記入力線路が切り離されたときに前記コモ
ン端子と接触するメーク端子と電源Eとの間に抵
抗R2を設け、また前記コモン端子に入力しきい
値電圧VTHなる負論理素子の入力端を接続して構
成し、前記入力線路を切り離したときの前記メー
ク端子の電圧Vio=E/(R2/R1)+1がVio<VTHと なるように、各素子を選定した信号折り返し監視
回路を具備させたことを特徴とする信号折り返し
回路。
[Claims for Utility Model Registration] In a signal folding circuit in which an input signal switching relay contact disconnects an input line, an output signal switching relay contact disconnects an output line, and connects a signal input terminal and a signal output terminal, the input signal switching circuit A resistor R1 is provided between the common terminal of the relay contact and the ground, a resistor R2 is provided between the make terminal and the power source E, which contacts the common terminal when the input line is disconnected, and a resistor R2 is provided between the power source E and the common terminal. The input terminal of a negative logic element having an input threshold voltage V TH is connected, and the voltage at the make terminal when the input line is disconnected is V io =E/(R 2 /R 1 )+1 is V io A signal loopback circuit characterized by comprising a signal loopback monitoring circuit in which each element is selected such that <V TH .
JP1984095236U 1984-06-27 1984-06-27 signal loop circuit Granted JPS6114546U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984095236U JPS6114546U (en) 1984-06-27 1984-06-27 signal loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984095236U JPS6114546U (en) 1984-06-27 1984-06-27 signal loop circuit

Publications (2)

Publication Number Publication Date
JPS6114546U JPS6114546U (en) 1986-01-28
JPH0127306Y2 true JPH0127306Y2 (en) 1989-08-15

Family

ID=30654263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984095236U Granted JPS6114546U (en) 1984-06-27 1984-06-27 signal loop circuit

Country Status (1)

Country Link
JP (1) JPS6114546U (en)

Also Published As

Publication number Publication date
JPS6114546U (en) 1986-01-28

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