JPH01269124A - Photographic printer - Google Patents

Photographic printer

Info

Publication number
JPH01269124A
JPH01269124A JP63097614A JP9761488A JPH01269124A JP H01269124 A JPH01269124 A JP H01269124A JP 63097614 A JP63097614 A JP 63097614A JP 9761488 A JP9761488 A JP 9761488A JP H01269124 A JPH01269124 A JP H01269124A
Authority
JP
Japan
Prior art keywords
memory
printing
contents
data
picture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63097614A
Other languages
Japanese (ja)
Inventor
Michinao Osawa
大澤 道直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63097614A priority Critical patent/JPH01269124A/en
Publication of JPH01269124A publication Critical patent/JPH01269124A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dot-Matrix Printers And Others (AREA)
  • Digital Computer Display Output (AREA)
  • Television Signal Processing For Recording (AREA)
  • Storing Facsimile Image Data (AREA)

Abstract

PURPOSE:To synthesize a signal to input without having a picture memory and to obtain a picture hard copy by storing and operating picture element data with two pairs of the shift register, sending the result into a buffer memory and executing the photographic printing. CONSTITUTION:The title printer is composed of an A/D converter 1 to binarize a video signal, registers 2 and 3 to temporarily store digital data, a counter 4 to designate the position to fetch a picture, a switch 5 to switch the contents to pass directly the and the contents to pass the arithmetic result for the contents of a shift register 2, a computing element 6 to execute the operation such as interpolarion, a memory 7 to store the data of plural lines, a processing part 8 to generate the address control signal of the memory, a circuit 9 to generate a clock synthesized to a synthesizing signal, a data processing part 10 to execute the photographic printing and a part 11 to photographic-print. Thus, the photographic printing synthesized to the inputted video signal can be executed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は主にパーソナルコンピュータ、テレビ、VTR
、スチルビデオ、レーザーディスク等の映像信号をハー
ドコピーする印画装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is mainly applicable to personal computers, televisions, VTRs, etc.
The present invention relates to a printing device for hard copying video signals of still videos, laser discs, etc.

[従来の技術] 従来のパーソナルコンピュータ等の映像信号をハードコ
ピーする印画装置においてはデジタル化された映像信号
を一旦画像メモリに記憶しメモリの内容を印画装置の速
度に応じて読み出し印画するのが一般的である。またメ
モリを持たないシステムにおいては二組のバッファメモ
リを持って互いに同期を取りながら印画するのが一般的
である。
[Prior Art] Conventional printing devices that hard copy video signals from personal computers and the like temporarily store digitized video signals in an image memory, read out the contents of the memory in accordance with the speed of the printing device, and then print. Common. Furthermore, in systems without memory, it is common to have two sets of buffer memories and print while synchronizing with each other.

[発明が解決しようとする課題] 前記のようなシステムをより簡略化して、入力している
映像信号に同期した印画を行うために、更には印画ライ
ン数の補間、水増し、データ補正等の処理を実施して簡
略化したシステムで印画する為にはメモリを最小限にと
どめることが重要になる。
[Problems to be Solved by the Invention] In order to further simplify the system described above and perform printing in synchronization with the input video signal, processing such as interpolation of the number of printing lines, padding, data correction, etc. In order to carry out printing with a simplified system, it is important to keep memory to a minimum.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係わる印画装置は、2組のシフトレジスタによ
り画素データを記憶し演算させ、その結果をバッファメ
モリに送り印画を実施することにある。
The printing apparatus according to the present invention stores and calculates pixel data using two sets of shift registers, and sends the results to a buffer memory for printing.

[実 施 例] 第1図は本発明の実施例を示すブロック図であり第2図
は画面上での本発明の説明のための図であり第3図は実
施例のタイミングチャートを説明する図である。第1図
でA/D1は映像信号を二値化するA/D変換器であり
、シフトレジスタ2及びシフトレジスタ3はデジタルデ
ータを一時記憶するレジスタ、カウンタ4は画面を取り
込む位置を指定するためのカウンタ、SW5はシフトレ
ジスタ2の内容を直接通過させるものと演算結果を通す
ものとを切り換λる為のスイッチ、演算器6は補間等の
演算をする演算器、メモリ7はラインバッファとして印
画の複数ラインのデータを記憶する為のメモリ、アドレ
ス処理8はメモリのアドレス制御信号を発生する処理部
、クロック9は同期信号に同期したクロックを発生する
ための回路、印画処理10は印画のためのデータ処理部
、メカニズム11は印画する部分である。
[Embodiment] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the present invention on a screen, and Fig. 3 is a timing chart of the embodiment. It is a diagram. In Figure 1, A/D1 is an A/D converter that binarizes the video signal, shift register 2 and shift register 3 are registers that temporarily store digital data, and counter 4 is for specifying the position to capture the screen. SW5 is a switch for switching between passing the contents of the shift register 2 directly and passing the calculation results, the computing unit 6 is a computing unit that performs calculations such as interpolation, and the memory 7 is used as a line buffer. A memory for storing multiple lines of data for printing, an address processing section 8 for generating memory address control signals, a clock 9 for generating a clock synchronized with a synchronization signal, and a printing processing section 10 for printing. The data processing unit and mechanism 11 are the parts that print images.

信号の流れに従って詳細に説明する。入力されるアナロ
グ映像信号は印画処理する色に応じて選択され(図示せ
ず)1のA/D変換器に入力されデジタルデータに変換
される。2のシフトレジスタは例えば5×6ビツトで構
成して5画素6ビツトのデータを連続的に取り込む、即
ち第2図のCRT等の画面に於ける図において水平方向
である横に並んだ5画素(横l縦lの5点)を取り込む
1次に次ラインの水平走査ラインのデータ(横2縦2)
を再度取り込み両ラインのデータがシフトレジスタ2及
び3に記憶される0両データの内容から6の演算器によ
り縦ライン補間、横方向位置補正等の演算処理を実施す
る。これらの演算処理は1次ラインのサンプリング期間
までの期間で行い、それまでに次段のメモリ7に転送し
てしまう、メモリ7ではシフトレジスタより演算結果の
データを書き込むことと印画処理回路lOに応じた読み
だしをタイムシェアで実施する。このメモリのアドレス
制御は8の処理回路で実施する。またアドレス処理は入
力する同期信号に応じたクロック発生回路9により行う
This will be explained in detail according to the signal flow. The input analog video signal is selected according to the color to be printed and input to one A/D converter (not shown), where it is converted into digital data. For example, the shift register No. 2 is composed of 5 x 6 bits and continuously takes in data of 5 pixels and 6 bits, that is, 5 pixels lined up horizontally in the diagram of a screen such as a CRT as shown in Fig. 2. (5 points horizontally and vertically l) The data of the horizontal scanning line of the primary line (2 horizontally 2 vertically)
is taken in again, and the data of both lines are stored in the shift registers 2 and 3. From the contents of the 0 and 0 data, the arithmetic unit 6 performs arithmetic processing such as vertical line interpolation and horizontal position correction. These calculation processes are performed during the period up to the sampling period of the primary line, and are transferred to the next stage memory 7 by then. In the memory 7, the data of the calculation results is written from the shift register and the data is transferred to the print processing circuit lO. Perform appropriate readings on a timeshare. This memory address control is performed by eight processing circuits. Further, address processing is performed by a clock generation circuit 9 according to an input synchronization signal.

第2図における印画処理の順番は水平走査にしたがって
各ライン5ドツトずつサンプリングをして行き垂直方向
に下まで来たら次垂直ライン2に移る0次ラインでは、
演算処理の関係から、重複した垂直ラインでサンプリン
グを実施する場合もある。メモリ7には垂直方向の5ラ
インまたは4ラインのバッファとして一時記憶する。垂
直方向に左から右にサンプリングが終了すると印画にお
ける一色が終了し、入力の映像信号の色信号を変えて次
の色を実施する。一般的には3色の色の面順次を繰り返
すことにより一枚の印画が終了する。
The order of the printing process in Fig. 2 is as follows: 5 dots are sampled from each line according to horizontal scanning, and when it reaches the bottom in the vertical direction, the next vertical line 2 is started.
Due to computational processing considerations, sampling may be performed on overlapping vertical lines. The memory 7 temporarily stores the data as a 5-line or 4-line buffer in the vertical direction. When sampling is completed from left to right in the vertical direction, one color in the print is completed, and the next color is executed by changing the color signal of the input video signal. Generally, one sheet of printing is completed by repeating the three colors sequentially.

第3図は第1図のブロック図におけるタイミングチャー
トを示す、Aは水平同期信号でありシフトレジスタへの
取り込みは水平周期に同期して実施する。Bの5(nl
、sfn+ 1)、S(n+ 2)はシフトレジスタに
取り込むタイミングを示し取り込む場所に応じて変化し
てゆく、この位置のコントロールはカウンタ4がうけも
つ、Cの斜線の部分は演算器6での演算可能期間を示す
、Dはシフトレジスタからメモリへの転送期間を示す、
 T (m)、T (m+1)、T(m+2)、は転送
可能な期間であり、印画処理から、メモリ7への書き込
み可能期間から決定される。この期間に演算処理が終了
しているときに転送が実施される。従ってCの演算期間
はDの1転送期間間を残して、終了する必要がある。こ
の条件により、連続したサンプリングが実施される。
FIG. 3 shows a timing chart in the block diagram of FIG. 1. A is a horizontal synchronizing signal, and the input into the shift register is performed in synchronization with the horizontal period. B's 5 (nl
, sfn+ 1), and S(n+ 2) indicate the timing of loading into the shift register and change depending on the loading location.The counter 4 is responsible for controlling this position. Indicates the operable period, D indicates the transfer period from the shift register to the memory,
T(m), T(m+1), and T(m+2) are periods during which transfer is possible, and are determined from a period during which data can be written into the memory 7 from printing processing. Transfer is performed when arithmetic processing is completed during this period. Therefore, the calculation period of C must be completed with one transfer period of D remaining. Under this condition, continuous sampling is performed.

本実施例に於いては、サンプリング数を5画素ずつで説
明したが、印画のスピードに応じて、さらにはメモリの
構成に応じて、如何なる画素毎にサンプリングしても、
同様に構成することができる。また、実施例では、3色
面順次の場合の例で示したが、ライン順次で切り換えて
も同様である。また、メモリの前にラッチ回路をおくと
、メモリへの転送に、より余裕が持て同様に考えること
ができる。
In this embodiment, the sampling number is 5 pixels at a time, but depending on the printing speed and the memory configuration, sampling may be performed for any number of pixels.
It can be configured similarly. Further, in the embodiment, an example in which three color planes are sequentially used is shown, but the same effect can be obtained even if the switching is performed line sequentially. Also, if a latch circuit is placed in front of the memory, there will be more margin for transfer to the memory, which can be considered similarly.

[発明の効果] この発明は、以上説明したように画面メモリを持たずに
入力する信号に同期を取り画面ハードコピーを得ること
が可能になる。
[Effects of the Invention] As explained above, the present invention makes it possible to obtain a hard copy of the screen by synchronizing with input signals without having a screen memory.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるプリント装置のブロック図。 第2図は本発明の詳細な説明する図。 第3図は本発明の詳細な説明するタイミングチャート図
。 ■・・・・A/D変換器 2.3・・シフトレジスタ 6・・・・演算器 7・・・・バッファメモリ 11・・・・印画メカニズム 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴 木 喜三部(化1名)第2阿
FIG. 1 is a block diagram of a printing apparatus according to the present invention. FIG. 2 is a diagram illustrating the present invention in detail. FIG. 3 is a timing chart diagram explaining the present invention in detail. ■...A/D converter 2.3...Shift register 6...Calculating unit 7...Buffer memory 11...Printing mechanism and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Suzu Kisanbe (1 person) 2nd A

Claims (1)

【特許請求の範囲】[Claims]  入力された映像信号デジタル化するA/D変換器、複
数画素を高速で記憶するシフトレジスタを二組、該シフ
トレジスタの内容をもとに演算する演算器、シフトレジ
スタの取り込みのアドレスを発生するカウンタ群、演算
内容を格納し更に印画のためのバッファとするメモリ、
メモリのアドレス等の制御をするカウンタ群、メモリの
内容を印画処理する処理回路群、印画メカニズムを具備
し入力された映像信号と同期とって印画することを特徴
とする印画装置。
An A/D converter that digitizes the input video signal, two sets of shift registers that store multiple pixels at high speed, an arithmetic unit that performs calculations based on the contents of the shift registers, and generates addresses for loading the shift registers. A group of counters, a memory that stores calculation contents and also serves as a buffer for printing;
A printing device comprising a counter group for controlling memory addresses, etc., a processing circuit group for printing the contents of the memory, and a printing mechanism, and printing in synchronization with an input video signal.
JP63097614A 1988-04-20 1988-04-20 Photographic printer Pending JPH01269124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63097614A JPH01269124A (en) 1988-04-20 1988-04-20 Photographic printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63097614A JPH01269124A (en) 1988-04-20 1988-04-20 Photographic printer

Publications (1)

Publication Number Publication Date
JPH01269124A true JPH01269124A (en) 1989-10-26

Family

ID=14197085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63097614A Pending JPH01269124A (en) 1988-04-20 1988-04-20 Photographic printer

Country Status (1)

Country Link
JP (1) JPH01269124A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164852A (en) * 1986-12-16 1992-11-17 Semiconductor Energy Laboratory Co., Ltd. Method of orientating a ferroelectric liquid crystal layer by AC electric field

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164852A (en) * 1986-12-16 1992-11-17 Semiconductor Energy Laboratory Co., Ltd. Method of orientating a ferroelectric liquid crystal layer by AC electric field

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