JPH01268045A - Electronic component - Google Patents
Electronic componentInfo
- Publication number
- JPH01268045A JPH01268045A JP9539088A JP9539088A JPH01268045A JP H01268045 A JPH01268045 A JP H01268045A JP 9539088 A JP9539088 A JP 9539088A JP 9539088 A JP9539088 A JP 9539088A JP H01268045 A JPH01268045 A JP H01268045A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- printed circuit
- flat
- mounting
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 abstract description 16
- 238000005476 soldering Methods 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract 3
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばフラットパック形パッケージ集積回路
等の・Y面付りリードを備えた多足電子部品に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-legged electronic component, such as a flat-pack package integrated circuit, having Y-faced leads.
底面及び頂面か平行平板状で、かつ、はんだ付Gプ等用
のリード端子が平板に平行に突出し・ているこの種の多
足電子部品として、いわゆるフラットパック形パッケー
ジ(以下、フラットパッケージと略称する)の集積回路
(以下、ICと略称する)があり、第2図に、例えば実
開昭62−162870号公報に開示されたこの種のI
Cの部分平面図を示す。This type of multi-legged electronic component, in which the bottom and top surfaces are parallel flat plates, and lead terminals for soldering connectors etc. protrude parallel to the flat plate, is called a so-called flat pack package (hereinafter referred to as flat package). There is an integrated circuit (hereinafter abbreviated as IC) of the type shown in FIG.
A partial plan view of C is shown.
6はフラットパッケージIC(fill断として示す)
、2は各平面付けリードフレーム端子、3は、それぞわ
の端子2用の各導体ランド、4は、該IC6を実装すべ
きプリント回路基板のレジスト穴、8は、はんだを示す
。6 is a flat package IC (shown as a fill cut)
, 2 indicates each flat lead frame terminal, 3 indicates each conductor land for each terminal 2, 4 indicates a resist hole of the printed circuit board on which the IC 6 is to be mounted, and 8 indicates solder.
7は、平面付けリード列の各最外側の端Y−2部にそれ
ぞれ各外側に広く形成したはんだ溜りランド部である。Reference numeral 7 denotes a solder pool land portion formed widely outwardly at each outermost end Y-2 of each flat lead row.
こねは、該[C6をプリント回路基板上に実装するに際
して、ペースト状のはんだを各導体ランド3.7に塗布
したのち、該IC6の各リード2を該各ランドに位置合
せして、レーザ光線もしくは赤外線の照射加熱等により
、それぞれの両者をはんだ接合する場合、上記リード列
の中間部の各ランド部3においては、それぞわ隣接する
各ランド間にはみ出したペースト状はんだは、溶融の際
の凝集力(表面張力)により、それぞれ両側のランド部
に引寄せられて正常のはんだ接合が行われるが、最外側
のランド部が、中間部の各ランド3と同一形状であると
、外側にはみ出したペースト状はんだは、前記のような
溶融時の凝集力が片側にしか作用しないため不足して基
板上に残留し、固化してボール状となったはんだが移動
して、プリント回路基板上の短絡や絶縁不良等を生ずる
可能性を防止するために設けられたものである。When mounting the [C6 on a printed circuit board, paste solder is applied to each conductor land 3.7, each lead 2 of the IC6 is aligned to each land, and a laser beam is applied. Alternatively, when the two are soldered together by infrared irradiation heating, etc., in each land portion 3 in the middle of the lead row, the paste-like solder that protrudes between each adjacent land will be removed during melting. Due to the cohesive force (surface tension) of , they are attracted to the lands on both sides and a normal solder joint is performed, but if the outermost land has the same shape as each land 3 in the middle, The overflowing paste-like solder remains on the board because the cohesive force during melting as described above only acts on one side, and the solder solidifies into a ball shape and moves, causing the solder to stick to the printed circuit board. This is provided to prevent the possibility of short circuits or poor insulation.
(発明が解決しようとする課題)
しかしながら、以上のような従来例にあっては、前記は
んだ溜りランド部7などIC6の各隅部に、本来は不必
要なランドパターン7面積を要し、この分のプリント回
路基板面積が利用できないため、高密度実装化に適して
いる薄形のフラットパッケージICの本来の利点を、十
分に発揮できないという問題点があった。(Problem to be Solved by the Invention) However, in the conventional example as described above, an unnecessary area of the land pattern 7 is required at each corner of the IC 6, such as the solder pool land portion 7. There was a problem in that the inherent advantages of thin flat package ICs, which are suitable for high-density packaging, could not be fully exploited because the printed circuit board area could not be utilized.
その他に、フラットパッケージICをフロー槽に流す時
、流す方向によっては、フラットパッケージICのピン
の端部に、はんだブリッジを生じやすくなるという問題
点があった。Another problem is that when a flat package IC is poured into a flow tank, depending on the direction of flow, solder bridges are likely to occur at the ends of the pins of the flat package IC.
本発明は、以上のような従来例の問題点にかんがみてな
されたもので、フラットパッケージIC等のプリント回
路基板等への実装の、より高密度化を可能とする手段の
提供を目的としている。The present invention has been made in view of the problems of the conventional examples as described above, and aims to provide a means that enables higher density mounting of flat package ICs and the like on printed circuit boards, etc. .
このため、本発明においては、フラットパックIC等の
電子部品の各平面材はリード列の最外端を、実装上の非
接続(Non Connection)端子(略してN
Cf4子)として形成することにより、前記目的を達成
しようとするものである。Therefore, in the present invention, each planar member of an electronic component such as a flat pack IC connects the outermost end of the lead row to a non-connection terminal (abbreviated as N) on mounting.
The purpose is to achieve the above object by forming a Cf4 child).
以上のような構成により、平面材はリード列の最外端部
の端子は、プリント基板等への実装に使用しないように
したため、この部において前記のような不具合を生ずる
ことがないため、従来のこの部のランド面積等が不要と
なり、基板のレジスト穴の従来の各隅部面積を有効に利
用できるため、より高密度の実装が可能となり、かつ、
はんだ付は作業も効率化される。With the above configuration, the terminals at the outermost ends of the lead rows of the planar material are not used for mounting on printed circuit boards, etc., so the above-mentioned problems do not occur in this part, so it is possible to This eliminates the need for land areas, etc., and allows effective use of the conventional corner areas of the resist holes on the board, making it possible to implement higher-density mounting.
Soldering also makes work more efficient.
以下に、本発明を実施例に基づいて説明する。 The present invention will be explained below based on examples.
第1図に、本発明の特徴を最もよく表わすフラットパッ
ケージICの一実施例の、誼記従来例第2図に対応する
部分平面図を示し、第2図におけると同一(相当)構成
要素は、同一符号で表わす。FIG. 1 shows a partial plan view of an embodiment of a flat package IC that best represents the features of the present invention, corresponding to FIG. 2 of the conventional example, and the same (equivalent) components as in FIG. , are represented by the same symbols.
(構成)
第1図において、6はフラットパッケージIC11は、
本発明により、各平面材はリード列の最外端に設けたN
C(不接続)端子、2は各リードフレーム端子、3は、
それぞれ端子2用の各ランド、4aは、実装すべきプリ
ント基板のレジスト穴、5は、リード列最外端部に生じ
たはんだのブリッジ部である。(Configuration) In FIG. 1, 6 indicates a flat package IC 11.
According to the present invention, each plane member has a N
C (no connection) terminal, 2 is each lead frame terminal, 3 is,
Each land for the terminal 2, 4a, is a resist hole of a printed circuit board to be mounted, and 5 is a solder bridge portion formed at the outermost end of the lead row.
(作用)
つぎに、上記構成において、プリント回路基板上への実
装に際して、リードフレーム2のはんだ付けを行うとき
、既述のように、−数的に、リード列の最外端ではんだ
ブリッジング部5が多発する可能性があるが、この端子
1はNC端子であるため、これらのはんだブリッジは、
本来の電気回路上に影響を及ぼすことがなく、また、該
フラットパッケージICを実装すべきプリント回路基板
のレジスト穴4aの各隅部面積を従来例に比して有効に
使用し得るため、その分、実装密度を高めることができ
、また、はんだ付は効率も向上して、製造コストの低減
に寄与することができる。(Function) Next, in the above configuration, when soldering the lead frame 2 when mounting it on a printed circuit board, as described above, - numerically, solder bridging is performed at the outermost end of the lead row. Part 5 may occur frequently, but since this terminal 1 is an NC terminal, these solder bridges are
This method has no effect on the original electric circuit, and the area of each corner of the resist hole 4a of the printed circuit board on which the flat package IC is mounted can be used more effectively than in the conventional example. Therefore, the packaging density can be increased, and the efficiency of soldering can also be improved, contributing to a reduction in manufacturing costs.
(発明の効果〕
以上説明したように、本発明によれば、フラットパック
IC等の電子部品の平面材はリード列の最外端をNC端
子とするよう構成したため、各隅部面積の利用により、
プリント回路基板等への、すり高密度実装化が可能とな
り、はんだ付は作業の効率も向上する。(Effects of the Invention) As explained above, according to the present invention, since the planar material of electronic components such as flat pack ICs is configured so that the outermost end of the lead row is the NC terminal, the area of each corner can be utilized. ,
It enables high-density mounting on printed circuit boards, etc., and improves the efficiency of soldering work.
第1図は、本発明によるフラットパッケージICの一実
施例の部分平面図、第2図は、従来例の第1図相当図で
ある。
1・・・・・・NC端子
2・・・・・・リードフレーム端子
3・・・・・・ランド
5・・・・・・はんだブリッジ部
6・・・・・・フラットパッケージI C(?E子子部
品出出願人キャノン株式会社
6フラツトハーJγ−ヨクI(−
の−実施料の部分平面図
笥 1 図FIG. 1 is a partial plan view of an embodiment of a flat package IC according to the present invention, and FIG. 2 is a view corresponding to FIG. 1 of a conventional example. 1...NC terminal 2...Lead frame terminal 3...Land 5...Solder bridge portion 6...Flat package IC (? E Child Parts Applicant Canon Co., Ltd. 6 Flat Hard Jγ-Yoku I (- Partial Plan View of Royalty Fee 1 Figure
Claims (1)
ジ集積回路等の多足電子部品において、前記各平面付け
リード列の各最外端をそれぞれ非接続端子として形成し
たことを特徴とする電子部品。1. A multi-legged electronic component such as a flat-pack packaged integrated circuit having rows of flat leads, characterized in that each outermost end of each row of flat leads is formed as a non-connection terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9539088A JPH01268045A (en) | 1988-04-20 | 1988-04-20 | Electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9539088A JPH01268045A (en) | 1988-04-20 | 1988-04-20 | Electronic component |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01268045A true JPH01268045A (en) | 1989-10-25 |
Family
ID=14136320
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9539088A Pending JPH01268045A (en) | 1988-04-20 | 1988-04-20 | Electronic component |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01268045A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5086335A (en) * | 1990-07-31 | 1992-02-04 | Hewlett-Packard Company | Tape automated bonding system which facilitate repair |
US5736792A (en) * | 1995-08-30 | 1998-04-07 | Texas Instruments Incorporated | Method of protecting bond wires during molding and handling |
-
1988
- 1988-04-20 JP JP9539088A patent/JPH01268045A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5086335A (en) * | 1990-07-31 | 1992-02-04 | Hewlett-Packard Company | Tape automated bonding system which facilitate repair |
US5736792A (en) * | 1995-08-30 | 1998-04-07 | Texas Instruments Incorporated | Method of protecting bond wires during molding and handling |
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