JPH01267767A - Data processing unit - Google Patents

Abstract

PURPOSE:To lower the frequency of a down load request to a host processor, to cause a memory to inexpensive, and to shorten even a restoration time at the time of a program destruction by providing a memory for a load module to each processor in which a program is loaded from the host processor. CONSTITUTION:Memories 19, 29 and 39 for load modules are provided for respective processors 15, 25 and 35 separately from main memories 16, 26 and 36, the program to be down-loaded from a host processor 11 is written to the memories 19, 29 and 39 for the load modules once, next, the program is read from the memories 19, 29 and 39 for the load modules by an IPL (Initial Program Load) processing, and it is written to the main memories 16, 26 and 36 of respective processors 15, 25 and 35. Thus, the restoration at the time of the program destruction can be speedily executed, and the inexpensiveness can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device in which a single host processor loads a program into a group of multiple processors.

[Conventional technology]

Figure 4 shows Mitsubishi Electric Technical Report Vol. 61 No. 4 (April 1987).
This figure shows a conventional data processing device as described on page 18 of the publication (January 25, 2013). In the figure, 11 is a host processor that centrally manages programs of a plurality of processors, which will be described later. 12 is a disk memory that stores each program of the plurality of processors. 13 is provided within the host processor 11, and 15. A download processing circuit that performs a download process when the host processor 11 loads a program to a target processor among the plurality of processors; 14 is a communication path connecting the host processor 11 and the plurality of processors; 15. 25.
Reference numeral 35 constitutes the plurality of processors to be loaded. In this case, there are three processors, each of which is a PU, a PU, and a PU. Processors numbered PU 3, 16, 26. 36 are the main memo in which the corresponding processor Is, 25. 35 programs are written! j, 17.27.37 are respectively provided in the corresponding processors 15.25.35, and 1 corresponding main memory 16.26. IPL (In1tia
l Program Load) processing circuit, 18°2
8.38 is the corresponding IPL processing circuit 17.27
．． This is a pushbutton switch that activates 37.

Next, the operation will be explained. For example, when the IPL processing circuit 11 is activated by the IPL activation push button switch 18 of the processor 15, the IPL processing circuit 1γ issues a download request to the host processor 11 via the communication path 14. In the host processor 11, the download processing circuit 13 is activated in response to a download request from the processor 15, reads the target program from the disk memory 12, and downloads the program to the processor f15 via the first communication path 14. processor 1
The IPL processing circuit 17 of No. 5 writes the downloaded program into the main memory 16.

[Problem to be solved by the invention]

Conventional data processing devices are configured as described above, so in order to be able to sufficiently respond to download requests from multiple processors 15.25゜35 at the same time, the host processor 11 and disk The performance of the memory 12 needs to be high speed and large capacity, which has the problem of being expensive.

In addition, in the event that a program is destroyed during program debugging, it is necessary to download it from the host processor 11. Therefore, if a processing bottleneck occurs in the host processor 11, the entire system of the data processing device must be restored. The problem was that it took a lot of time.

This invention was made to solve the above-mentioned problems, and it quickly recovers when a program is destroyed.
The object of the present invention is to obtain an inexpensive data processing device.

[Means to solve the problem]

In the data processing device according to the present invention, each processor is provided with a load module memory separate from the main memory, and the program downloaded from the host processor is
Once written to the load module memory, then I
During PL processing, the program is read from this load module memory and written to the main memory of each processor.

[For production]

In the data processing apparatus according to the present invention, when a program for each processor is downloaded from a host processor to each processor, the program is written into the main memory of each processor via a load module memory attached to the processor. In that case, the load module memory is configured such that it is possible to determine whether the content (program) exists or not, and when the IPL process is started, if the content (program) in the load module memory is "No 2", , makes a download request to the host processor and waits until the content (program) becomes "present", and if the content (program) is "present", the content is read out and written into the main memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 19, 29, and 39 are processor 1, respectively.
This is a load module memory that is separately attached to each of the main memories 16, 26, and 36 of 5.25.35, and forms the essential part of the present invention. In FIG. 1, the other configurations Ifi are the same as or similar to the conventional data processing device explained with reference to FIG. Totoku.

Next, referring to FIG. 2, in particular, FULL processor 1
The operation when the content of the load module memory 19 is "none" when the host processor 11 downloads the program of the processor 17 to the main memory 16 of the processor 7 will be explained.

First, when the push button switch 18 for IPL activation is pressed, the IPL processing circuit 17 is activated. The IPL processing circuit 17 checks the content of the load module memory 19, and if it is "no", sends the communication path 14 to the host processor 11.
Submit a download request via . The host processor 11 activates the download processing circuit 13, reads the target program from the disk memory 12, and downloads it to the processor 15. Processor 15
The L processing circuit 17 writes the downloaded program into the load module memory 19 and also writes the same program into the main memory 16.

On the other hand, the contents of load module memory 19 are
The operation in the case of "Yes" will be explained next with reference to FIG.

First, when the push button switch 18 for IPL activation is pressed, the IPL processing circuit 17 is activated. The IPL processing circuit 17 checks the content of the load module memory 19, and if it is "present", reads the content (program) and writes it into the main memory 16.

If you want to change the contents of the program, use disk memory 1.
Change the contents of the area corresponding to the processor 15 of 2,
Next, the contents of the load module memory 19 are set to "null" and the IPL start push button 18 is pressed.

In the above embodiment, the program storage medium of the host processor 11 is the disk memory 12, but it may be a semiconductor memory.

Further, the IPL processing circuits 1γ, 27 . As a means for starting 37, there is a push button switch 18 for starting IPL.
38 is used, but it may be started from a terminal connected to the processor 15°25.35, or it may be started from the host processor 11 side in the form of a start command.

〔Effect of the invention〕

As described above, according to the present invention, the data processing device
A memory for a load module is provided in each processor to which a program is loaded from a host processor.
Since the configuration is configured to reduce the frequency of download requests to the host processor, the memory of the host processor, such as a disk memory, does not need to be high-speed and large-capacity, and therefore the memory can be replaced with an inexpensive one. This also has the effect of shortening the recovery time when the program of each processor is destroyed.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram of a data processing device according to an embodiment of the present invention, and Fig. 2 is a memo for the load module! 71
9.29.39 is a memo for the load module! 4 is a system configuration diagram of a conventional data processing device. 11 is a host processor, 12 is a memory (disk memory), 13 is a download processing circuit, 14 is a communication path, 1
5.25.35 is the processor, 16.26.36 is the main memory, 17, 27.37 is the engineering PL processing circuit, 19, 29
．． 39 is memory for load module. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation -1°-,

Claims (1)

[Claims] a plurality of processors; a memory that stores programs for each of the plurality of processors; a host processor that drives the memory to load the program in the memory to a corresponding one of the plurality of processors; a communication path that commonly connects a host processor and the plurality of processors; a main memory that is attached to each of the plurality of processors and stores the program of the processor; and one main memory for each of the plurality of processors. and a load module memory that is attached thereto and receives the program from the memory and supplies it to the main memory when the program of the processor is loaded from the memory driven by the host processor. .