JPH01262485A - Electronic circuit device - Google Patents

Abstract

PURPOSE:To securely find trouble in a signal processor by sending test data to signal processors and allowing a trouble circuit to receive processing results from those signal processors and decide the trouble. CONSTITUTION:A CPU 7 which performs general control over respective parts generates test data for trouble inspection at prescribed timing, supplies it to selectors 1, 2, and 3 for switching an input signal to be processed and the test data, and switches the selectors 1-3 and a trouble detecting circuit 8 to a trouble detection mode. This circuit 8 compares processing results at the time of the application of the test data to respective signal processing circuits 4, 5, and 6 to detect the occurrence of trouble in a signal processing circuit, thereby sending a trouble detection signal to the CPU 7. A display part makes various displays according to an indication from the CPU 7 and displays the occurrence of trouble when the signal processing circuit is in trouble.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an electronic circuit device having a signal processing circuit,
More specifically, the present invention relates to an electronic circuit device capable of inspecting a signal processing circuit for failure.

(Background of the invention) In recent years, signal processing circuits include ICs (gate arrays).

(including PLA, etc.) are used in large numbers. IC like this
There are the following methods for inspecting for internal failures such as, or failures in connections with peripheral circuits.

(1) Failure inspection method in the production process (a) Inspect the board on which the component is attached visually or with a tester to check for poor soldering and short circuits.

(b) Alternatively, check the board to which the component is attached using a dedicated board tester to check whether a predetermined voltage is being obtained.

(2) Inspection method during operation (a) II If the electronic circuit device no longer operates normally,
judge firmly.

(b) A person inspects the board visually or with a tester.

(3) Failure inspection method for a single IC (a) A signal of a predetermined test pattern is applied to the IC, and judgment is made based on the processing output.

(b) There is a method for testing sequential circuits called the scanvase method. This method divides the entire circuit into a memory element such as a 7-lip flop and a combinational circuit, scans a test pattern into the memory element, operates the combinational circuit, and then sequentially reads out the contents of the memory element to make a decision. be.

(c) As described in Japanese Unexamined Patent Publication No. 160071/1982, two circuits having the same circuit configuration are arranged in one chip,
There is also a method of applying the same input to each and detecting a failure if the outputs are different.

(Problems to be Solved by the Invention) The above method has the following drawbacks. The drawbacks will be explained in conjunction with the above items.

(1) Failure inspection method in the production process (a) Because it relies on human experience, it is not possible to increase the failure detection rate. It also requires skill and a lot of man-hours.

(1)) It is expensive because it requires a dedicated device (dedicated board tester). Further, it requires man-hours such as creating a dedicated program.

If a flat package IC is used, it cannot be inspected as is. Further, it cannot be used on a board with high density mounting.

(2) Inspection method during operation (a) There is a risk that abnormal operation may occur between the occurrence of a failure and the time it is dealt with, resulting in destruction of parts and accidents.

(b) Because it relies on human experience, it is impossible to achieve a high failure detection rate. Also, it requires skill and a lot of man-hours.

(3) Failure inspection method for a single IC (a) It is extremely difficult to create an appropriate test pattern. It also requires many patterns.

(b) Circuit design work is extremely difficult and requires a large number of man-hours.

(C) The circuit scale is more than twice that of a normal case. Furthermore, it is difficult to detect a failure that does not affect the output.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to realize an electronic circuit device that has a simple configuration and can easily perform a failure test inside a signal processing circuit.

(Means for Solving the Problems) The present invention for solving the above problems is an electronic circuit device having a plurality of signal processing means for performing signal processing, the plurality of signal processing means having a comprising a test data generating means for applying test data; and a failure checking means for performing a failure check by comparing respective outputs of the plurality of signal processing means when the test data is applied; This is characterized in that a failure is determined when the outputs of the plurality of signal processing means do not match.

(Operation) In the present invention, the test signal generation means sends test data to each signal processing means, and the failure detection means receives the processing results from the signal processing means, compares them, and tests for failure.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of essential parts of an embodiment of the present invention.

In the figure, 1.2.3 is a selector that switches between the input signal to be processed and test data, and 4.5.6 is a selector that performs predetermined processing on the signal that has passed through selector 1.2.3 and outputs it. This is a signal processing circuit for In this embodiment, the signal processing circuits 4, 5.6 have the same circuit configuration. 7 is a CPLJ that centrally controls each part. At a predetermined timing, the CPU 7 generates test data for failure inspection and supplies it to each of the selectors 1, 2.3, and switches the selector and the failure detection circuit to failure detection mode. 8 is the signal processing circuit 4.5.
This is a failure detection circuit that detects the occurrence of a failure in the signal processing circuit by comparing the processing results when test data is applied to each of the signal processing circuits. This failure detection circuit 8 sends a failure detection signal (for example, a signal that becomes high level when a failure is detected) to the CPU 7. Reference numeral 9 denotes a display section, which displays various displays based on instructions from the CPtJ 7, and also displays a message indicating that the signal processing circuit is out of order when the signal processing circuit is out of order. FIG. 2 is a block diagram showing an electrical configuration when the signal processing circuit is implemented as an IC. Components that are the same as those in FIG. 1 are given the same numbers and their explanations will be omitted. 10 is an IC equipped with the plurality of selectors, the plurality of signal processing circuits, and the failure detection circuit. The CPUs 7 and 1010 are connected as shown in this figure, and exchange test data, failure detection mode switching data, and failure detection data.

FIG. 3 is a flowchart showing the operation of the CPU 7 during a failure test. The operation of the present invention will be outlined below using FIGS. 1 to 3.

The CPU 7 transmits failure detection mode switching data to the IC 10 immediately after the electronic circuit device is powered on or after the signal processing operation is completed. As a result, selector 1 in IC10
3 is switched to pass the test data from the CPU 7, and the IC 10 enters the failure detection mode (step 2). This bond, CPtJ7, transmits predetermined test data (step ■). Note that if the signal processing circuit is a sequential circuit, it is necessary to reset the memory element. IC
Each of the signal processing circuits 4 to 6 in 10 performs predetermined signal processing on this test data. The respective processing results are compared in the failure detection circuit 8. Here, the failure detection circuit 8 compares each of the outputs of the signal processing circuits 4 to 6 (for each bit if the output is multiple bits), and determines that there is a failure if even one output is different. . For example, the failure detection circuit outputs 1 (or a failure detection signal is present) when there is a failure, and outputs 0 when there is no failure. Here, it is assumed that n signal processing circuits process m-bit signals, and the i-th (1
j-th bit (1≦j≦m) of the signal processing circuit where ≦i≦n)
If the output of this fault detection circuit 8 is Olj, then the output T of this failure detection circuit 8 is
can be expressed as .

At this time, the CPU 7 monitors the response from the failure detection circuit 8 (step ■), and when there is a failure detection signal, the CPU 7 monitors the response from the failure detection circuit 8.
It is determined that there is a failure in one of the signal processing circuits in Cl0,
A failure is displayed on the display unit 9, and the operation of the IC determined to be failed is stopped (step 2). Furthermore, if no failure detection signal is output, the IC is determined to be normal and the inspection is terminated.

During normal signal processing, each signal processing circuit in C10 processes and outputs an input signal.

In addition, in this explanation, for convenience, the selector and signal processing circuit are
Although the case where a set is provided has been described, the number may be any number as long as it is two or more.

In addition, in the above explanation, the signal processing circuits have the same circuit configuration, but even if they are not the same, the test data can be used.

All you need to do is make some changes to the circuit configuration.

Next, the operation when the electronic circuit device of the present invention is applied to a uniformity processing device will be explained using FIG. 4.

In the figure, the same parts as in FIG. 1 are designated by the same numbers, and their explanation will be omitted. 11 is a COD for converting the color-separated image of red R into an electric signal, which is color-separated by a dichroic mirror (not shown); 12 is a COD for similarly converting the color-separated image of cyan C into an electric signal. , 13
is A for A/D converting the output of CC[)11゜12.
/D conversion circuit; 14 is a gate circuit that extracts only the effective area from the A/D converted image signal; 15 is a gate circuit that extracts only the effective area from the A/D converted image signal;
6-bit), color code (2-bit) and density data (
16 is a color ghost correction circuit that corrects color ghosts included in the image signal; 17 is an MTF correction circuit that corrects resolution; 18
19 is a density selection circuit for selecting density, and 19 is a multi-value conversion circuit for multi-value conversion of the image signal. These MTF correction circuits 17. Density selection circuit 18. The multilevel converting circuit 19 is constituted by a one-chip rC and has the configuration shown in FIG. 1 (excluding the CPU and display section) (hereinafter referred to as rCb). Further, the IC may include a plurality of p1 type circuits inside. Reference numeral 20 denotes a partial color conversion circuit that converts the color of a part of an image, and is composed of a 1-chip IC, and has the configuration shown in FIG.
(excluding PU and display section) (hereinafter referred to as IO
(called C). Reference numeral 21 is a scaling circuit that scales the image, and 22 is a printer interface circuit that converts an image signal into a signal for printer output. These magnification changing circuits 21. The printer interface circuit 22 is composed of a one-chip IC, and has the configuration shown in FIG. 1 (excluding the CPU and display section) (hereinafter referred to as ICd).
. 23 is a timing generation circuit for driving each part.

This timing generation circuit 23 is constituted by a one-chip IC and has the configuration shown in FIG. 1 (excluding the CPU and display section) (hereinafter referred to as ICa).

Note that wiring from this timing generation circuit 23 to each part is omitted.

The operation will be explained below. The optical image scanned by a scanner (not shown) is separated into a red R color-separated image and a cyan C color-separated image by a dichroic mirror, and each is read by a CGDll, 12. and,
After being A/D converted by the A/D conversion circuit 13, the image signal of only the effective area is extracted by the gate circuit 14. This gate circuit 14 receives a signal (
84 or A3) is given. This image signal is separated into a color code and density data by a color separation circuit 15. The color code and density data are sent to a color ghost correction circuit 16 where color ghost correction is performed. This color ghost correction circuit operates in the main scanning direction,
Perform color ghost correction in the n1 scanning direction. The color ghost-corrected density data is subjected to resolution correction and 81 degree selection. Also, the color code is the partial color conversion circuit 2
0, and if there is an instruction from CP (J7), partial color conversion is executed.
Scaling is performed. Thereafter, the multi-value conversion circuit 19 converts the density data from the scaling circuit 21 into multi-value data based on the threshold data from the CPLJ 7, and sends it to the printer interface. This multivalued signal is sent to the printer interface 22.
from there to a printer (not shown). Incidentally, when performing such an operation, the timing circuit 23
It receives timing generation data from 7 and provides timing signals to each circuit.

By the way, in the above image processing device, ICa is the custom IC that constitutes the timing generation circuit, and ICb is the MT.
IOC is a custom IC that constitutes the F correction circuit, one-time selection circuit, and multi-value conversion circuit, IOC is a custom IC that constitutes a partial color conversion circuit, and ICd is a custom IC that constitutes a magnification circuit and a printer interface. And each IC
has a selector, a signal processing circuit, and a failure detection circuit, and directly exchanges data with the CPU 7 via a signal line. Further, since this image processing device needs to process red and cyan signals, it is assumed that two sets of selectors and signal processing circuits in each IC are arranged, one for red and one for cyan. That is, if you are not in failure test mode (
(normal operation mode), (7) CPU 3 and E
Ca-rcdG is operating normally.

Here, failure inspection of ICa will be explained.

Immediately after the image processing apparatus is powered on or after the image processing operation ends (for example, one second later), failure detection mode switching data is sent from the CPU 7 to the ICa via the timing generation data line. This causes the fca to switch from normal image processing operation to failure detection mode. After that, the CPU 7 sends the test data to ICa via the timing generation data line.
Send to. In the ICa, each signal processing circuit performs signal processing, and the failure detection circuit 8 compares and determines each processing result. The result (failure detection signal) is sent back to the CPU 7 via the timing generation data line. CPU 7 returns I according to the response result.
The state of Ca is determined, and if there is a failure, that fact is displayed on the display section 9, and the operation of ICa (timing generation circuit 23) is stopped.

If there is no failure, the test ends and normal signal processing operations resume.

Similar failure tests are performed for ICb, Ice, and ICd. For this reason, details will be omitted.

Note that the CPU 7 may be separate from the CPU used in normal operation. Furthermore, if appropriate measures are taken, the CPU 7 may be omitted.

With the above configuration, failures can be detected without relying on human experience, so the detection rate is extremely high. Also,
Since it is not necessary to add any parts, it is possible to prevent a decrease in reliability due to the addition of parts (increase in the number of parts). Therefore, increase in substrate area can also be suppressed.

Furthermore, the present invention can also be used for flat package ICs and high-density mounting boards, which have been widely used recently.

If a failure test is performed at regular intervals, even if a failure occurs during operation, it can be detected almost at the same time as the failure occurs. For this reason, it is also possible to prevent the destruction of the nine abnormally operating parts and accidents.

In the above-described embodiment, the explanation was focused on the function of failure detection, but it is also possible to perform failure diagnosis. In this case, it is necessary to make changes to the CPU. Further, in the above-described embodiments, the case where the present invention is applied to an image processing device has been described, but it goes without saying that the present invention is not limited to this and can be applied to various electronic circuit devices.

(Effects of the Invention) As described above in detail, in the present invention, in an electronic circuit device including a plurality of signal processing circuits, a CPU sends a specific signal (test data) to a plurality of signal processing devices,
The failure detection circuit is configured to receive processing results from these signal processing devices and determine a failure. Therefore, it is possible to realize an electronic circuit device that can inspect and reliably discover failures inside the signal processing device with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the main part configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing the main part composition when the circuit in Fig. 1 is integrated into an IC, and Fig. 3 explains failure inspection. FIG. 4 is a block diagram showing the configuration of an applied example of the present invention. 1.2.3... Selector 4.5.6... Signal processing circuit 7... CPLI 8... Failure detection circuit 9... Display section 10... IC11, 12
...CCD 13...A/D conversion circuit 14...
・Gate 15...Color separation circuit 16...Color ghost correction circuit 17...M-F correction circuit 18...Density selection circuit 1
9...Multi-value conversion circuit 20...Partial color conversion circuit 2
1... Magnification variable circuit 22... Printer interface 23... Timing generation circuit Patent applicant Konica Co., Ltd.
Ceremony: Patent attorney Fuji Ijima, 1 person, Ward 1

Claims (1)

[Claims] An electronic circuit device having a plurality of signal processing means for performing signal processing, including a test data generation means for applying test data for failure inspection to the plurality of signal processing means, and when the test data is applied. and fault testing means for performing fault testing by comparing respective outputs of the plurality of signal processing means, and the fault testing means is configured to determine a failure when the outputs of the plurality of signal processing means do not match. An electronic circuit device characterized by comprising: