JPH01261928A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain a stable clock pulse without being affected by means of the lack and occurrence of an input pulse by interrupting the input of a phase comparator and prohibiting a comparison action at the time of the lacking and occurring of the input pulse. CONSTITUTION:When a bit pulse A lacks, a pulse (a) is not outputted from a one shot multi 1a, and a pulse (e) is not outputted from a delay circuit 5a. Since the pulse (d) of H is not outputted from an OR circuit 7 even if a pulse (f) is outputted from the delay circuit 5b, the pulse (f) is interrupted in an AND gate 6c. When the lacking and occurrence of the bit pulse A exists, one of the multis 1a and 1b does not generate the gate pulse at all. Consequently, both AND gates 6b and 6c come to off-states, and the output of a frequency- divider 4 and the input of the occurrence pulse to the phase comparator 2 at the lacking time of the pulse A are prevented. Consequently, the oscillation state of VCO3 becomes stable without being affected by the lacking and occurrence of the bit pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked loop (
PLL) circuit.

[Conventional technology]

When recording and reproducing signals on an optical disk, a synchronization signal based on a pre-pit string preformatted on the optical disk is read, and a lock pulse necessary for recording and reproduction processing is formed from this synchronization signal. A synchronization signal reproduced from an optical disk consists of a train of pulses (hereinafter referred to as pit pulses) resulting from reading pre-pits, and the period of this pit pulse is longer than the period of the required clock pulse. A PLL circuit is generally used as a means for forming such a lock pulse.

The PLL circuit consists of a voltage controlled oscillator, a frequency divider and a phase comparator. When forming a clock pulse from a synchronization signal read from an optical disk as described above,
A clock pulse is generated from a voltage controlled oscillator, this clock pulse is divided by a frequency divider to have the same period as the pit pulse of the synchronization signal, and a phase comparator is used to compare the output pulse of the frequency divider and the bit pulse of the synchronization signal. The phases are compared and the voltage controlled oscillator is controlled with a control voltage according to the phase difference.

[Problems to be Solved by the Invention] □ On the other hand, pit pulses may be missing or pulse noise may occur due to defects or adhesion of dust on the optical disk. In the above PLL circuit, if a pit pulse is missing in the synchronization signal, the phase comparator determines that the period of the pit pulse has become longer because there is no pit pulse to compare the phase with the output pulse of the frequency divider. Then, the voltage controlled oscillator is controlled so that its oscillation frequency becomes lower.

In addition, if pulse noise is mixed into the synchronization signal, the phase comparator treats this as a pit pulse and operates (therefore, this pulse noise is called a pit pulse), but the phase should be compared with this. Since there is no output pulse from the frequency divider, it is determined that the period of the pit pulse has become shorter, and the voltage controlled oscillator is controlled in the direction of increasing the number of oscillation periods.

In this way, the conventional P L that controls the voltage controlled oscillator by directly comparing the phase of the output pulse of the frequency divider and the pit pulse.
In the L circuit, there is a problem in that synchronization tends to occur when pit pulses are missing or appear.

To avoid this, you can lower the loop gain so that it does not respond to missing or emerging pit pulses, but this also makes the response to the synchronization signal looser and There was also the problem that the retraction speed became slow.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable PLL circuit that eliminates such problems, maintains a high pull-in speed, and prevents synchronization due to missing or overflowing pit pulses.

[Means to solve the problem]

To achieve the above objects, the present invention provides means for forming a first gate pulse phase-locked to the output pulse of a frequency divider, and a means for forming a first gate pulse that is phase-locked to the output pulse of a frequency divider. means for delaying the input pulse by 1/2 of the pulse width of the second gate pulse; means for forming a second gate pulse phase-locked to the input pulse; ．． Means is provided for supplying the delayed output pulse of the splitter and the delayed input pulse to the phase comparator only during the period when the second gate pulse exists simultaneously.

1st. Since the pulse widths of the second gate pulses are equal and therefore the delay amounts of the output pulse and the input pulse of the frequency divider are also equal, it is possible to compare the phases of these delayed pulses and to compare the output pulse and input pulse of the frequency divider. Comparing the phases is the same thing. By the way, when a pit pulse is missing, the second gate pulse is not generated, so the pulse input to the phase comparator is prohibited, and when a pit pulse is generated, there is no output pulse from the frequency divider at this point. Since the first gate pulse is not generated, pulse input to the phase comparator is prohibited. Therefore, when a pit pulse is missing or appears, the phase comparator does not perform a comparison operation, and the oscillation state of the voltage controlled oscillator is maintained as it is.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention, in which la and lb are one-shot multi-by-breaks, 2 is a phase comparator, and 3 is a voltage controlled oscillator (
(hereinafter referred to as VCO), 4 is a frequency divider, 5a, 5b are delay circuits, 6-a, 6b, 5c are AND gates, 7
are OR circuits 1, 8, and 9 are input terminals, and 10 is an output terminal.

FIG. 2 is a waveform diagram showing signals at various parts in FIG. 1, and corresponding signals in FIG. 1 are given the same reference numerals.

1 and 2, the pit pulse A of the synchronization signal reproduced from the optical disc (not shown) is input to the input terminal 8.
is input. This pit pulse A is supplied to the one-shot multivibrator 1a as a manual trigger, and a gate pulse a of "H" whose phase coincides with that of the pit pulse A and a pulse width T is formed. Further, the bit pulse A is delayed by 1/2 of the pulse width of the gate pulse a, that is, a time T/2, by the delay circuit 5a, and is supplied to the atgate 6b as a pulse e.

On the other hand, the VCO 3 generates a clock pulse CK of a desired frequency, and this clock pulse CK is divided by a frequency divider 4. The frequency division ratio of this frequency divider 4 is set equal to the frequency ratio of pit pulse A and clock pulse CK when they have correct frequencies. The output pulse g of the frequency divider 4 is supplied as a trigger force to the one-shot multi-vibration brake lb, and a gate pulse b of "H" whose phase coincides with this output pulse g and whose pulse width is T is formed. The output pulse g of the frequency divider 4 is also 1/2 of the pulse width of data 1 to pulse b in the delay diagram 15b, that is, T/2.
and the AND gate 6c as a pulse f.
supplied to

Gate pulses a and b output from the one-shot multi-by-breaks la and lb are supplied to an AND gate 6a. The output C of this AND gate 6a is supplied to an OR circuit 7, and the output d of this OR circuit 7 is supplied as a gate pulse to AND gates 6b and 6C.

Therefore, when the pulse periods of gate pulses a and b overlap at least partially, the output C of the AND gate 6a becomes "H" during this overlap period, and therefore, the "H" gate pulse is output from the OR circuit 7 during this overlap period. d is output. During the pulse period of this gate pulse d, the AND gates 6b, 6c are turned on, and during this period, the pulse e,
If f is output, these are anime) 6b, 6c
The signal is supplied to the phase comparator 2 through.

Here, one-shot multivibrator LA.

The time constants of 1b are equal to CR, and therefore the pulse widths of gate pulses a and b output from these are equal to T. Further, since the delay times of the delay circuits 5a and 5b are both set to be equal to T/2, the delay time of the delay circuit 5a and 5b is set equal to T/2.
The output pulse e of is located at the center of the pulse period of gate pulse a, and the output pulse f of delay diagram B5b is also located at the center of the pulse period of gate pulse b.
It is located at the center of the pulse period.

During the “H” period of the output C of the AND gate 6a, the delay circuit 5
In order for the output pulses e and f of the delay circuit 5a and 5b to exist simultaneously, the delay circuit 5
The time difference between the output pulses b and f must be within the range of ±T/2. In other words, when the time difference between the output pulse g of the frequency divider 4 and the pit pulse A is within ±T/2,
Output pulse h of phase comparator 2) 6b, 6C
, i are input and their phases are compared, and a control voltage j is generated such that the phase difference between them is a predetermined value (for example, zero) and is supplied to the VCO 3.

Therefore, if pit pulse A is missing as shown by the broken line A1 in FIG. 2, even if gate pulse b is output from one-shot multi-by break 1b, gate pulse a is output from one-shot multi-by break 1a. Therefore, the output C of the AND gate 6a is “
It will not be "H".

Therefore, due to the loss of the pit pulse A, the delay diagram 5a
When the pulse f is output from the delay circuit 5b even though the pulse e is not output from the OR circuit 7, the "H" gate pulse d is not output from the OR circuit 7, so the pulse f is blocked by the AND gate 6C, and as a result, the phase There is no input pulse to the comparator 2, and the VCO 3 is held in the same state and is not controlled to change the oscillation frequency.

In addition, as shown by hatching as A2 in FIG. 2, when a pit pulse emerges, this emergent pulse (that is, the previous pulse noise) A2 causes a one-shot multi-by-break 1a. The gate pulse a2 is triggered and the gate pulse a2 whose phase matches the gate pulse a2 is generated, and the gate pulse a2 is delayed by the delay circuit 5a and supplied to the AND gate 6b.

However, near this point, the output pulse g of the frequency divider 4 is not generated, and therefore the gate pulse b is not generated from the one-shot multivibrator 1b, so the output C of the AND gate 6a becomes "H". There isn't. Therefore, the outflow pulse A2 is blocked by the controller 6b,
There will be no input pulse to phase comparator 2.

As mentioned above, when pit pulses are missing or gushing, one-shot multi-bye break la occurs.

One of the AND gates 1b does not always generate a gate pulse, and therefore both AND gates 6b and 6c are in the off state,
The output pulse of the frequency division N4 and the springing pulse when a pit pulse is missing are prevented from being input to the phase comparator 2. Therefore, the oscillation state of C03 is not affected by the loss or occurrence of pit pulses, and becomes stable.

During a certain period from the start of input of the synchronization signal by pit pulse A, that is, during the pull-in start period, “H” is output from the input terminal 9.
” control signal B is input. As a result, the output d of the OR circuit 7 becomes “H” and the AND gates 6b and 6c are turned on. At the start of this pull-in, the pit pulse input to the input terminal 8 The phase relationship between A and the output pulse g of the frequency divider 4 is random, and no matter what phase relationship they have, the pit pulse A is sent to the frequency divider 4 via the delay circuit 5a and the AND gate 6b. The output pulse g of is supplied to the phase comparator 2 via the delay circuit 5b and the AND gate 6c. Therefore, the VCO 3 is set so that the output pulse g of the frequency divider 4 is rapidly phase-locked to the pit pulse A. controlled.

In this way, when a predetermined period of time has elapsed for the completion of the pull-in operation of V'CO3, the control signal B from the input terminal 9 becomes "L", and from then on, the output C of the AND gate I.6a causes the AND gate 6b to , 6C are controlled, and a stable control operation is performed that is not affected by pit pulse omission or occurrence.

〔Effect of the invention〕

As explained above, according to the present invention, when an input pulse is missing or appears, the input of the phase comparator can be cut off to prohibit the comparison operation, and the input pulse is not affected by the omission or occurrence of the input pulse. Therefore, stable clock pulses can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a phase locked loop circuit according to the present invention, and FIG. 2 is a waveform diagram showing signals at various parts in FIG. la, lb...One-shot multi-by-break, 2...Phase comparator, 3...
...... Voltage controlled oscillator, 4... Frequency divider, 5a, 5b... Delay circuit, 6a,
6b, 6c......and gate, 8...
...Input terminal, 10...Output terminal.

Claims (1)

[Claims] A voltage controlled oscillator that generates a clock signal, a frequency divider that divides the frequency of the clock pulse, and a phase comparator that compares the phases of the output pulse of the frequency divider and the input pulse to control the voltage controlled oscillator. In the phase-locked loop circuit, the pulse width T is synchronized with the output pulse of the frequency divider.
first means for generating a first gate pulse of T/2; second means for delaying the output pulse of the frequency divider by a time T/2; third means for generating a gate pulse; and a third means for generating a gate pulse;
and a fifth means for supplying the second and fourth output pulses to the phase comparator during the period when the first and second gate pulses are simultaneously present. A phase locked loop circuit featuring: