JPH01258506A - Logic circuit - Google Patents

Abstract

PURPOSE:To obtain a longitudinal emitter coupling logic circuit with small glitch noise by flowing not only the base emitter capacity current of transistor(TR) but also the current from a capacitor at the time of transition. CONSTITUTION:When an input signal inputted to the base of a TR7 is an H level from a reference voltage (d) inputted to the base of a TR8, the TR7 is on and the TR8 is off. At this time, when an input signal (a) inputted to the base of a TR3 is the H level from a reference voltage (b) inputted to the base of a TR4, the TR3 is on, the TR4 is off and an output (e) is an L level and an output (f) is the H level. In this condition, when the signal (c) is changed to an L level and simultaneously, the H level is inputted to the base of the TR8, the TR7 is off, the TR8 is on, and since the current flows in the sequence of a resistance 1, a TR6, the TR8 and a current source 9, outputs (e) and (f) hold the previous condition. At this time, the emitter current of the TR7 is reduced at a high speed, a current flows from capacitors 10 and 11 transiently and a glitch noise is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, and more particularly to improvements in vertical two-stage emitter-coupled logic circuits.

[Conventional technology]

FIG. 5 shows an example of a conventional logic circuit that includes the problem to be solved by the present invention. Further, FIG. 6 is a diagram for explaining the operation of this logic circuit, with (A) showing a partial circuit diagram and (B) showing a waveform diagram.

This logic circuit is a vertical two-stage emitter-coupled logic circuit, with a resistor of 1.2 and transistors of 3.4°, 5.6°, and 7.8°.
and a current source 9.

A first input signal a, a first reference voltage S, a second input signal C1, and a second reference voltage d are applied to the bases of the transistors 3, 4, 7.8, respectively.

According to such a circuit configuration, if the second input signal C input to the base of the transistor 7 is at a higher level than the second reference voltage d input to the base of the transistor 8, the transistor 7 is turned on. , transistor 8 is turned off. At this time, if the first input signal a input to the base of transistor 3 is at a higher level than the first reference voltage input to the base of transistor 4, transistor 3 is turned on and transistor 4 is turned off. become.

Therefore, the current flows through resistance 1. The current flows in the order of transistor 3, transistor 7, and current source 9, and the output e becomes low level and the output f becomes high level. In this state, the second input signal C
When changing from high level to low level, transistor 7 is turned off, transistor 8 is turned on, and the current flows through resistor 1. Transistor 6, transistor 8. Since the current flows in the order of the current source 9, the outputs e and f maintain their previous states.

- [Problem to be Solved by the Invention] In the conventional logic circuit described above, when the first input signal a is constant and the second input signal C is changed from high level to low level at high speed, the result shown in FIG. As shown in (B), glitch noise occurs in the low level output. This is because when the base voltage of transistor 7 changes from high level to low level, transistor 7 is turned off, the emitter current of transistor 7 decreases, and transistor 8
Emitter current of 1. □ increases. At this time, since Ib2 flows through the base-emitter junction of the transistor 8, the emitter current of the transistor 8 1. Even if □ increases, the transistor 8 does not turn on, and the collector current Ic2
There is a lag in time before it begins to flow.

Therefore, the current LI''Ic2 flowing through the resistor 1 is I
. The current decreases by 2, and glitch noise occurs in the low level output.

Therefore, in a conventional logic circuit having the above characteristics,
When the second input signal C changes rapidly, there is a drawback that large glitch noise occurs in the low-level output.

An object of the present invention is to provide a vertical two-stage emitter-coupled logic circuit with low noise.

[Means to solve the problem]

The logic circuit of the present invention includes a first transistor whose collector is connected to a first power supply via a first resistor, whose base is applied with a first input signal, and whose collector serves as a first output terminal. and a second transistor having a collector connected to the first power supply via a second resistor, a first reference voltage being applied to the base, and the collector serving as a second output terminal; a third transistor connected to the emitter connection point of the first and second transistors and having a base applied with a second input signal; and a third transistor having a collector connected to the collector of the first transistor and having a base connected to the second input signal. a fifth transistor having a collector connected to the collector of the second transistor and a base connected to the first output terminal; a fifth transistor having a collector connected to the collector of the fourth transistor and the first output terminal; a sixth transistor connected to the emitter connection point of the fifth transistor and having a second reference voltage applied to its base; and between the emitter connection points of the third and sixth transistors and the second power supply. The current source is connected to the current source, and the capacitor is connected between the emitter connection point of the third and sixth transistors and the collector of the sixth transistor.

The capacitor can also be replaced by a diode, in which case the anode side of the capacitor is connected to the emitter junction of the third and sixth transistors and the cathode side is connected to the collector of the sixth transistor.

Further, in the logic circuit of the present invention, the collector is connected to the first power supply via the first resistor,
a first transistor to which a first input signal is applied to a base and whose collector serves as a first output terminal; a collector connected to a first power supply via a second resistor;
a second transistor whose base is applied with a first reference voltage and whose collector serves as a second output terminal; whose collector is connected to the emitter connection point of the first and second transistors; a third transistor to which an input signal of the first transistor is applied; a fourth transistor having a collector connected to the collector of the first transistor and a fourth transistor having a base connected to the second output terminal; a fifth transistor connected to the collector of the transistor and having the first output terminal connected to the base; a fifth transistor having the collector connected to the emitter connection point of the fourth and fifth transistors and having the base connected to the second input terminal; a sixth transistor to which a negative phase signal is applied; a current source connected between the emitter connection point of the third and sixth transistors and a second power supply; Preferably, the capacitor is connected between the emitter connection point of the transistor and the collector of the sixth transistor.

The first and second capacitors may be replaced by first and second diodes, respectively, in which case the first capacitor has its anode side connected to the emitter connection points of the third and sixth transistors and its cathode side connected to the emitter connection points of the third and sixth transistors. is connected to the collector of the sixth transistor, and the second capacitor has its anode side connected to the emitter connection point of the third and sixth transistors, and its cathode side connected to the collector of the third transistor.

According to the invention, it is also preferable that the base inputs of the fourth and fifth transistors are connected to the second and first output terminals, respectively, via emitter followers.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a logic circuit according to the present invention, and FIG. 2 is a diagram for explaining the operation of the logic circuit of FIG.
) shows a partial circuit diagram, and (B) shows a waveform diagram.

In FIG. 1, circuit elements that are the same as those shown in FIG. 5 described above are given the same reference numerals.

In FIG. 1, a resistor 1 has one end connected to a first power supply VCC and the other end connected to the collectors of transistors 3 and 5. On the other hand, one end of the resistor 2 is connected to the first power supply vee, and the other end is connected to the collectors of the transistors 4 and 6. The emitters of transistors 3 and 4 are connected,
The connection point is connected to the collector of transistor 7.

The emitters of transistors 5 and 6 are connected, and the connection point is connected to the collector of transistor 8. The emitters of transistors 7 and 8 are connected, and the connection point is a current source 9
■Second power supply via. connected to. capacitor 10
teeth! - Connected between the emitter connection point of Ranjistaf and 8 and the collector of transistor 8.

In one or more circuit configurations, if the second input signal C input to the base of transistor 7 is at a higher level than the second reference voltage d input to the base of transistor 8, transistor 7 is turned on; Transistor 8 is turned off. At this time, if the first input signal a input to the base of transistor 3 is at a higher level than the first reference voltage input to the base of transistor 4, transistor 3 is turned on and transistor 4 is turned off. become.

Therefore, the current flows through resistance 1. Transistor 3. The current flows through the transistor 7 and the current source 9 in this order, and the output e becomes low level and the output f becomes high level.

In this state, when the second input signal C is changed from high level to low level, transistor 7 is turned off, transistor 8 is turned on, and the current flows through resistor 18, transistor 6, transistor 8, and so on. Since the current flows in the order of the current source 9, the outputs e and f maintain their previous states. At this time, transistor 7
Emitter current of■. , decreases rapidly, transiently not only the base-emitter capacitance current rbz of the transistor 8 but also the current 1. of the capacitor 10 decreases. flows, and the current flowing through resistor 1 is ■. r+I cz+I r , which makes it possible to reduce the glitch noise of the low level output.

As a modification of the above logic circuit, the same effect can be obtained by replacing the capacitor 1o with a diode. In this case, the anode of this diode is connected to the emitter connection point of transistors 7 and 8, and the cathode is connected to the collector of transistor 8.

FIG. 3 is a circuit diagram of a logic circuit according to the present invention, and FIG. 4 is a diagram for explaining the operation of the logic circuit of FIG.
) shows a partial circuit diagram, and (B) shows a waveform diagram.

According to this embodiment, in the logic circuit shown in FIG. 1, a capacitor 11 is further connected between the emitter connection point of transistors 7 and 8 and the collector of transistor 7.

In the above circuit configuration, if the second input signal C input to the base of transistor 7 is at a higher level than the second reference voltage d input to the base of transistor 8, transistor 7 is turned on; 8 is off. At this time, if the first input signal a input to the base of transistor 3 is at a higher level than the first reference voltage input to the base of transistor 4, transistor 3 is turned on and transistor 4 is turned off. become.

Therefore, the current flows through resistance 1. Transistor 3. The current flows through the transistor 7 and the current source 9 in this order, so that the output e becomes low level and the output f becomes high level.

In this state, when the second input signal C is changed to high level or low level, at the same time, an opposite phase signal g is applied to the base of the transistor 8, which is the opposite phase of the second input signal C, that is, changes from low level to high level. manually. Transistor 7 is turned off, transistor 8 is turned on, and the current flows through resistor 1. Transistor 6, transistor 8. Current source 9
Since the outputs flow in the order of 0, the outputs e and f retain their previous states.

At this time, when the emitter current 111+ of the transistor 7 decreases rapidly, not only the base-emitter capacitance current 1bZ of the transistor 8 but also the current I of the capacitor 10 and the current I2 of the capacitor 11 flow, and the current flows through the resistor 1. becomes ■cI'' Ic2+ 1++ I2, and the glitch noise of the low level output can be reduced.

As a modification of the above logic circuit, capacitors 10 and 11
A similar effect can be obtained by replacing each with a diode. In this case, a diode replacing capacitor 10 has its anode connected to the emitter connection of transistors 7 and 8 and its cathode to the collector of transistor 8. Further, a diode replacing the capacitor 11 has its anode connected to the emitter connection point of the transistors 7 and 8 and its cathode connected to the collector of the transistor 7.

In each of the above logic circuits, the transistors 5 and 6 are directly connected to the outputs f and e, but the present invention also applies to logic circuits in which the transistors 5 and 6 are connected to the outputs f and e through emitter followers. Application is possible.

〔Effect of the invention〕

As described above, according to the present invention, a vertical two-stage emitter-coupled logic circuit with small glitch noise can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram of a logic circuit according to the present invention, FIG. 2 is a diagram for explaining the operation of the circuit in FIG. 1, FIG. 3 is an electric circuit diagram of a logic circuit according to the present invention, and FIG. 5 is a diagram for explaining the operation of the circuit shown in FIG. 3, FIG. 5 is an electric circuit diagram of a conventional logic circuit, and FIG. 6 is a waveform diagram for explaining the operation of the circuit shown in FIG. ■, 2...Resistor 3.4, 5, 6, 7.8...Transistor 9...Current source 10, 11...Capacitor a...First input signal b...First Reference voltage C...Second input signal d...Second reference voltage e, f...Output signal g...Reverse phase signal of the second input signal VCC...First Power supply VEE...Second power supply IC+...Collector current IcZ of transistor 7...
・Collector current Ibl of transistor 8...Base-emitter capacitance current Ib□ of transistor 7...Base-emitter capacitance current Ll of transistor 8...Emitter current Ia2 of transistor 7...
Emitter current of transistor 8 ■, ... capacitor 1
0 current I2 ... Current agent of capacitor 11 Yoshiyuki Iwasa, patent attorney t current r of capacitor 10, IIct" Ic
z ``It, No-low level output ゛vT CB) Fig. 2 Fig. 3 Fig. 4 Current of capacitor 10 ■, -几'V----Current of capacitor 11 12''V---- --r
c+ "Icz" L + I2, No--low level output 2 hours (Bn Figure 4, Figure 5, Figure 6, Figure 6, 2nd input signal C) Collector current I of transistor 7. Base emitter capacitance of transistor 8 @浬1bz Transistor 8 collector current IGz Iζs ” Icz Low level output time B) Figure 6

Claims (5)

[Claims] (1) a first transistor having a collector connected to a first power supply via a first resistor, a first input signal being applied to the base, and the collector serving as a first output terminal; connected to the first power source via the second resistor;
a second transistor whose base is applied with a first reference voltage and whose collector serves as a second output terminal; whose collector is connected to the emitter connection point of the first and second transistors; a third transistor to which an input signal of is applied; a fourth transistor having a collector connected to the collector of the first transistor and a base connected to the second output terminal; a fourth transistor having a collector connected to the collector of the second transistor; a fifth transistor connected to the collector of the transistor and having the first output terminal connected to the base; and a fifth transistor having the collector connected to the emitter connection point of the fourth and fifth transistors and having the base connected to the second reference voltage. a current source connected between the emitter connection point of the third and sixth transistors and a second power supply, and the emitter connection point of the third and sixth transistors; and a capacitor connected between the collector of the sixth transistor and the collector of the sixth transistor. (2) The logic circuit according to claim 1, wherein the capacitor is replaced with a diode whose anode side is connected to the emitter connection point of the third and sixth transistors and whose cathode side is connected to the collector of the sixth transistor. (3) a first transistor having a collector connected to a first power supply via a first resistor, a first input signal being applied to the base, and the collector serving as a first output terminal; connected to the first power source via the second resistor;
a second transistor whose base is applied with a first reference voltage and whose collector serves as a second output terminal; whose collector is connected to the emitter connection point of the first and second transistors; a third transistor to which an input signal of is applied; a fourth transistor having a collector connected to the collector of the first transistor and a base connected to the second output terminal; a fourth transistor having a collector connected to the collector of the second transistor; a fifth transistor connected to the collector of the transistor and having the first output terminal connected to the base; a fifth transistor having the collector connected to the emitter connection point of the fourth and fifth transistors; a sixth transistor to which a negative phase signal of the input signal is applied; a current source connected between the emitter connection point of the third and sixth transistors and a second power supply; a first capacitor connected between the emitter connection point of the transistor and the collector of the sixth transistor; and between the emitter connection point of the third and sixth transistors and the collector of the third transistor. A logic circuit configured with a connected second capacitor. (4) The first capacitor is connected to the anode side of the third capacitor.
and a first diode connected to the emitter connection point of the sixth transistor and having its cathode connected to the collector of the sixth transistor, and replacing the second capacitor with a first diode having its anode connected to the third and sixth transistors. 4. The logic circuit according to claim 3, wherein the logic circuit is replaced by a second diode connected to the emitter connection point of the third transistor and whose cathode side is connected to the collector of the third transistor. (5) The logic circuit according to any one of claims 1 to 4, wherein base inputs of the fourth and fifth transistors are connected to the second and first output terminals, respectively, via emitter followers.