JPH01258452A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH01258452A JPH01258452A JP63086512A JP8651288A JPH01258452A JP H01258452 A JPH01258452 A JP H01258452A JP 63086512 A JP63086512 A JP 63086512A JP 8651288 A JP8651288 A JP 8651288A JP H01258452 A JPH01258452 A JP H01258452A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrate
- support substrate
- gate opening
- metal mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 33
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000007789 sealing Methods 0.000 claims abstract description 12
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract 2
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は金属製支持基板上に半導体チップを固定し、こ
の基板の表面および裏面を共に樹脂で被覆した絶縁型の
樹脂封止半導体装置に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an insulated resin-sealed semiconductor device in which a semiconductor chip is fixed on a metal support substrate and both the front and back surfaces of this substrate are coated with resin. .
従来のこの種の半導体装置は、第５図の断面図に示すよ
うに、金属製支持基板２１の上に半導体チップ２を搭載
し、基板２１の長手方向の一方の端部の支持ビン４と他
方の端部の外部リード５とにより基板２１を樹脂封止金
型１２内の注入空間に支え、金型１２の樹脂注入用のゲ
ート口１３から樹脂３を注入して支持基板の表面および
裏面にわたり樹脂３で被覆していた。As shown in the cross-sectional view of FIG. 5, a conventional semiconductor device of this type has a semiconductor chip 2 mounted on a metal support substrate 21, and a support bin 4 at one end of the substrate 21 in the longitudinal direction. The substrate 21 is supported in the injection space in the resin sealing mold 12 by the external lead 5 at the other end, and the resin 3 is injected from the resin injection gate 13 of the mold 12 to seal the front and back surfaces of the support substrate. The entire surface was covered with resin 3.
上述した従来の半導体装置の金属支持基板の形状では、
樹脂の注入口となるゲート口と対向する端部（支持ピン
４が突き出ている部分）形状が樹脂流入方向に対して直
角に近い角度を持っているため、樹脂の注入圧が分散さ
れることになり、金属支持基板の表面、裏面に注入され
る樹脂圧の低下を生じ、樹脂ボイド、ピンホール等の未
充填が発生する。その結果、外観不良発生率が高く、コ
スト高になるという欠点を有していた。In the shape of the metal support substrate of the conventional semiconductor device described above,
Since the shape of the end (the part from which the support pin 4 protrudes) facing the gate port that serves as the resin injection port has an angle close to perpendicular to the resin inflow direction, the resin injection pressure is dispersed. This causes a decrease in the pressure of the resin injected onto the front and back surfaces of the metal support substrate, resulting in unfilled resin voids, pinholes, etc. As a result, there have been disadvantages in that the incidence of appearance defects is high and the cost is high.
上記問題点に対し本発明の半導体装置における半導体チ
ップが搭載されている金属支持基板は、長手方向の少く
とも一方の端部は底面の角の部分で底面から１５〜５０
°の角度範囲の斜面となっている。しかしてこの斜面は
、樹脂封止の際に成形金型の樹脂注入のゲート口と対向
した位置関係にある。In order to solve the above problem, the metal supporting substrate on which the semiconductor chip is mounted in the semiconductor device of the present invention has at least one end in the longitudinal direction at a corner of the bottom surface, which is 15 to 50 mm away from the bottom surface.
The slope has an angle range of °. However, the slope of the lever is positioned opposite to the resin injection gate of the molding die during resin sealing.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第１図（ａ）は本発明の一実施例の斜視図、同図（ｂ）
は同図（ａ）のＡ−Ａ線断面図である。第１図（ａ）、
（ｂ）において金属支持基板１の上面には半導体素子
２が固定され、支持基板１の上面および下面側は共に樹
脂３で被覆されている。支持基板１の長手方向の一方の
端部の２箇所から支持ピン４が突出し、反対の端部から
は外部リード５が外部へ引出されている。しかして、支
持基板１の支持ピン４がある端部の下面の角の部分は、
取付穴６の下面開口の中心を横切る下面の横断線を出発
線として、端部に向けて約４５°の角度θで削り取られ
た形の斜面８となっている。FIG. 1(a) is a perspective view of an embodiment of the present invention, and FIG. 1(b) is a perspective view of an embodiment of the present invention.
is a sectional view taken along line A-A in FIG. Figure 1(a),
In (b), a semiconductor element 2 is fixed to the upper surface of the metal support substrate 1, and both the upper and lower surfaces of the support substrate 1 are covered with a resin 3. Support pins 4 protrude from two locations on one end of the support substrate 1 in the longitudinal direction, and external leads 5 are drawn out from the opposite end. Therefore, the corner part of the lower surface of the end where the support pin 4 of the support board 1 is located is as follows.
A slope 8 is formed by cutting off at an angle θ of about 45° toward the end, starting from a transverse line of the lower surface that crosses the center of the lower opening of the mounting hole 6.
第２図（ａ）は第１図の支持基板の取付穴部分の部分断
面図、第２図（ｂ）は同図（ａ）の左方向から見た側面
図である。2(a) is a partial cross-sectional view of the mounting hole portion of the support substrate in FIG. 1, and FIG. 2(b) is a side view seen from the left side of FIG. 2(a).
第２図（ａ）の支持基板端部下面側の斜面８においては
、同図（ｂ）に見られるように、取付穴６の下面部は斜
面８に半円形の横向き開ロアとなって現われている。し
たがって、第３図の断面図に示すように、金型１２の中
空部に、支持ピン４と外部リード５でもって支持基板１
を支持し、金型１２のゲート口１３から樹脂３を注入し
た場合、樹脂３は斜面８に沿って矢印すに示すように進
入し、支持基板１の下面と金型の間の狭い隙間にも容易
に入り込む。また、矢印ａに示すように注入樹脂３は取
付穴５の横向き開ロアから取付穴を通って基板１の上面
側に廻り込み、半導体素子２のある基板１の上面側にも
十分に樹脂被覆が行なわれる。In the slope 8 on the lower surface side of the end of the support board in FIG. 2(a), as seen in FIG. ing. Therefore, as shown in the cross-sectional view of FIG.
When the resin 3 is injected from the gate port 13 of the mold 12, the resin 3 enters along the slope 8 as shown by the arrow and enters the narrow gap between the lower surface of the support substrate 1 and the mold. can also be easily penetrated. Further, as shown by arrow a, the injected resin 3 flows from the horizontally open lower side of the mounting hole 5 through the mounting hole to the upper surface of the substrate 1, and the upper surface of the substrate 1 where the semiconductor element 2 is also sufficiently coated with resin. will be carried out.
なお、上記斜面の角度θは４５°にしているが、この角
度は１５〜５０°の範囲にとることができる。Note that although the angle θ of the slope is set to 45°, this angle can be set in a range of 15 to 50°.
第４図は本発明の実施例２の樹脂封止を説明するための
断面図である０本実施例では、金型のゲート口１３と対
向した傾斜面を２段構成にして傾斜角度を小さく設定し
やすくしである。すなわち、第１段の傾斜８ａは金属支
持基板１１の表面部から約１／３迄に形成し、さらに第
２段の傾斜８ｂを第１の実施例に示した角度で形成した
。FIG. 4 is a cross-sectional view for explaining resin sealing in Example 2 of the present invention. In this example, the inclined surface facing the gate opening 13 of the mold is configured in two stages to reduce the inclination angle. It is easy to set up. That is, the first stage slope 8a was formed up to about ⅓ from the surface of the metal support substrate 11, and the second stage slope 8b was formed at the angle shown in the first embodiment.
以上説明したように本発明は、金属支持基板の端部に傾
斜面を設け、成形工程においてゲート口と傾斜面とが対
向するように配置することにより、外観不良率の大巾な
低減が可能であり原価低減に寄与できる。As explained above, in the present invention, by providing an inclined surface at the end of the metal support substrate and arranging the gate opening and the inclined surface so as to face each other during the molding process, it is possible to significantly reduce the appearance defect rate. This can contribute to cost reduction.
第１図（ａ）は本発明の一実施例の斜視図、同図（ｂ）
は同図（ａ）のＡ−Ａ線断面図、第２図（ａ）は第１図
の金属支持基板の部分断面図、第２図（ｂ）は同図（ａ
）の左方向から見た側面図、第３図は第１図の実施例の
樹脂封止工程を説明するための断面図、第４図は本発明
の他の実施例の樹脂封止工程を説明するための断面図、
第５図は従来の樹脂封止半導体装置の樹脂封止工程を説
明するための断面図である。
１．１１．２１・・・・・・金属支持基板、２・・・・
・・半導体素子、３・・・・・・封止樹脂、４・・・・
・・支持ピン、５・・・・・・外部リード、６・・・・
・・取付穴、７・・・・・・横向き開口、８，８ａ、８
ｂ・・・・・・斜面、１２・・・・・・金型、１３・・
・・・・ゲート口。
代理人 弁理士 内 原 音
（ｔｚ） （ｂ）
第 Ｚ 図FIG. 1(a) is a perspective view of an embodiment of the present invention, and FIG. 1(b) is a perspective view of an embodiment of the present invention.
2(a) is a partial sectional view of the metal support substrate in FIG. 1, and FIG. 2(b) is a sectional view taken along the line A-A in FIG.
) as seen from the left, FIG. 3 is a sectional view for explaining the resin sealing process of the embodiment of FIG. 1, and FIG. 4 is a side view of the resin sealing process of another embodiment of the present invention. A cross-sectional view for explanation,
FIG. 5 is a cross-sectional view for explaining the resin sealing process of a conventional resin-sealed semiconductor device. 1.11.21...Metal support substrate, 2...
...Semiconductor element, 3... Sealing resin, 4...
...Support pin, 5...External lead, 6...
...Mounting hole, 7...Side opening, 8, 8a, 8
b...Slope, 12...Mold, 13...
...Gate entrance. Agent Patent Attorney Uchihara Oto (tz) (b) Figure Z
Claims (1)
型内に配置し、前記金型のゲート口から樹脂を注入して
前記金属支持基板の表面および裏面を前記注入樹脂によ
り被覆してなる樹脂封止半導体装置において、前記樹脂
封止の際前記金型のゲート口に対向する前記金属支持基
板の端部底面の角の部分は、この底面に対し１５〜５０
゜の角度の範囲の斜面に形成されていることを特徴とす
る樹脂封止半導体装置。A resin formed by arranging a metal support substrate on which a semiconductor chip is mounted in a resin sealing mold, injecting resin from the gate opening of the mold, and coating the front and back surfaces of the metal support substrate with the injected resin. In the sealed semiconductor device, the bottom corner of the end of the metal support substrate facing the gate opening of the mold during the resin sealing is 15 to 50 mm away from the bottom surface.
1. A resin-sealed semiconductor device, characterized in that the device is formed on a slope having an angle of .degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63086512A JPH01258452A (en) | 1988-04-08 | 1988-04-08 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63086512A JPH01258452A (en) | 1988-04-08 | 1988-04-08 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01258452A true JPH01258452A (en) | 1989-10-16 |
Family
ID=13889034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63086512A Pending JPH01258452A (en) | 1988-04-08 | 1988-04-08 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01258452A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5514913A (en) * | 1991-12-05 | 1996-05-07 | Consorzio Per La Ricerca Sulla Microelettronica Net Mezzogiorno | Resin-encapsulated semiconductor device having improved adhesion |
| JPH09232496A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Electronic component |
| JP2012033178A (en) * | 2003-06-23 | 2012-02-16 | Sandisk Corp | Integrated circuit product |
-
1988
- 1988-04-08 JP JP63086512A patent/JPH01258452A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5514913A (en) * | 1991-12-05 | 1996-05-07 | Consorzio Per La Ricerca Sulla Microelettronica Net Mezzogiorno | Resin-encapsulated semiconductor device having improved adhesion |
| US5766985A (en) * | 1991-12-05 | 1998-06-16 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Process for encapsulating a semiconductor device having a heat sink |
| JPH09232496A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Electronic component |
| JP2012033178A (en) * | 2003-06-23 | 2012-02-16 | Sandisk Corp | Integrated circuit product |
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