JPH05315535A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH05315535A
JPH05315535A JP12151792A JP12151792A JPH05315535A JP H05315535 A JPH05315535 A JP H05315535A JP 12151792 A JP12151792 A JP 12151792A JP 12151792 A JP12151792 A JP 12151792A JP H05315535 A JPH05315535 A JP H05315535A
Authority
JP
Japan
Prior art keywords
resin
island
lead frame
gate
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP12151792A
Other languages
Japanese (ja)
Inventor
Kenji Suetake
健司 末竹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12151792A priority Critical patent/JPH05315535A/en
Publication of JPH05315535A publication Critical patent/JPH05315535A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To enable the resin flow rate in the gate opposite side to be controlled in the higher and lower side making reference to that in an island by applying a non-conductive resin to the inner lead in the opposite side of a gate part wherein the resin is injected. CONSTITUTION:Multiple inner leads encircling an island 4 lead out the equal number of leads in four directions. A non-conductive resin tape 3 is applied to the part on the inner leads 5 in the opposite side of a gate part 7. Through these procedures, the resin flow rate in the higher and lower side can be controlled making reference to that running in the island 4 through a cavity 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、樹脂封止型半導体装置
用リードフレーム(以下リードフレームと略す。)に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device lead frame (hereinafter referred to as a lead frame).

【0002】[0002]

【従来の技術】従来のリードフレームは、図3に示すよ
うに、半導体素子を搭載するアイランド4を備え、この
アイランド4の周囲を囲むようにインナーリード5が配
置されている。インナーリード5は半導体によって2方
向もしくは四方向に同数のリードを導出し、ゲート側及
びゲート対向側2と区分すれば、インナーリード5の幅
やインナーリード5のスキマはほぼ均等に設計されてい
た。
2. Description of the Related Art A conventional lead frame, as shown in FIG. 3, includes an island 4 on which a semiconductor element is mounted, and an inner lead 5 is arranged so as to surround the island 4. As for the inner leads 5, if the same number of leads are led out in two directions or four directions by the semiconductor and are divided into the gate side and the gate facing side 2, the width of the inner leads 5 and the clearance of the inner leads 5 are designed to be substantially equal. ..

【0003】リードフレームに搭載する半導体素子の電
極数が増加すると、それに対するインナーリード5の本
数も増加し、それに伴い、インナーリード5の先端は微
細化されてくるため、インナーリード5の変形が生じや
すくなってくる。従来このリード変形防止の為に非導電
性の樹脂テープ3がインナーリード5上に貼れる場合が
あり、その形状は長方形の形状もしくは正方形の形状に
貼られており、ゲート部及びゲート対向側も区別した場
合、樹脂テープ3は形状・位置共に均等に形成されてい
た。
When the number of electrodes of the semiconductor element mounted on the lead frame increases, the number of inner leads 5 corresponding thereto also increases, and the tips of the inner leads 5 become finer accordingly, so that the inner leads 5 are deformed. It tends to occur. Conventionally, in order to prevent the lead from being deformed, a non-conductive resin tape 3 may be pasted on the inner lead 5, and the shape is pasted in a rectangular shape or a square shape, and the gate portion and the gate facing side are also distinguished. In this case, the resin tape 3 was formed uniformly in shape and position.

【0004】[0004]

【発明が解決しようとする課題】この従来のリードフレ
ームにおいては、インナーリード幅,インナーリード間
スキマ樹脂テープ位置・形状がゲート側とゲート対向側
が、ほぼ均等に設計されており、アイランドの上に半導
体素子を搭載して金型に入れ、ゲート部7からゲート対
向側2に樹脂を流して樹脂封止する場合、アイランドを
基準にしてアイランドの上方(半導体素子が搭載された
方)とアイランドの下方(裏面)の樹脂の体積は異な
る。そのためキャビティ6を流れる樹脂速度はアイラン
ドを基準にして上下で異なり、樹脂速度の遅いアイラン
ドの裏面側に封入工程での樹脂未充填等のボイド不良が
発生するという問題点があった。
In this conventional lead frame, the inner lead width and the gap / inner lead tape position / shape between the inner leads are designed to be substantially even on the gate side and the gate facing side, and the inner lead When a semiconductor element is mounted and placed in a mold, and resin is flowed from the gate portion 7 to the gate facing side 2 for resin sealing, the island above the island (on which the semiconductor element is mounted) and the island The volume of the resin on the lower side (back side) is different. Therefore, the speed of the resin flowing through the cavity 6 is different between the upper and lower sides with respect to the island, and there is a problem that void defects such as resin unfilling occur in the back surface side of the island having a slow resin speed in the encapsulation process.

【0005】[0005]

【課題を解決するための手段】本発明のリードフレーム
は、樹脂注入を行うゲート部の対向側のインナーリード
に非導電性の樹脂テーブを貼付けている。あるいは、ゲ
ート部側に比べてゲート部対向側のインナーリード幅を
太くしインナーリード間スキマを密にしたことを特徴と
している。
In the lead frame of the present invention, a non-conductive resin tape is attached to the inner lead on the side opposite to the gate portion where resin is injected. Alternatively, it is characterized in that the inner lead width on the gate facing side is thicker than that on the gate side and the gap between the inner leads is made dense.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例のリードフレームの平面図
である。アイランド4を囲んで、複数のインナーリード
5が4方向に同数のリードを導出している。ゲート部7
の対向側2のインナーリード5の上に非導電性の樹脂テ
ーブ3を貼付けている。この樹脂テープ3によって、キ
ャビティ6内を流れるアイランド4を基準にして上下の
樹脂速度をゲート部対向側2で調整している。
The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention. Surrounding the island 4, a plurality of inner leads 5 lead out the same number of leads in four directions. Gate part 7
A non-conductive resin tape 3 is attached on the inner lead 5 on the opposite side 2. The resin tape 3 adjusts the vertical resin speed on the gate facing side 2 with respect to the island 4 flowing in the cavity 6.

【0007】次に第2の実施例にについて図面を参照し
て説明する。図2は第2の発明のリードフレーム平面図
である。アイランド4を囲むインナーリード3はゲート
部7側とゲート対向側2と区分した場合、ゲート部7側
に比べてゲート対向側2は、インナーリード5の幅を太
くし、インナーリード間のスキマを密にしている。この
差によってゲート対向側2での上下の樹脂速度調整して
いる。第2の実施例は、第1の実施例と比べて樹脂テー
ブ3を使用してない為、コストが安いだけでなく、樹脂
テープ3が貼れない大ペレット対応のインナーリード5
の短いリードフレーム1に適している。
Next, a second embodiment will be described with reference to the drawings. FIG. 2 is a plan view of the lead frame of the second invention. When the inner lead 3 surrounding the island 4 is divided into the gate portion 7 side and the gate facing side 2, the width of the inner lead 5 on the gate facing side 2 is thicker than that on the gate portion 7 side, and the gap between the inner leads is reduced. It's close. By this difference, the upper and lower resin speeds on the gate facing side 2 are adjusted. The second embodiment does not use the resin tape 3 as compared with the first embodiment, so that not only the cost is low, but also the inner lead 5 for large pellets on which the resin tape 3 cannot be stuck.
Suitable for lead frame 1 having a short length.

【0008】[0008]

【発明の効果】以上説明したように本発明は、ゲート部
の対向側に非電導性の樹脂テーブを貼付けたり、ゲート
部側に比べてゲート対向側のインナーリードの幅を太く
インナーリード間スキマを密にして、ゲート対向側の樹
脂速度をアイランドを基準に上下で調整している。よっ
て今迄問題となっていたアイランド基準に上側の樹脂速
度が下側の樹脂速度より速かった為発生していたアイラ
ンド裏面側の巻き込みボイド不良が低減できる。
As described above, according to the present invention, a non-conductive resin tape is attached to the opposite side of the gate portion, or the inner lead gap on the gate opposite side is made wider than that on the gate side. And the resin speed on the gate facing side is adjusted up and down based on the island. Therefore, the entrainment void defect on the back surface side of the island, which occurred because the resin speed on the upper side was higher than the resin speed on the lower side with respect to the island standard, which has been a problem until now, can be reduced.

【0009】以下に今回ゲート対向部にテープを貼った
場合のシミュレーションを行い、効果を確認した。図4
が今回シミュレーションに用いたモデル図である。図5
がシミュレーションの解析結果である。縦軸が注入時
間,横軸が充填率差であり中央を0%として(+)方向
が上面の流れが実行している割合、(−)方向が裏面の
流れが先行している割合を示している。グラフの中の黒
四角(■)はテープを貼った場合、黒丸(●)がテープ
なしの従来のリードフレームを表わしている。また充填
率の定義については、図6(a),(b)に従い、下記
の式を用いて算出した。
Below, a simulation was carried out when a tape was attached to the gate facing portion this time, and the effect was confirmed. Figure 4
Is the model diagram used for this simulation. Figure 5
Is the analysis result of the simulation. The vertical axis represents the injection time, the horizontal axis represents the difference in filling rate, and the center is 0%, and the (+) direction is the ratio of the upper surface flow being executed, and the (-) direction is the ratio of the back surface flow preceding. ing. The black squares (■) in the graph represent the conventional lead frame without tape when the tape is attached. The definition of the filling rate was calculated using the following formula according to FIGS. 6 (a) and 6 (b).

【0010】 充填率(%)=(充填長さ/経路の全距離)×100 充填率差(%)=(上面の充填率)−(裏面の充填率) 図5を説明すると、最初樹脂注入は下側より樹脂注入す
る為にゲート部ではアイランドの裏面側の樹脂が先行し
ているが、キャビティ途中にアイランドが搭載されてい
る為に、上側の樹脂流路厚が狭くなり、ゲート対向部で
は逆に、樹脂速度が早くなる。その為、上側の樹脂が下
側にまわり込み、アイランド裏面側にボイド不良が発生
した。しかし黒丸で示したようにテーピングするとゲー
ト対向側では上側下側の樹脂充填率が等しくなりボイド
不良も起きにくくなるという確証を得た。このことはイ
ンナーリード幅をゲート対向部側で太くし、インナーリ
ードスキマを密にした場合についても同様のシミュレー
ション結果を得た。
Filling rate (%) = (filling length / total distance of path) × 100 Filling rate difference (%) = (filling rate of upper surface) − (filling rate of back surface) Referring to FIG. Since the resin is injected from the lower side, the resin on the back side of the island precedes at the gate part, but since the island is mounted in the middle of the cavity, the resin flow path thickness on the upper side becomes narrow, and the gate facing part On the contrary, the resin speed increases. Therefore, the resin on the upper side wraps around to the lower side, and a void defect occurs on the back surface side of the island. However, as shown by the black circles, it was confirmed that taping has the same resin filling rate on the upper and lower sides on the gate facing side, and void defects are less likely to occur. This means that the same simulation result was obtained when the inner lead width was made thicker on the gate facing side and the inner lead gap was made denser.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のリードフレーム平面図FIG. 1 is a plan view of a lead frame according to an embodiment of the present invention.

【図2】本発明の第2の実施例のリードフレーム平面図FIG. 2 is a plan view of a lead frame according to a second embodiment of the present invention.

【図3】従来のリードフレーム平面図FIG. 3 is a plan view of a conventional lead frame.

【図4】シミュレーション解析に使用したリードフレー
ム平面のモデル図
FIG. 4 Model diagram of the plane of the lead frame used for the simulation analysis

【図5】解析結果を示す図FIG. 5 is a diagram showing analysis results.

【図6】解析方法の定義を示す図FIG. 6 is a diagram showing the definition of an analysis method.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 ゲート対向側 3 樹脂テープ 4 アイランド 5 インナーリード 6 キャビティ 7 ゲート部 1 Lead Frame 2 Gate Opposite Side 3 Resin Tape 4 Island 5 Inner Lead 6 Cavity 7 Gate

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載するアイランドと前記
アイランドを取り囲んで配置された複数のインナーリー
ドとを備えた樹脂封止型の半導体装置用リードフレーム
において、樹脂注入を行うゲート部の対向側のインナー
リードに非導電性の樹脂テープを貼付けたことを特徴と
する半導体装置用リードフレーム。
1. A resin-encapsulated lead frame for a semiconductor device, which comprises an island for mounting a semiconductor element and a plurality of inner leads arranged so as to surround the island, on a side opposite to a gate portion for resin injection. A lead frame for a semiconductor device, characterized in that a non-conductive resin tape is attached to the inner lead.
【請求項2】 半導体素子を搭載するアイランドと、前
記アイランドを取り囲んで配置された複数のインナーリ
ードとを備えた樹脂封止型の半導体装置用リードフレー
ムにおいて、樹脂注入を行うゲート部側に比べてゲート
部対向側のインナーリード幅を太くしインナーリード間
スキマを密にしたことを特徴とする半導体装置用リード
フレーム。
2. A resin-encapsulated lead frame for a semiconductor device, which comprises an island on which a semiconductor element is mounted and a plurality of inner leads arranged so as to surround the island, as compared with a gate portion side on which resin is injected. The lead frame for a semiconductor device is characterized in that the inner lead width on the side opposite to the gate portion is widened so that there is a close gap between the inner leads.
JP12151792A 1992-05-14 1992-05-14 Lead frame for semiconductor device Withdrawn JPH05315535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12151792A JPH05315535A (en) 1992-05-14 1992-05-14 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12151792A JPH05315535A (en) 1992-05-14 1992-05-14 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH05315535A true JPH05315535A (en) 1993-11-26

Family

ID=14813177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12151792A Withdrawn JPH05315535A (en) 1992-05-14 1992-05-14 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH05315535A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017170814A (en) * 2016-03-25 2017-09-28 日立オートモティブシステムズ株式会社 Resin molded article

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017170814A (en) * 2016-03-25 2017-09-28 日立オートモティブシステムズ株式会社 Resin molded article

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990803