JPH01258294A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To keep the plural types of function in one device by switching the function in correspondence to the type of a dummy cycle. CONSTITUTION:When a low address strobe the inverse of RAS signal and a column address strobe the inverse of CAS signal are in the condition of high potential and a power source is inputted, an output M of a latch circuit 13 goes to be the low potential. Next, when the dummy cycle is executed and RAS only-refresh (ROR) is executed, a one-shot pulse is generated in the output of a generating circuit 12 when the RAS signal is changed from the low potential to high potential. Then, the output M goes to the high potential and it is inputted to a CAS control system. After that, transistors Q5 and Q6 are turned on and an NBL mode is obtained. Next, when CBR refresh is executed after the power source is supplied, the output of a CBR deciding circuit 11 is changed from being high to be low and the output of a latch circuit 14 is caused to be high and inputted to an NOR circuit C1. Then, the output M goes to be low, the transistors Q5 and Q6 are turned off and a page mode can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic random access memory, and more particularly to a dynamic random access memory whose function can be switched among semiconductor memories.

[Conventional technology]

Currently, among semiconductor memories, especially dynamic random access memories (hereinafter referred to as DRAM), page mode (page mode) is used as a function to increase speed.
Page Mode), NBL Mode (Nibb
mode), or static column mode (S
Various methods have been realized, such as tatic column mode). However, these functions cannot be provided simultaneously in the same device, and each exists as a different product. For example, traditional NBL
Next, switching between a mode device and a page mode device will be described.

In FIG. 4, Q1 to Q4 are N-channel transistors, A, -, -A are inverting circuits, B is a NAND circuit, 1
2 is a column address strobe (hereinafter referred to as "CAS") system control circuit, 2 is a pull to NBL) system control circuit, 5
EEND is the sense completion signal and the CAS system start signal.
MSI・2 indicates a cut or fuse by mask slicing (hereinafter referred to as “MSI・MS2°°”).

In this conventional example, once the MSI/MS2 portion is brought into the connected state and the CAS system becomes active, the contacts a and 1] are clamped to a low potential by the active signal C of the CAS system. Even if the bundle C-S-signal is set, the CAS system will not be reset, and the NBL system will not be reset.
Mikari is set, and N n L is synchronized with the C-furnace entry signal.
, only the system works. That is, the circuit shown in the fourth [¥1] operates in the NBL mode. Also, MSI and MS2
or in the disconnected state, no change is given to contacts a and b by the active signal C of the CAS system, and C' A
The CAS system operates in synchronization with the s'- signal. In other words, it becomes possible to operate in base mode.

In this way, two functions were switched depending on whether or not the MSI and MS2 were connected.

[Invention or problem to be solved]

As mentioned above, when switching the conventional function, it is done by hardware, such as by performing a master slice on the contacts MSI and MS2 in the subsequent process of the diffusion process, or by providing a fuse and cutting it with a master saver or the like. was. Therefore, there is a drawback that it is impossible to switch the assembly.

Unlike the above-described conventional method for switching functions using hardware, the present invention is different in that it uses a software method for switching functions depending on the type of dummy cycle.

[Means to solve the problem]

The dynamic random access memory of the present invention is configured to include a determination circuit for switching the function of the device according to the type of dummy cycle during initial settings after power-on. Ru.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

First, the present invention will be explained in detail with reference to FIG.

In this embodiment, the determination circuit for switching the function of the device is a CBS (CAS before RAS).
) It is composed of a determination circuit 11, a one-shot generation circuit 12, and latch circuits 13 and 14.

In the present invention, the dummy cycle enters the NBL mode during the last-only refresh (RAS only refresh, hereinafter referred to as "ROR"), and the dummy cycle enters the NBL mode during the last-before-last-refresh (CAS).
before RAS refresh, hereinafter "C"
A switching determination circuit is provided to switch the function using software so that the system enters the page mode when the system is in the "BR" mode.

In FIG. 2, RAS is a row address strobe, and m is a column address strobe, which are external input signals. A-A, ・A2... is an inverting circuit, B-B
, ・B2 is a NAND circuit, C is a NOR circuit, D is a delay circuit, Qp+-Qp□ is a P-channel transistor, Q
NI・QN2・Qt”C6 is an N-channel transistor,
1 is CAS system control circuit, 2 is NBL system control circuit, 5EE
ND is a sensing completion signal and a CAS system start signal.

The operation of the present invention is such that the output M of the latch circuit 13 is turned on with the πτ signal/"Ch, - signal at a high potential."
can be brought to a low potential. After that, when executing a dummy cycle, for example, in the case of the embodiment shown in FIG.
When OR is performed, the RAS signal is active! When changing from (low potential) to reset state (high potential), N
A one-shot pulse from a high potential to a low potential is generated at the output of the AND circuit B1, and a high potential is generated at the output M of the latch circuit 13. At the same time, Qp+・QNI of latch circuit 1
becomes non-conductive and maintains the latched state. Also, the output M
is input to the first stage of the CAS system control in FIG. 3, and keeps transistors Q5 and C6 always conductive. This corresponds to the state in which the MSI/MS2 of the prior art described above is connected, and enables NBL mode operation. After this C
Even if BR is performed, since the output M of the latch 13 is input to the NOR circuit C2, the output of the latch circuit 14 maintains a low potential.

Next, if you perform a CBR refresh after turning on the power,
A level change from a high potential to a low potential occurs in the output of the NAND circuit B2, and the output of the latch circuit 14 becomes high, and at the same time, the transistor Qp+.

becomes non-conductive and maintains the latched state. Latch circuit 1
Since the output of 4 is input to the NOR circuit (Z), the output M of the latch circuit 13 holds a low potential, and its fil R
Even if the OR is performed, the output M is not affected. Therefore, transistors Q5 and Q6 always maintain a non-conducting state, which corresponds to the disconnected state of MS1 and MS2 of the prior art described above, and enable operation in page mode.

〔Effect of the invention〕

As explained above, the present invention provides a judgment circuit for switching functions according to the type of dummy cycle, so that functions can be switched according to software, and one device can have multiple types of functions. effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention, and FIG. 2 is a V circuit diagram showing an example of a configuration according to a conventional technique. 1...CAS system control circuit, 2...NBL system control circuit,
11... CBR determination circuit, 12... One shot generation circuit, 13 and 14... Latch circuit.

Claims (1)

[Claims] In dynamic random access memory,
A dynamic random access memory characterized by comprising a determination circuit for switching the function of the device according to the type of dummy cycle during initial setting after power-on.