JPH03176900A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten test time at a wafer state in spite of specification by setting the level of at least one of second deciding signals at the level corresponding to the prescribed level of a first decision signal compulsorily with the first deciding signal. CONSTITUTION:When a bonding terminal 11 is set at an NC state not being connected to any part, a bonding switching signal BO goes to a low level, and the deciding signal B1 goes to the low level. Since the judging signal B1 is set at the low level, the judging signal NBL goes to the low level inspite of the connecting state of an input switching part 21. Therefore, the same state can be set as when a signal FNBL goes to the low level, then, input/output data can be processed with four bits. In such a way, it is possible to perform a test in a short period of time at the wafer state in spite of the specification.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory whose type can be determined by a determination signal whose level is set according to the connection state of bonding terminals and switching of masks. .

[Conventional technology]

In semiconductor memories, as typified by dynamic RAMs, the test time increases as the capacity increases, and the diffusion period becomes longer due to the complexity and miniaturization of the manufacturing process.

Therefore, we have developed products with different output data bit configurations and functions.
It is possible to deploy the same pellet by switching fuses, aluminum wiring masks, and bonding points, making it easy to adjust production for each product even if the diffusion period is long, and allowing simultaneous development of multiple products.

In particular, regarding the bit configuration of output data, products with multiple bit output require shorter test time than products with fewer bits output even with the same memory capacity. Tests are conducted in a multi-hit configuration to reduce selection test time.

In the conventional semiconductor memory of this type, as shown in FIG.
■The power potential. The mask can be switched to the 0 point or the ground potential point, and the signals FSC and FNBL are sent to the inverter I4. I5
．． Engineering 8. Judgment signal generators 2B and 2D amplified by I3 and output as judgment signals SC and NBL, bonding terminal 11, inverters II and I2, and N-channel M
It is equipped with an O8 type transistor Ql, and the bonding terminal 11 is at the power supply potential ■. . It has a determination signal generation circuit 1 that outputs a determination signal Bl of a predetermined level depending on whether a point is touched or not, and is configured to determine the type based on the determination signals Bl, SC, and NBL.

Next, the operation of this semiconductor memory will be explained.

Table 1 shows the types developed by the combination of mask switching and bonding switching of the semiconductor memory shown in FIG.

Table 1 For example, the bonding switching signal BO is set to the power supply potential voo, and the signal FSC is set to the ground potential (hereinafter referred to as GND) signal FN.
When BL is GND, it becomes a 1-bit output first page product (XIF, P,), and when the bonding terminal 11 is not connected to anything (hereinafter referred to as NC), it becomes a 4-bit output first page product ( X4 F, P
,) becomes.

Similarly, the signal FSC is at the power supply potential V. signal FNBL is GN
When the voltage is D, the bonding switching signal BO is at the power supply potential V. . In this case, it becomes a static column product (Xi S, C,) with a 1-bit output, and the bonding terminal 11 is N.
C is a 4-bit output static column product (X4
S, C,). The bonding switching signal B○ is the power supply potential ■. 0, signal FSC is GND, signal FNBL is power supply potential V. . If so, it is a nibble product with 1-bit output (XI NI
BLE).

[Problem to be solved by the invention]

In the conventional semiconductor memory described above, for example, the signal FSC is set to GND, and the signal FNBL is set to the power supply potential v. .

When using a Xi NIBBLE product, the bonding switching signal BO is always at the power supply potential ■. Since it is necessary to set the value to 0, the test in the way/'1 state is performed in a 1-bit output configuration, which has the disadvantage that the test time becomes longer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that can be tested in a short time regardless of the product type.

[Means to solve the problem]

The semiconductor memory of the present invention includes a bonding terminal, and a first level that is at one of the first and second levels depending on whether or not the bonding terminal is connected to a first potential point of a predetermined potential. A first determination signal generation unit that outputs a determination signal of the above is connected to either the first potential point or a second potential point having a different potential from the first potential point by switching the mask. and a plurality of second determination signal generation units each outputting a second determination signal of a level corresponding to the potential point to which the input switching unit is connected, =6 - In a semiconductor memory whose type can be determined based on the first and second judgment signals, at least one of the second judgment signals is forcibly set to the first judgment signal.
A level switching means is provided to set the level corresponding to a predetermined level of the determination signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory shown in FIG.
8 to a two-man powered NAND gate G1, this NAN
The output of the input switching section is connected to one input terminal of the D gate, the output of the judgment signal generating section 1, that is, the first judgment signal B1 is connected to the other input terminal, and the input switching section 21. The determination signal generating section 2A is formed together with the inverter (2) 3, and the determination signal NBL is forced to the GND level by bringing the bonding terminal 11 into the NC state during a test of the wafer state.

Here, a NAND gate 1, a connection between the input terminal of this NAND gate 1 and the output terminal of the determination signal generation section 1,
And setting the bonding terminal 11 to the NC state serves as a level switching means.

Next, the operation of this embodiment will be explained.

When the bonding terminal 11 is brought into the NC state, the bonding switching signal BO becomes low level, and therefore the judgment signal Bl
is at a low level.

Since the determination signal B1 is at a low level, the determination signal NBL is at a low level regardless of the connection state of the input switching section 21.

Therefore, the signal FNBL is at low level (GND)! :.

As can be seen from Table 1, X4F, P,
, X4 S, C, and can process input/output data in 4 bits.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

This embodiment includes a decision signal generating section IA having the same configuration as the decision signal generating section 1, and a decision signal generating section 2B of the first embodiment.
Change the inverter 4 to a two-man powered NAND gate G2, connect the output of the judgment signal generator IA to one input terminal of this NAND gate G2, and connect the bonding terminal 11 to the NAND gate G2.
As state C, the determination signal SC is forcibly set to a low level,
X4F.

This allows testing to be performed as P, and has the advantage that there is no need to change the test program.

〔Effect of the invention〕

As explained above, the present invention is configured to forcibly set the second judgment signal to a level corresponding to the predetermined level of the first judgment signal, so that the test in the wafer state can be performed with multiple bits regardless of the product type. This has the effect of allowing testing to be performed in a short time because it can be performed using the input/output mechanism of

FIG. 2 is a circuit diagram showing an example of a physical memory.

1, L, 2A to 2D...determination signal generation section, 11 bond ink terminal, 21...input switching section, Gl.

G2...NAND gate, ■1 to ■8...inverter, Ql, G2...transistor.

Claims (1)

[Scope of Claims] 1. A bonding terminal that is provided with a bonding terminal and is at one of the first and second levels depending on whether or not the bonding terminal is connected to a first potential point of a predetermined potential. A first determination signal generating section that outputs one determination signal, and one of the first potential point and a second potential point having a different potential from the first potential point by switching the mask. Each input switching unit is provided with an input switching unit that can switch the connection, and each of the input switching units is provided with a plurality of second determination signal generation units that outputs a second determination signal of a level corresponding to the potential point to which the input switching unit is connected. , in a semiconductor memory whose type can be determined based on the first and second judgment signals, at least one of the second judgment signals is forcibly set to a predetermined value of the first judgment signal. A semiconductor memory characterized in that it is provided with a level switching means for setting a level corresponding to the level of the semiconductor memory. 2. At least one of the second determination signal generation sections includes a NAND gate that inputs the signal from the input switching section to the first input terminal and inputs the first determination signal to the second input terminal;
2. The semiconductor memory according to claim 1, further comprising an inverter for inverting the output of the ND gate.