JPH01257349A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To simply design a ROM by a method wherein the ROM is constituted of a total of two kinds of cells, i.e., one kind of ROM fundamental cell using a fundamental cell and one kind of logic cell used to write a data, in order to reduce an amount of a cell library for ROM use. CONSTITUTION:In a gate array according to a master slice system, a diffusion region ps where a potential of VDD has been supplied to a P-ch transistor and a diffusion region ns where a potential of VSS has been supplied to an N-ch transistor are arranged at the outside of a fundamental cell; the diffusion regions ps, ns and source regions 101-103, 104-106 of the P-ch and N-ch transistors inside the fundamental cell are connected by arranging a wiring part and a logic cell having the information on a contact 201; a fixed potential is supplied to the source regions. Cells constituting a ROM are one kind of ROM fundamental cell and one kind of logic cell. By this setup, when a ROM data is written, the degree of freedom when an integrated circuit is designed is high and this circuit can be designed simply and easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and relates to an R method for configuring a ROM in a master slice gate array.
This relates to the structure of OM data writing.

[Conventional technology]

Currently, when configuring a logic including ROM in a master slice gate array that realizes dedicated logic by manufacturing the basic cells first and changing the wiring process, (1) the basic cells are (2) A method in which only the ROM area is replaced with a dedicated ROM basic cell in which ROM data is written, and (2) a method in which data is written by connecting the basic cell and the power supply layer with wiring without using a ROM basic cell. exist.

Comparing method (1) and method (2), method (1) differs in ROM size and ROM data depending on the logic of the integrated circuit that constitutes it, and requires dedicated ROM data for each logic circuit. A written ROM area is required. Therefore, it is impossible to realize dedicated logic by changing only the wiring process, and there is no method suitable for gate arrays that is characterized by realizing a dedicated integrated circuit in a short period of time by changing only the wiring process. , (2).

[Problem to be solved by the invention]

However, when realizing ROM in method (2), R
There is a problem with the OM data writing method.

In case (2), ROM data is written by supplying vSS or VDD from the power supply layer to the source diffusion region of the transistor in the basic cell.

At this time, if power is supplied using a wiring layer in the same way as connecting the basic cells to configure logic, this will be realized in the intra-cell wiring of the basic cell that becomes a single ROM cell. A plurality of ROM basic cells having ROM data are required.

Therefore, as the size of the cell library required for logic design increases, the method of arranging ROM basic cells when configuring a ROM using ROM data possessed by ROM basic cells becomes a problem.

The present invention solves the above problems, and provides a ROM configuration method that takes advantage of the feature that a dedicated integrated circuit can be realized by changing only the wiring process in a master slice gate array. The purpose is to provide a data writing method.

[Means to solve the problem]

In the semiconductor integrated circuit device of the present invention, in a master slice type gate array, an expanded IIks where a potential of VDD is supplied to the Pch transistor side outside the basic cell.
A diffusion region to which a potential of vSS is supplied exists in the L region and the Nch transistor side, and a logic cell having wiring and contact information is arranged between the diffusion region and the source regions of the Pch and Nch transistors in the basic cell. A fixed potential is supplied to the source region.

(Example) FIG. 1 shows a layout diagram of the basic cell and the diffusion region located outside thereof in an example of the present invention. In the figure, ps,
Conventionally, ns exists for the purpose of suppressing channel leakage between transistors, and the diffusion region ps located on the Pch transistor side is fixed at a potential of VDD, and the diffusion region ns located on the Nchl transistor side is fixed at a potential of vSS. .

In the embodiment of the present invention, the ps is extended toward the Nch transistor and the ns is extended toward the Pch transistor for the purpose of supplying power to the transistors in the basic cell.

FIG. 2 shows a logic cell having wiring and contact information according to the present invention. The purpose of having a contact in a logic cell that connects a wiring layer and a diffusion region is to provide a contact between the basic cells when the basic cell does not become a ROM basic cell when realizing an arbitrary integrated circuit by providing a contact to the basic cell. The purpose of this invention is to prevent a decrease in the degree of freedom in wiring even if there is an unnecessary connection between the connection wiring and the contact.

FIG. 4 is a structural layout diagram of a ROM cell according to the present invention in which the basic cell shown in FIG. 1 is used as a ROM basic cell and ROM data is written using the logic cell shown in FIG. Dotted lines indicate logic cells, and ps and ns correspond to ps and ns in FIG. FIG. 3 shows a logic diagram of the 1-bit x 2-word ROM shown in FIG. 4.
2. OUT is Gl, G2. *D:1. The ROM data of D:2 is output to OUT by controlling the gate electrodes of Gl and G2.

The ROM data, Dil, and Di2 in FIG.
This corresponds to al and a2 in the figure. When writing ROM data, the ROM data is “L”.

In the case of W'', for the purpose of connecting the ns and al located on the Nch transistor side, the logic cell shown in FIG. Similarly, when the ROM data is "Hi", in order to connect the ps located on the Pch transistor side to 32, the internal contact of the logic cell is located on the ps, Place it at a position where the internal wiring connects to a2.

Since writing of ROM data in this method is realized by arranging logic cells, ROM cells into which necessary ROM data are written at the logic design stage are used as general logic cells, NAND, and NAND.

It is possible to configure a ROM of any size by using it in the same way as R1. At this time, the cells constituting the ROM are only one type of ROM basic cell and one type of logic cell, and this ROM data writing method has a high degree of freedom at the stage of designing an integrated circuit.

〔Effect of the invention〕

As described above, according to the present invention, the ROM is constituted by a total of two types of cells: one type of ROM basic cell using the basic cell and one type of logic cell used for writing data. The amount of cell libraries for ROM is small, which simplifies ROM design, and by taking advantage of the features of the master slice gate array, the mask substrate can be used for R
Since it is the same as an integrated circuit that does not include oM, the ROM
Similar to integrated circuits that do not include integrated circuits, it has the advantage that it is possible to respond in a short period of time by changing only the wiring process.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of the basic cell and the diffusion region located outside the basic cell in an embodiment of the present invention. 101.102,103...PchTr diffusion region 104.105.106...NchTr diffusion region 107,108...Gate electrode ps...Diffusion region ns having a potential of VDD...Diffusion region having a potential of vSS FIG. 1 is a logic cell diagram having wiring and contact information according to the present invention; FIG. 201...Contact 202...Metal wiring layer Figure 3 shows Nch transistor l bit x 2 words RO
It is a logical diagram of M. FIG. 4 is a structural layout diagram of a ROM cell according to the present invention in which the basic cell shown in FIG. 1 is used as a ROM basic cell and ROM data is written using the logic cell shown in FIG. 401.402...Metal wiring layer and above Applicant: Seiko Epson Co., Ltd. Representative Patent Attorney Masayoshi Ueghi and 1 other person↑↑Cow+φφ μ−

Claims (1)

[Claims] In a master slice type gate array in which basic cells constituted by two pairs of C-MOS transistors in which a Pch transistor and an Nch transistor have a common gate are regularly arranged, a Pch transistor is placed outside the basic cell.
There is a diffusion region on the ch transistor side to which a potential of VDD is supplied, and a diffusion region on the Nch transistor side to which a potential of VSS is supplied, and the diffusion region and P in the basic cell exist.
A semiconductor integrated circuit device, characterized in that source regions of channel and Nch transistors are connected by arranging logic cells having wiring and contact information, and a fixed potential is supplied to the source regions.