JPH01255923A - Data processor - Google Patents

Abstract

PURPOSE:To improve the arithmetic speed of a data processor by executing respective types of arithmetic operations directly by a data transferring device (DMAC) with use of an arithmetic means without using the control program of a central processing unit (CPU). CONSTITUTION:A CPU 1 sets the address information, etc., of the arithmetic data in a memory 3 to the register of a direct data transferring device (DMAC) 2. The DMAC 2 executes the succeeding arithmetic operation with an arithmetic means 5. The means 5 executes respective types of arithmetic inputted from a bus circuit 4. The result is outputted to an arithmetic result selecting means 6, only the result of the special arithmetic type is selected and held to an accumulating means 7 at the time of inputting a chip selecting signal. It is outputted to the bus circuit 4, fed back to the means 5 and the above-mentioned arithmetic operation is executed. Thus, the arithmetic speed of the data processor can be improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data processing device that can investigate data in memory and perform operations on data in memory at high speed, and improves processing speed even when a large amount of data is in memory. In a data processing device that includes at least a central processing unit, a direct data transfer device, a storage device, and a bus circuit that interconnects these, a calculation means for performing various operations on data, and an operation method in the calculation means are provided. an operation result selection means for selecting only the results of a specific operation type from among the results obtained, and the operation results selected by the selection means are accumulated when a chip select signal is input, and are returned to the bus circuit. In addition, storage means that operates to feed-hack to the calculation means are provided.

[Industrial application field]

The present invention relates to a data processing device, and more particularly to a data processing device that includes a microprocessor, a DMA control device, and a memory, and is capable of examining data on the memory and performing operations on the data on the memory at high speed.

In recent years, with the diversification of expression formats, such as character sizes, character pitches, character types, character shapes, foreign languages, graphs, image processing, form overlays, etc., there is a great demand for bitmap memories.

A large amount of memory is used for this bitmap memory, and even more memory must be used to meet the demand for more detailed representation. There is a desire to improve data processing speed in order to process this large amount of data in memory.

[Conventional technology]

FIG. 5 shows the configuration of a conventional data processing device.

In the figure, 1 is a central processing unit (hereinafter referred to as CPU) equipped with a work register WR and an index register IX, 38 is a random access memory (hereinafter referred to as RAM) in which a control program is stored, and 3B is a data RA.
M and 4 each indicate a bus circuit that interconnects the aforementioned devices. In addition to the above configuration, a data processing device generally includes a display 20 for displaying data, etc.
is connected to the bus circuit 4 via the D/A converter 21 and the amplifier circuit 22.
A printer 30 is connected to the bus circuit 4 via an I/F circuit 31. Note that the printer 30 and I/
It is connected to the F circuit 31 via a Centronics interface or the like. Further, the control program RAM 3A and the data RAM 3B may be the same RAM 3 but have separate internal areas.

In the data processing apparatus configured as described above, a case will be described in which data in one area or all areas in the data RAM 3B is sequentially operated to obtain a result. Such calculations are used to check the functionality of the RAM after the device is powered on, and to check the presence or absence of data when printing using a printer.

Here, for example, a process of sequentially ORing data from address 100 to address 109 and obtaining the result will be explained using the flowchart of FIG.

First, in step 601, "0" is put into the work register WR in the CPUI to clear the contents.

Subsequently, in step 602, the calculation start address 100 is entered into the index register IX of the CPUI. and,
Proceeding to step 603, there is an O between the data at the address pointed to by the index register
Performs the R operation and stores the result in the working register WR. In this case, if the data at address 100 is "1", "1" will be stored in the work register WR. In step 604, the address of index register IX is updated to 1 address. In step 605, index register I
Determine whether the address of X has reached the final address 110, and
If X≠110 (NO), return to step 603 and select O.
The R operation and the address of the index register IX are updated, and when IX=110, this routine ends.

In the process described above, if the repeated part of the process from step 603 to step 605 is coded using instructions for Motorola's M6800 microprocessor, the result will be as follows.

Label Instruction Operand Cycle count LI
0RAA O,X 5INX
4 CPX DI 5BNE
Ll Total number of 4 cycles 18 As described above, it can be seen that the conventional data processing device requires 18 bus cycles every time one byte is processed.

[Problem to be solved by the invention]

However, among the bus cycles mentioned above, one cycle for reading calculation data is essential, but the other one is essential.
The 7 cycles are necessary for program operation, and C
Since the PUI always operates while reading control programs one by one from the control program RAM 2, there is a problem that the flow of data is slowed down only while the control program is flowing through the bus circuit 5.

For this reason, users may be forced to wait for long periods of time for devices that users are closely involved with, such as terminal devices or personal devices, for devices that are not closely related to them, such as large computers or communication control equipment in a computer center. Although the general rule is that users should not wait, the problem is that they end up making users wait.

For example, looking at the time from power-on until it becomes usable, conventional data processing devices generally write certain values in all areas and read them out sequentially to check the functionality of the RAM immediately after power-on. , a check is being made to see if there are any errors. This check is repeated several times with different values to improve confirmation accuracy. As a result, in devices equipped with RAM of IM bytes or more,
Users may have to wait more than 10 seconds after turning on the power until the device is ready for use.

Furthermore, when printing using a printer, it is necessary to sequentially overwrite character, graph, image, and form overlay data on the bitmap memory, and at this time, the data after the OR operation is written to the bitmap memory. It will be done. After that, divide the bitmap memory into rows,
It adds a line feed order to the print data and sends it to the printing mechanism control section. However, when there is no print data at all on a certain line, a method is used that saves transfer time and time to move the print head left and right, and sends only a command to break the paper by one line. In order to realize this method, it is necessary to check the area for one line on the bitmap memory within a short time when the paper is fed a new line, and to confirm that there is no print data. The problem was that it took a long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing apparatus that solves the problems of the conventional data processing apparatus and can improve data processing speed even when processing a large amount of data in a memory.

[Means to solve the problem]

A principle diagram of a data processing apparatus of the present invention that achieves the above object is shown in FIG.

In the figure, ■ is a central processing unit (CPU), 2 is a direct data transfer device (hereinafter referred to as DMAC), 3 is a storage device, and 4 is a bus circuit that interconnects these devices. It is prepared for. 5 is a calculation means, which executes various calculations on input data. Reference numeral 6 denotes a calculation result selection means, which selects only the results of a specific type of calculation from among the results calculated by the calculation means 5.

Further, reference numeral 7 denotes an accumulation means, which operates to accumulate the calculation result selected by the selection means 6 when the chip select signal is input, and returns it to the bus circuit 4, and also feeds it back to the calculation means 5. .

[For production]

In the data processing device of the present invention, during arithmetic processing, the address information of the arithmetic data in the data RAM is set in the register of the DMAC by the CPU, and from then on, an independent arithmetic circuit is used by the DMAC without going through the control program of the CPU. Then, the /f5 calculation is executed.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the data processing apparatus of the present invention, and the same components as those of the conventional data processing apparatus are given the same reference numerals.

Similar to the conventional device, the bus circuit 4 is connected to the CPUI, RAM 3A for control programs, RAM 3B for data, etc., as well as a display 20 and an I/F circuit 31 via a D/A converter 21 and an amplifier circuit 22. A printer 30 is connected via. Similarly, the printer 30 and the /F circuit 31 are connected via a Centronics interface or the like.

In the data processing device having the above configuration, in this embodiment, DMAC2 is added, and its register is used as the start address register B of the transfer destination of the command register CR1.
R is used as the transfer source data length register DL and the transfer source address register AR. Command register CR
is used to instruct the start of transfer or interrupt in case of abnormality, and is used to indicate the start address register Bl? of the transfer destination. Set the write I10 port L of the storage register 70, set the number of bytes of the operation target area in the transfer source data length register DL, and set the number of bytes of the operation target area in the transfer source address register AR. Set address.

In the present invention, an arithmetic circuit 50 is provided connected to the bus circuit 4, and performs various operations on data input from the bus circuit 4, such as logical product (AND) operation and logical sum (OR) in this embodiment.
operations, exclusive OR (EOR) operations, and comparisons (COM
PARE) calculation is executed, and the calculation result of the calculation circuit 50 is output to the selection circuit 60 and held therein. A comparison register 92 is connected to the bus circuit 4 and is used to input a comparison reference value to the arithmetic circuit 50 when the arithmetic circuit 50 executes a comparison operation. In this embodiment, a comparison register 92 is provided in the bus circuit 4 to allow the arithmetic circuit 50 to execute comparison operations at high speed. Circuit 50 is capable of performing comparison operations.

90 has an input connected to the bus circuit 4 and an output connected to the selection circuit 60
This selection register 90 causes the selection circuit 60 to select and output one of the calculation results of the four types of calculations described above. For example, the selection circuit 60 receives a signal input from the selection register 90 as “
00", outputs the result of the AND operation, "01", outputs the result of the OR operation, "10", outputs the result of the exclusive OR operation, and "11". If so, output the result of the comparison operation.

The calculation result output from the selection circuit 60 is input to the storage register 70, where it is temporarily held. Accumulation register 7
The arithmetic result held at 0 is output to the bus circuit 4 through the buffer 93 and is also input to the arithmetic circuit 50 via the feedback circuit 80. The arithmetic circuit 50 is the bus circuit 4
The data input from and this feedback circuit 80
The above-mentioned calculations are performed using the data manually input through the .

91 is a chip select signal generating circuit, and the output of this chip select signal generating circuit 91 is sent to each storage register 70. Selection register 90, comparison register 92
and input to the buffer 93. Only when the chip select signal from the chip select signal generating circuit 91 is input, the elements connected to the chip select signal generating circuit 91 are activated and operated.

The aforementioned arithmetic circuit 50, selection register 90, and comparison register 92 have different addresses, and by specifying these addresses, data can be transferred from the data RAM 3B to the arithmetic circuit 50, selection register 90, and comparison register. The data is written to the register 92. Further, the arithmetic circuit 50 calculates the data written from the bus circuit 4 and the data from the storage register 70, but if you want to clear the storage register 70 at the start of calculation, what is stored in the storage register 70? Even if the calculation circuit 5
0, it is ANDed with "0" input from CPtJ 1 via the bus circuit 4, and the result is written into the storage register 70.

FIG. 4 shows the configuration of a specific example of the arithmetic circuit 50 shown in FIG. 2. In FIG. The arithmetic circuit 50 includes an AND circuit 51, O
It includes an R circuit 52, an EOR circuit 53, and a comparison circuit 54 consisting of a combination of an EOR circuit 54a and an OR circuit 54b. Data from the bus circuit 4 is branched within the arithmetic circuit 50 and input to one terminal of an AND circuit 51, an OR circuit 52, an EOR circuit 53, and an EOR circuit 54a, and
Data from the comparison register 92 is input to the other terminal of the OR circuit 54a. The output of this EOR circuit 54a is inputted to one terminal of an OR circuit 54b, and the above-mentioned AND circuit 51, OR circuit 52, EOR circuit 53 and this
Data obtained from the storage register 70 via the feedback circuit 80 is input to the other terminal of the circuit 54b. Then, an AND circuit 51, an OR circuit 52, an EOR
The output of the circuit 53 and the OR circuit 54b is the selection terminal SEL.
The selection terminal SEL is connected to a selection register 90.

By configuring the arithmetic circuit 50 as described above, one of the arithmetic results of the four types of arithmetic operations described above can be selected by the selection circuit 60 and stored in the storage register 70.

Here, the operation of one embodiment of the data processing apparatus of the present invention configured as described above will be explained using the flowchart of FIG. The processing procedure for sequentially performing an OR operation for each byte of addresses from (IFFF) to (IFFF) 166 will be described.

In step 301, an initial value, for example (00), is set in the storage register 70. Specifically, (00) is written from the bus circuit 4 to the address (COOO) + b, which indicates the address of the storage register 70, and (00) is written to the address (Cool) r b, which indicates the address of the selection register 90.
If 16 is written, no matter what is stored in the storage register 70, the result will be (00), , by OAND fi calculation with (00), 6, and this will be written into the storage register 70. In the following step 302, an operation type is set in the selection register 90.

This time, we will perform an OR operation, so specifically, the above (C
OOI) r Write (01) 1b to address h.

Then, from step 303 to step 306, D
Set each register of MAC2. That is, in step 303, the transfer source address register A of DMAC2 is
Set R to the start address of the operation target address in data RAM 3B, specifically (1000), 6, and proceed to step 30.
At step 4, the number of bytes at the address to be operated on is stored in the data length register DL indicating the number of bytes transferred by DMAC2, for example (1000).
, 6 are set. Furthermore, in step 305, DMAC2
110 boat address for writing in the storage register 70 in the transfer destination address register BR, for example (COOO) +
The address b is set, and in step 306, the DMAC 2 is activated by writing to the command register CR from the CPUI.

When DMAC2 starts up, in step 307 the DMAC
2 is the first address (10
00), , , and sends it to the arithmetic circuit 50. Then, the arithmetic circuit 50 calculates A between this data and the data from the storage register 70.
It executes NDXOR, EOR, and comparison operations, and sends the operation results to the selection circuit 60. Since the selection circuit 60 receives an OR operation command from the selection register 90, in step 308 the selection circuit 60 selects the result of the OR operation from among the results of the operation of the operation circuit 50 and stores it for storage. register 70
write to.

The calculation result written in the storage register 70 is returned to the bus circuit 4 via the buffer in step 309, and is also input to the calculation circuit 50 via the feedback circuit 80 in preparation for calculation at the next address.

When the calculations so far are completed, in step 310, the DM
The address of the calculation target address of AC2 is incremented by one address, and it is determined in step 311 whether or not that address is the final address. If it is not the final address, the process returns to step 307 and the above-described OR calculation is repeated.

This OR operation is repeated as many times as the number of bytes in the data length register DL, and the routine ends when all operations are completed.

The calculation result in this routine is (COOO) + b
Since it is stored at the address, the calculation result can be obtained by reading this address.

In this way, in the data processing device of the present invention, various calculations are performed in the calculation circuit 50 by the DMAC2 without going through the CPUI. The calculation speed is dramatically improved compared to other devices.

The number of cycles in the repetitive part (steps 603 to 605 in FIG. 6) in the conventional example described above was 18, but the number of cycles in the repetitive part (step 307 in FIG. 3) in this embodiment was 18.
~311) The number of cycles is 1.

Note that the types of calculations of the calculation circuit 50 in FIG. 2 are not limited to the four types described above, and it is not necessary to always have four types of calculations.

Further, the address of the storage register 70 described above is not a fixed address, but may be variable, for example. If the address of the storage register 70 is made variable in this way, A
OOO address to cooo address, 8001 address to 0001
The present invention can be applied to a DMAC that can only shift the write destination sequentially, such as by address. Furthermore, even if address space is applied to bitmap space, it is essentially the same.

〔Effect of the invention〕

As explained above, according to the data processing device of the present invention, various calculations are performed by the DMAC using a separately provided calculation circuit without going through the control program of the CPU, so the calculation speed is faster than in the past. It has the effect of improving dramatically.

As a result, the data processing apparatus of the present invention has the advantage that the waiting time at power-on is shortened, and there is no wasted time when printing data or the like.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the data processing device of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the data processing device of the present invention, and FIG. 3 is an explanatory diagram showing the operation of the device of FIG. 2. , FIG. 4 is a block diagram showing the detailed configuration of the arithmetic circuit in FIG. 2, FIG. 5 is a diagram showing the configuration of a conventional data processing device, and FIG. 6 is a flowchart showing the operation of the device in FIG. be. 1...Central processing unit (CPU), 2...Direct data transfer device (DMAC), 3A
...RAM for control program, 3B...RAM for data, 4...Bus circuit, 5...
- Calculation means, 6... Calculation result selection means, 7...
・Accumulation means, 8... Feedback means, 5
0... Arithmetic circuit, 60... Selection circuit, 70...
...Storage register, 90...Selection register, 92
...Register for comparison. . Fig. 1 Configuration diagram of a conventional data processing device Fig. 5

Claims (1)

[Claims] 1. A data processing device comprising at least a central processing unit (1), a direct data transfer device (2), a storage device (3), and a bus circuit (4) that interconnects these, comprising: calculation means (5) for performing various calculations; calculation result selection means (6) for selecting only the results of a specific type of calculation from among the results calculated by the calculation means (5); The selected calculation results are accumulated when the chip select signal is input, and are sent to the bus circuit (4).
) and an accumulating means (7) which operates to feed back data to the arithmetic means (5). 2. The data processing device according to claim 1, wherein the arithmetic means (5) is provided with at least one type of operation: a logical sum operation, a logical product operation, an exclusive logical sum operation, and a comparison operation. 3. The computer according to claim 1, wherein the calculation means (5) is provided with at least a type of comparison operation, and a comparison value storage means (9) whose value can be changed is provided on the input side of the calculation means (5). Data processing equipment.