JPH0778103A - Shared access control device - Google Patents

Abstract

PURPOSE:To efficiently attain data processing through a shared device without generating discrepancy by providing a control part for controlling access to the shared device with a counting part and a waiting part. CONSTITUTION:The control part 1 is provided with the counting part 12 and the waiting part 13. When one (a5 e.g.) of plural processors accesses the shared device 2, the counting part 12 calculates the number K of continuous accesses and the waiting part 13 exclusively controls the access of the other processor b6 among the plural processors to the device 2 until the count value K (k is a positive integer) reaches K=p/m. Namely the control part 1 holds the connected state of a data transfer path between a certain specific processor and the device 2 until at least the count value of the counting part 12 reaches a prescribed value based upon a signal outputted from the waiting part 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to transmitting and receiving data between a plurality of processors via a commonly accessed device in a multiprocessor configuration.

In recent years, the number of bits of processing units of various processors including a microprocessor is 8 bits and 1
It is increasing to 6 bits, 32 bits, and 64 bits. Along with this, the number of bits of the data transfer interface between the processor and other devices (for example, the bit width of the data bus) is also increasing.

On the other hand, the number of bits of data transmitted and received at one time between a plurality of processors is "8" bits for alphanumeric characters, "16" bits for kana-kanji characters, and "64" for double precision floating point data of 64 bits. There are various cases such as "16" bits, etc., although the bit and the address data of the memory depend on the memory capacity. Furthermore, when a large amount of data is transferred, it is several KB (kilobytes) to several tens of KB.

The present invention relates to processing when the number of (significant) bits forming such data is larger than the number of bits of the data transfer interface.

[0005]

2. Description of the Related Art A conventional technique described below is a case where a device commonly accessed by a plurality of processing devices is a shared memory.

In the prior art, the number of consecutive accesses K
Is a case where K = 1 in each processing device and the number p of bits constituting the data is equal to or less than the minimum number of bits of the plurality of data transfer interfaces.

That is, if the number of bits of the data transfer interface between a certain processing device and the control unit is m and the number of bits of the data transfer interface between another processing device and the control unit is n, then p≤MIN (m , N ...).

FIG. 8 is an example of application of a conventional memory access device, and is a configuration diagram when applied to a printer controller. The main components of the printer controller 8a are the receiving circuit 15, the first processing device 5, the shared memory access control unit 1a, the shared memory 2a, the second processing device 6, and the like.
Bit map memory 16, CG memory 17, drawing circuit 1
8

The number of bits of the data transfer interface between the first CPU 5 and the control unit 1a is 16-bit bus A.
3, the number of bits of the data transfer interface between the second CPU 6 and the control unit 1b is 32 bits on the bus B4.
It has a multi-processor configuration.

The CPU 5 stores print data in the shared memory 2a in 16-bit units, and the CPU 6 reads the print data in 32-bit units from the shared memory 2a. 7
Is a personal computer or other host, 8a is the printer controller, and 19 is a printer. Host 7
The printer controller 8a and the printer controller 8a are not directly related to the present invention, but 1-bit serial transmission (RS232C), 8
It is connected by an interface such as a bit centro interface or a 16-bit system bus.

The shared memory 2a is a shared memory that can be accessed by both the CPU 5 and the CPU 6. The capacity is, for example, 64 KB (kilobytes), and the specific area 21a
The data area 22a and the data area 22a, the address is attached in byte units, and the addressing (addressing) is possible with 16 bits (corresponding to 64 KB).

The capacity of the specific area 21a is 32B (bytes)
And the addresses are 0 to 31. When displayed in hexadecimal becomes "0 _H" ~ "1F _H". (When displaying the following hexadecimal "0 _H", expressed as such "1F _H".) The address of the data area 22a is 32 to 65
535. When displayed in hexadecimal, "20 _H " to "FF
FF _H ”. (The capacity is 64KB-32B.)
The bitmap memory 16 stores the result of dot development of character and graphic data.

The CG memory 17 stores font data for developing characters into dots. The connection between each of these components is as follows.

(1). The data transfer bus A3 has 16 bits, that is, m = 16, and the circuits connected to this bus A3 are the memory access control unit 1b, the CPU 5, and the receiving circuit 15.

(2). The data transfer bus B4 has 32 bits, that is, n = 32, and the circuits connected to this bus B4 are the memory access control unit 1b, the CPU 6, the bit map memory 16, the CG memory 17, and the drawing circuit 18.
Is.

(3). The shared memory access controller 1a and the CPU 5 are connected via a plurality of control signal lines 30. One of the plurality of control signals is referred to as “DAC
K "signal. The "DACK" signal is used by the memory access control unit 1b to notify the CPU 5 of the completion of data transfer using the bus A3, that is, the completion of data transfer with a bus bit width of 16 bits. By this completion notification, both processors can perform interrupt access to the shared memory 2a, and the memory access control unit 1a connects the data transfer path to the processor that accessed earlier and starts data transfer. .

(4). Memory access control unit 1a and CP
It is connected to U6 via a plurality of control signal lines 40. One of the control signals is "READY"
Signal. This "READY" signal is the same as in (3) "D
The shared memory access control unit 1a has the same function as the "ACK" signal, and notifies the CPU 6 of the completion of the processing, that is, the completion of the data transfer of the bus bit width of 32 bits. By this completion notification, the interrupt access to the shared memory from both devices becomes possible, and the memory access control unit 1a establishes the data transfer path to the processing device that has accessed earlier and starts the data transfer.

(5). The shared memory access control unit 1a and the shared memory 2a are connected by a 32-bit signal line 60. Since the CPU 5 and the shared memory access control unit 1a are connected by the 16-bit bus A3, the CP
When U5 accesses the shared memory 2a, partial read / write (partial storage / read) is performed on the 32-bit shared memory 2a. For example, the CPU 5 uses the address “0, 1, 2, 3” (that is, 32) of the shared memory 2a.
Bit), address "0, 1" (16 bits)
Alternatively, data is partially stored / read out at the address "2, 3" (16 bits).

(6). The CPU 5 and the shared memory access controller 1a are connected by a 24-bit address bus 31, and address information for access is sent using this address bus 31.

(7). Address information for access is sent to the CPU 6 and the shared memory access control unit 1a using the bus B4. This means that data of both address information and data information is exchanged using the bus B4. The address information and the data information are distinguished by one of the plurality of control signal lines 40.

(8). The CPU 5 and the CPU 6 are directly connected by the control signal line 50. Control signals are transmitted and received through this signal line. Immediately after the power is turned on, while the CPU 5 initializes a certain address of the specific area 21a of the memory 2a--for example, the address "0"-(clears "0"), the CP
The U5 outputs a control signal to the CPU 6 via the control signal line 50 to bring the CPU 6 into an inoperative state. After the initialization process is completed, the CPU 5 releases the control signal to the CPU 6, and the CPU 6 starts its operation. This is because the CPU 5 first stores valid data in the shared memory 2a, and then the CPU 6 reads the valid data from the shared memory 2a so that the subsequent processing can be continued.

If the CPU 6 accesses the address "0" of the shared memory 2a before the CPU 5 and the address "0" has a certain value (a value other than "0"),
The operation of the CPU 6 may print wrong characters.

(9). As described in (3) and (4) above, the memory access control unit 1a includes the CPU 5 or the CP.
When the shared memory 2a is accessed from U6,
Perform exclusive control. The data transfer path of the CPU that has accessed earlier is brought into the connected state, and the other data transfer path is brought into the disconnected state.

That is, if the shared memory 2a is accessed from one CPU and the shared memory 2a is subsequently accessed from the other CPU, the memory access controller 1a accesses the shared memory 2a. Until the above is completed, the data transfer path of the other CPU is cut off.

(10). For each bus 3 and 4 (1),
As described in (2), a plurality of circuits and devices are connected. Addresses (machine numbers) are assigned to the plurality of circuits and devices, and data can be exchanged between the plurality of circuits and devices by mutually specifying the addresses.

As described in (6) above, the address information when the CPU 5 accesses the shared memory 2a is sent using the 24-bit address bus 31, and the most significant 4 bits of these 24 bits are used. Is displayed.

For example, 24 as in "AXXXXXX _H "
The most significant 4 bits of the bit are designated by "A _H ".
Since the most significant 4 bits are “A _H ”, the memory access control unit 1a determines that the shared memory 2a is being accessed.

[0028] The address of when CPU5 to access the 32 bytes of a specific region 21a "A00000 _H" -
Is a "A0001F _H", the address of the data area is "A00020 _H" - "A0FFFF _H".

Similarly, the CPU 6 accesses the memory 2a.
Address information at the time of using the 32-bit bus B4
It is sent, but CPU6 is 32 bytes of specific area 21a
The address to access is "C000000
0_H~ "C000001F_HAnd the data area
The address is "C00000020_H~ "C000FFF
F _HIt will be. (The most significant 4 bits are "C_H"
Was decided as an example (design specification), and "A_H"
You may decide. ) By doing this, the memory
The access control unit 1b uses the most significant 4 bits of each address information.
Shared memory 2a is accessed by decoding
You can see that it is done.

FIG. 9 shows an example of data in a conventional specific area. In this specific area 21a of the shared memory 2a, information for mutual communication between the CPUs 5 and 6 connected to each bus is stored. . In each 2 bytes (16 bits) of addresses "0, 1" and "4,5" of this area, each CPU has a data area 22 of the shared memory 2a.
The access start address when accessing a is 2 bytes (16 bits) for each of the addresses "2, 3" and "6, 7"
Stores the access end address.

In the case of the printer controller 8a, every time the CPU 5 stores the print data in the data area character by character (16-bit unit), the CPU 6 writes the print data in the data area by 2 characters (32-bit unit). It is readable.

The print data read address of the CPU 6 is C
It is necessary for the PU 5 to be within the area where the print data is stored. This necessary condition can be confirmed by checking the size relationship of the addresses as follows.

Storage start address of CPU5≤read start address of CPU6, read end address of CPU6≤CP
Storage end address of U5 If this condition is not met, incorrect characters may be printed.

FIG. 10 shows an example of data in the conventional data area, and shows a state in which character code data is stored in units of 2 bytes in the data area 22a of the memory 2a. A memory configuration as shown in FIG. 9 and FIG.
The outline of the exchange of print data with the PU 6 is as follows.

.. First, as described in (8) above, after the power is turned on, the CPU 5 initializes (clears "0") the address "0" of the specific area 21a. As a result, even if the CPU 6 reads the storage start address for starting the print data reading, since "0" is stored, the CP
It can be seen that print data is not yet stored in U6. (The storage start address must be "32"(" _20H ")
Is greater. ). Next, the CPU 6 also initializes (clears "0") the addresses "4,5" of the specific area 21a. As a result, the CPU5
After storing the character data in the entire data area and before storing the character data for the second time, it is possible to confirm that the reading is completed by checking the contents of the addresses "4,5". If the reading is not completed, the storage of the character data is stopped.

Due to the above, the CPU 5 and the CPU 6
Data can be exchanged with and without conflict. ． The CPU 5 stores each character (16 bits) in the data area 22a. At this time, as described in (3) above, a "DACK" signal is output every time one character (16 bits) is stored, and the CPU 6 can access it.

However, as described above, since the address "0,1" of the specific area 21a is still "0",
The CPU 6 knows that the data has not been stored yet.

.. When a certain number of characters are stored, C
The PU 5 stores the storage end address in the addresses "2, 3" of the specific area 21a. The address "0, 1" is still "0".

.. Finally, the CPU 5 stores the storage start address in the address "0, 1" of the specific area 21a. As a result, the CPU 6 can be accessed. The operation of the printer controller 8a having the above configuration will be described in more detail with reference to a time chart.

FIG. 6 is a time chart (part 1) of the prior art, showing the above. First, when print data is sent from the host 7, the receiving circuit 15 aligns the data (16 bits if received in 1 bit).
Assemble into bits. ), And sends it to the CPU 5.

The CPU 5 sends the code data of one specific character, for example, "A", to the control unit 1a via the bus A3 at time "t1". When the control unit 1a completes the storage of the code data of the character "a", the time "t"
The "DACK" signal is set to "Low" at "2" and set to "High" at time "t3". Due to this change in the "DACK" signal, the CPU 5 is released from the data transfer process for one character at time "t3", and can perform the transfer process for the next character and other processes.

When the CPU 6 reads the character data after the time "t3", first the address of the specific area 21a is designated "0", the "data storage start address" is read, and then the "data storage end address". Read out. In this case, the information of the read address "0" is sent to the control unit 11a via the bus B4.

At time "t4", "0," in the specific area 21a
The "1" address is designated and the "data storage start address" is read. In this case, since the bus width is 32 bits,
32-bit data is transferred to the CPU 6.

The control unit 1a sends the 32-bit data to the CP
When the transfer to U6 is completed, at the time “t5”, the “READ
The "Y" signal is set to "Low", and "High" is set at time "t6".
h ”. By the change of this "READY" signal, C
The PU 6 is released from the data transfer processing at time “t6” and can perform the next processing.

The CPU 6 uses the specific area 2 read thereafter.
The contents of the address "0, 1" of 1a are checked, it is found that the "data storage start address" is "0", and it is determined that character data is not yet stored.

The CPU 6 determines that the time "t1" and the time "t".
Even if the memory 2a is accessed with "2", the CPU 5 is in the waiting state because the CPU 5 is accessing first. In this case, the memory 2a can be accessed at the time "t3", the data transfer path is brought into the connected state, and the data transfer is started.

FIG. 7 is a time chart of the prior art (No. 2), which is slightly more complicated than that of FIG.
The CPU 5 starts accessing the memory 2a at time "t11". After that, the CPU 6 starts accessing the memory 2a at time "t12", but the CPU 5 has already started accessing the memory 2a.
, The data transfer path is disconnected by the control unit 1b, access to the shared memory is suppressed, and a standby state is set. (See (9) above) At time “t14”, the access (data transfer) of the memory 2a of the CPU 5 is completed, the CPU 6 is connected to the data transfer path, and the CPU 6 shifts from the wait state to the data transfer state.

When the CPU 5 starts to access the memory 2a at time "t15" after the CPU 6 has entered the data transfer state, the memory access of the CPU 5 is suppressed this time, and the CPU 5 enters the waiting state.

When the 32-bit data transfer to the CPU 6 is completed at time "t17", the data transfer to the CPU 5 is started. As described above, in the related art, both the address information and the character information are 16 bits as a meaningful chunk of data, and the processing can be performed if at least 16 bits are accessed.

In order to realize this, one CPU irrespective of whether it is the specific area 21a or the data area 22a,
When accessing the shared memory 2a, the other C
The access to the memory 2a of the PU is suppressed and the PU memory 2a enters the waiting state (the data transfer path is in the disconnected state), and the processing completion signal
The change of CK "and" READY "enables the other CPU to access the shared memory 2a.

[0051]

As described above, when the data configuration (significant) number of bits p is larger than the number of bits m or n of the data transfer interface, the problem that data is not transmitted and received accurately. Occurs. (That is,
MIN (m, n ...) <p) For example, when the capacity of the memory 2a is increased to 64 KB or more in order to increase the processing speed, the addressing (addressing) is insufficient with 16 bits. become. When the capacity of the memory 2a is 128 KB, the number of bits for displaying the address is at least "17".
That is, "1 + 16" bits are required.

In this case, if "32" bits are considered as the number of bits for displaying the address, if the CPU 5 has the upper or lower 2 bytes (16 bytes) of the 32 bits,
If the CPU 6 accesses 4 bytes (32 bits) including 2 bytes (16 bits) of the storage start address at the time when the bit 6) is stored in the specific area 21a as the storage start address, incorrect address information is stored in the CPU 6 There is a problem that is taken into.

That is, of the 17 bits, only "1" or "16" bits are fetched and incorrect address information is transferred. In view of such a point, the present invention provides the CPU 5 until the CPU 5 continuously stores 2 bytes (16 bits) of data in the shared memory 2a twice.
It is an object of the present invention to provide a means for preventing 6 from accessing the shared memory 2a.

[0054]

The above problems can be solved by a shared access control device configured as follows.

FIG. 1 shows the principle of the present invention. (A). It includes a plurality of processing devices 5, 6, a shared device 2 commonly accessed by the plurality of processing devices, and a control unit 1 for controlling access to the shared device 2 by the plurality of processing devices 5, 6. Then, the control unit 1 and the processing devices 5,
6, there are data transfer interfaces 3 and 4, respectively, and the number of bits of one of the data transfer interfaces 3 and 4 is m.
In the shared access control device, the m may be different for each of the data transfer interfaces 3 and 4, and the number of bits constituting the data transmitted and received between the plurality of processing devices via the shared device 2 is p. The control unit 1 is provided with a count unit 12 and a wait unit 13, and the count unit 12 continues when one processing device a5 of the plurality of processing devices accesses the shared device 2. The number of times of access K is counted, and when the certain processing device a5 is accessing the shared device 2, the wait unit 13 determines that K is a positive integer and the count value is K = p / m.
Until (K is a positive integer), the access to the shared device 2 of the other processing device b6 among the plurality of processing devices is exclusively controlled.

(B). In (A) above, the “quote” is 0
Alternatively, if p / m = “quotient” + “remainder” is not 0 when the p / m = “quotient” + “surplus” is determined to be a positive integer, then K = the “quotient” +1 is reached and other The processing device b6 is configured to exclusively control access to the shared device 2.

(C). In the above (A), the p / m
Is provided with a plurality of counting units 12 corresponding to the respective processing devices (5, 6) such that 2 ≦ p / m. (D). In the above (A), (B), or (C), when the "remainder" is 0, the initial value of the counting unit 12 is the "quotient", and when the "remainder" is not 0, the counting unit 1
The initial value of 2 is set to the “quotient” +1, and the certain processing device a
Each time 5 accesses the shared device 2, the counting unit 12
Is decremented by "1", and the access to the shared device 2 of the other processing device b6 of the plurality of processing devices is exclusively controlled until the count unit 12 reaches 0.

[0058]

In other words, with the above configuration, when there is data having the number of bits p, the first processing device converts m-bit data to M (M = 1 to p / m (M is After accessing the shared device 2 consecutively for a positive integer)) times to generate a block of p-bit data, the second processing device can access the shared device 2.

Similarly, when the number of bits n of the data transfer interface of the second processing device is smaller than p, the second processing device converts n-bit data to N (N = 1 to p / n (N
Is a positive integer)) consecutively accessing the shared device 2, and then another processing device can access the shared device 2.

If p / m and p / n are not divisible, the number K of consecutive accesses is K = 1 + p / m or K = 1 + p / n. When m <n and p = n, K is the ratio K of the number of bits of the data transfer interface.
= N / m.

The wait unit 13 and the "DACK" signal and "R"
The role of the "EADY" signal will be described. As described above, the "DACK" signal or the "READY" signal is sent every time one access from a certain specific processing device is completed (transfer of the number of bits of the data transfer interface is completed).

In the prior art, this data transfer completion signal makes it possible for all devices including the certain specific device to access the shared device. If there is an access, the accessing processing device and the shared device can be accessed. The data transfer path between them becomes the connected state, and the data transfer is started.

In the present invention, every time one data transfer is completed to a certain specific processing apparatus that has accessed the shared device, the "DACK" signal and the "READ" signal are transferred as in the conventional case.
Although the "Y" signal is sent, the control unit holds the disconnection state of the data transfer path between the other processing device and the shared device until at least the counter unit reaches a predetermined value by the signal of the wait unit.

Further, the control section holds the connection state of the data transfer path between the certain specific processing apparatus and the shared apparatus until at least the counter section reaches a predetermined value by the signal of the wait section.

After the counter section reaches a predetermined value, the control section connects the data transfer path with the processing apparatus that has accessed the shared device earlier to connect the other processing apparatus and the shared apparatus. The data transfer path between them is disconnected.

By doing so, when data is transferred between a plurality of processors via the shared device, the content of the data can be guaranteed.

[0067]

The embodiment described below is for the case where the count value K of the number of consecutive accesses is K = 2, p is 32 bits, and m is
Is a case where the first processing device of 16 bits makes continuous access to the shared memory twice, and then the second processing device of n of 32 bits makes the shared memory accessible.

The present invention is applied when each processing device accesses a specific area of the shared memory.
Conventional techniques are applied when accessing the data area. FIG. 2 is a block diagram of an embodiment of the present invention, in which the present invention is applied to the printer controller of FIG. 8 described in the section of the prior art. Similar to the prior art, the first CPU 5
The number of bits of the interface between the control unit 1a and the control unit 1a is 16 bits, and the number of bits of the interface between the second CPU 6 and the control unit 1a is 32 bits.

Further, even if the shared memory 2 is composed of a multi-port memory, the present invention can of course be implemented. In FIG. 2, 8 is a printer controller, 1 is a shared memory access control unit, and 2 is a shared memory. The other components are the same as those in FIG.

The shared memory access control unit 1 is provided with a count unit 12 and a wait unit 13. The shared memory 2 has a capacity of 128 KB and includes a specific area 21 and a data area 22. Therefore, at least 17 bits are required for addressing the shared memory 2.
Here, 32 bits are considered as this address information.

The capacity of the specific area 21 is 32 B (bytes), and the addresses are 0 to 31. Also, data area 2
Address 2 is 32 to 131071. (Capacity is 1
28KB-32B. FIG. 3 is an example of data of a specific area in the present invention, and shows a situation in which the access start / end addresses of each CPU are stored. Since 17 bits are required for addressing as described above, 4 bytes (32 bits) are allocated as the capacity for storing each access start / end address.

FIG. 4 shows an example of data in the data area according to the present invention. Since each character has 16 bits of data, 2 bytes (16 bits) are assigned to each character. This figure is similar to the prior art.

FIG. 5 is a time chart of the present invention.
The operation of each circuit / device when the present invention is applied is shown. The present invention will be described below with reference to FIGS.

As described above, the access address information of the shared memory 2 of the CPU 5 is the 24-bit address bus 31.
The address information when accessing 32 bytes of the specific area 21 is "A00000 _H " ~
It is "A0001F _H ". Address information of the course data area is "A00020 _H" - "A1FFFF _H".

The access address information of the shared memory 2 of the CPU 6 is sent using the 32-bit bus B4.
Address information when CPU6 accesses a 32 bit particular region 21 "C0000000 _H" - "C00
0001F _H ”, and naturally the address information of the data area is“ C0000020 _H ”to“ C001FFFF _H ”.

By doing so, the control unit 1 decodes the most significant 4 bits of each address information, and if the decoding result is "A _H " or "C _H ",
It can be seen that the memory 2 is being accessed, and the middle 6
If ~ 17 bits are "0", it is known that the specific area 21 is being accessed, and if the middle 6 to 17 bits are not "0", it is clear that the data area 22 is being accessed.

As a matter of course, if the most significant 4 bits are not "A _H " or "C _H ", it means that another circuit or device connected to each bus is being accessed. In FIG. 5, the CPU 5 designates the address “A00000 _H ” at time “t21” and sets the data “0000”.
_Suppose you have transferred " _H ". In the shared memory access control unit 1, since the most significant 4 bits of the address data are "A _H ", the counter of the counter unit 12 is reset.

The control unit 1 sets the data transfer path between the shared memory 2 and the CPU 5 to the connected state, and the shared memory 2 and the C
The data transfer path with the PU 6 is disconnected. After that, even if the CPU 6 accesses the specific area 21 at time “t22”, the data transfer path is still held in the disconnected state by the wait unit 13, so that the data transfer is suppressed.

When the "DACK" signal is "High"-"Lo"
By changing from “w” to “High”, the counter of the counter unit counts up at time “t24”, and the value becomes “1”.

Subsequently, the CPU 5 designates the address "A00002 _H " at the time "t25" and sets the data "002".
0 _H ”is transmitted. "DACK" signal is "High"-
By changing from “Low” to “High”, the counter of the counter unit counts up at time “t27”, and the value becomes “2”.

Since the value of the counter becomes "2", the wait unit 13 sets the wait signal to "High"-"Low" at the time "t27", and the CPU 6 can access the memory 2.

That is, at time "t22", the address information has already been transferred from the CPU 6 to the control unit 1 using the bus B4, and the address information has been decoded.
The control unit 1 sets the data transfer path between the CPU 6 and the shared memory 2 to the connection state at time “t27”, and starts the data transfer.

When the data transfer from the memory 2 to the CPU 6 is completed, the "READY" signal changes from "High" to "Lo".
w ”-“ High ”. However, when the CPU 6 accesses the data area 22 at time “t22”,
Until the time "t24" when the "DACK" signal changes, C
Although the PU 6 is in the waiting state, the data area 22 can be accessed after the time “t24”. When a data area is accessed, since a group of (meaningful) data is in units of 16 bits, the control unit 1 can control the C unit irrespective of the wait unit 13 as described in the prior art.
The data transfer path between the PU 5 or CPU 6 and the data area 22 is set in the connected state to enable access.

In other words, the wait signal is valid only when the CPU 5 accesses the specific area 21. As described above, whether or not the specific area 21 is accessed can be easily determined by decoding the middle 6 to 17 bits of the access address information.

In the above, m is a 16-bit CPU and n is 3
In a multiprocessor system composed of a 2-bit CPU, the number p of data bits is 32.
As for the processing in the case of a bit, a CP having a 64-bit connection interface is further provided as a third processing device.
The situation is the same even if U is connected to the control unit 1a.

In this case, when p is 64 bits,
Until the CPU whose m is 16 bits completes the access to the shared memory four times in succession, the access to the shared memory by other CPUs is suppressed. As a matter of course, until the CPU having an interface of 32 bits completes the access to the shared memory twice in succession, the access to the shared memory of the other CPU is suppressed.

When p is 32 bits, access to the shared memory by other CPUs is inhibited until the CPU having the 16-bit interface completes the access to the shared memory twice in succession.

Further, a count unit and a wait unit are provided corresponding to each processing device, and the control unit receives the number of consecutive accesses K or the significant bit number p of data as an initial value from each processing device, and thereafter. It is possible to use a device that uses this value to control access inhibition.

In the above description, the value of p is a convention (specification) in advance, but it may be sent as a parameter from each processing device to the control unit prior to data transfer. The case where the number p of bits constituting the data is several bytes has been described above. However, even if the number p is several tens to several tens of KB, the count value K of the counter unit 12 only increases, and the general case of the present invention. The sex is not lost.

[0090]

As is apparent from the above description, according to the present invention, a control unit for controlling access to a shared device is provided with a count unit and a wait unit, so that a plurality of processes connected to the shared device can be processed. Efficient and consistent sharing by inhibiting access to the shared device from other processing devices until data access with a significant number of bits from one of the processing devices to the shared device is completed. There is an effect that data processing can be performed via the device.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a data example of a specific area in the present invention.

FIG. 4 is an example of data in a data area according to the present invention.

FIG. 5 is a time chart of the invention.

FIG. 6 is a time chart of the related art (No. 1)

FIG. 7 is a time chart of the related art (No. 2)

FIG. 8 is an example of application of a conventional memory access device.

FIG. 9: Example of data of a conventional specific area

FIG. 10: Data example of conventional data area

[Explanation of symbols]

1, 1a, shared memory access control unit 2, 2a shared memory 3 data transfer bus A 4
Data transfer bus B 5 First processing unit 6
Second processing device 7 Host 8, 8a Printer controller 12 Counting unit 13
Weight unit 15 Receiver circuit 16
Bitmap memory 17 CG memory 18
Drawing circuit 19 Printer 30, 4
0,50 Control signal line 60 Signal line 31
Address bus 21,21a Specific area 22,22
a Data area

Claims (4)

[Claims] 1. A plurality of processing devices (5, 6), a shared device (2) commonly accessed by the plurality of processing devices, and a shared device (2) of the plurality of processing devices (5, 6). ), And a data transfer interface (3, 4) exists between the control unit (1) and each processing device (5, 6). , The number of bits of one of the data transfer interfaces (3) is m, and the value of the m may be different for each data transfer interface (3, 4). Through (2), the plurality of processing devices (5,
6) In a shared access control device in which the number of constituent bits of data transmitted and received between p and p is p, the control unit (1) is provided with a count unit (12) and a wait unit (13), and the count unit (12) is provided. Counts the number of consecutive accesses K when one processing device a (5) of the plurality of processing devices accesses the shared device (2), and the wait unit (13) Certain processing device a (5)
Is accessing the shared device (2), it is assumed that K is a positive integer and the other processing device b (6) among the plurality of processing devices until the count value reaches K = p / m. A shared access control device, which exclusively controls access to the shared device (2). 2. In claim 1, when “quotient” is 0 or a positive integer, p / m = “quotient” + “remainder” is not K when the “remainder” is not 0. Quotient "+
A shared access control device, which exclusively controls access to the shared device (2) of another processing device b (6) among the plurality of processing devices until reaching 1. 3. The p / m according to claim 1, wherein the p / m is 2
A shared access control device having a plurality of counting units 12 corresponding to the respective processing devices (5, 6) such that ≦ p / m. 4. In the claim 1, the claim 2, or the claim 3, when the “remainder” is 0, the initial value of the counting unit (12) is set to the “quotient”, and the “remainder” is 0. If not, the initial value of the count section (12) is set to the “quotient” +
1, and each time the processing device a (5) accesses the sharing device (2), the count unit (12) is decremented by "1",
A shared access control device, which exclusively controls access to the shared device (2) of another processing device b (6) among the plurality of processing devices until the count unit (12) reaches 0. .