JPH01253369A - Flicker correcting device for solid-state television camera - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to easily change processing contents by detecting the mean level of each field via an averaging circuit to obtained a signal free from flicker component, dividing between said signal and the output of the averaging circuit containing the flicker component via a division circuit, and inputting the result of this division to a gain circuit for control of the circuit gain. CONSTITUTION:A video signal S10 contains the flicker component and is inputted through a video input terminal 1. An averaging circuit 2 averages the signals S10 for a single field period and transmits them synchronously with a vertical fly-back line. A filter LPF3 has characteristics for deleting the flicker component out of the output signal of the circuit 2 and obtains a signal by deleting the flicker component out of a signal S11. A delay circuit 4 functions to secure the coincidence in phase between the signals S10 and S11 and delays the signal S10 by three field. A gain control circuit 6 performs multiplication between the signal S10 and the output signal S14 of a division circuit 5 for deletion of the flicker component. Thus it is possible to attain the effect equivalent to the conventional ones with simple constitution containing just a single LPF.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a flicker correction device for a solid-state television camera that uses a solid-state image sensor and reduces flicker under fluorescent lamp illumination in a television camera.

Conventional technology When photographing with a television camera, the subject is illuminated by a light source that lights up at the mains frequency, such as a fluorescent lamp, and the vertical synchronization frequency (hereinafter referred to as rma) of the television camera
For example, if the power supply frequency (hereinafter referred to as fp) is different from f
When v is 60t4z and fp is 50t4z, flicker of 201-1z occurs in the photographed video. A conventional flicker correction device for a solid-state television camera is disclosed in, for example, Japanese Patent Laid-Open No. 123880/1983. In addition, in the example below, fv is 60Hz, f'p
will be explained as 50 t-Iz.

FIG. 10 shows a block diagram of this conventional flicker correction device for a solid-state television camera, where 1 is an input terminal for a video signal, 101 is a vertical R line portion where there is no video signal, and il −+ b→ Similarly, the switch circuit 106, which sequentially switches C→a→b→C..., has d −+ 6-1− f in the vertical retrace portion where there is no video signal.
-+ (Switch circuits 102, 103, 104 that switch i→e→f...) are, for example, the 12th
As shown in the figure, 106 is an LPF with the same characteristics that does not allow frequencies higher than 20 Hz to pass.
F103. LPF 104 (7) An averaging circuit that averages the output signal, 107 is the output signal of the switch 105 and the averaging circuit 1
06 is a division circuit that performs division of the output signal, 6 is a gain control circuit that multiplies the video signal input from input terminal 1 and the output signal of the division circuit, and 7 is an output terminal that outputs a signal from which flicker has been removed. It is.

The operation of the conventional flicker correction device for a solid-state television camera constructed in 6″4 as described above will be explained.

FIG. 11 is a diagram showing signals of various parts in the conventional example.

5110 is a video signal with flicker input through input terminal 1, and is a step-like signal that is repeated every three fields. Signals 5111, 5112° 5113 are LPF102, LPF103° LPF10, respectively.
4 input signals. Signal 8114°8115.811
6 is LPF102゜LPF103, LPF respectively
104(7) output signal.

Signal 11γ is the output signal of switch 105, signal 8118
5119 is the output signal of the averaging circuit 106, and 5119 is the dividing circuit 10.
7 (signal 5118/signal 8117).

In the signal 5110, every other field is DI, D2.
．． Assume that the signal D3 appears repeatedly. Assuming that the subject is a completely still image, and if Do is a flicker-free signal, then Dl: 11.D.

D2=I2・D.

D3=43・D.

becomes. 11. ! 2. I3 is a flicker component. D
1 to D3 are values that fluctuate up and down around the level of the signal DO, and the average value of 11 to D3 is 1.

The smoothing process in the LPFs 102 to 104 is represented by a function F. Signals 8114, 8115, 5116 (7) values are Dl,
D2. Assuming D3, D1=F(Dl) =7 (I 1・no) Since 11 is constant within one field, DI=11
−F(Do)=11・D.

Similarly, it can be expressed as below. The output signal 3118 (denoted below) is +13DO)/3 = DO(11-142+I3)/3 where the flicker is repeated every 3 fields and
The average value of is 1, so 11+I2-143=3. Therefore, it can be expressed as L=DO.

The value τ/go]- of the signal 5119 is L/D2:1/I2 L/D3=1/I3, as in the case of =1/11. The gain control circuit 6 multiplies the video output by 1/11 in the field of Dl, and similarly multiplies it by I3 in the field of D2, 1/X2, and 1/D3. Therefore, the output of the gain control circuit 6 in any field is Do, and the flicker component is removed.

Problems to be Solved by the Invention However, in the above configuration, it is necessary to prepare a plurality of LPFs having the same characteristics, which has the problem of increasing the circuit scale.

In view of this point, the present invention has provided a
An object of the present invention is to provide a flicker correction device for a solid-state television camera that reduces the circuit scale by reducing the circuit size to one.

Means for Solving the Problems The present invention provides an averaging circuit for detecting an average level of a video signal, an LPF for inputting the output of the averaging circuit, and an LPF for detecting an average level of a video signal.
A flicker correction device for a solid-state television camera, comprising a division circuit that divides a predetermined signal obtained from the output of the average circuit and the output of the average circuit, and a gain control circuit that controls the gain of the circuit according to the output of the division circuit. be.

Effect of the present invention With the above-described configuration, the averaging circuit detects the average level for each field, passes the average level through the LPF, obtains a signal from which the 7-flicker component is removed, and removes the flicker component. The output of the averaging circuit containing the flicker component is divided by a dividing circuit, and the output of the dividing circuit is input to a gain circuit to control the gain of the circuit, thereby obtaining a video signal from which flicker has been removed. .

Embodiment FIG. 1 shows a block diagram of a flicker correction device for a solid-state television camera according to a first embodiment of the present invention. In FIG. 1, 1 is a video signal input terminal, 2 is an averaging circuit that averages the video signal for one field period, 3 is an LPF that removes flicker components from the output signal of the averaging circuit 2, and 4
is a delay circuit that delays the output signal of average circuit 2, and 5 is L
a division circuit that divides the output signal of PF3 and the output signal of delay circuit 4; 6 is a gain control circuit that controls the gain of the circuit;
Terminal is an output terminal that outputs a signal from which the flicker component has been removed.

The operation of the solid-state television camera flicker correction device of this embodiment configured as described above will be described below.

FIG. 2 is a diagram showing signals of each part of this embodiment.

In the figure, the horizontal axis indicates time and field numbers, and the vertical axis indicates signal level. The explanation will be given below based on the same figure. The signal S10 is a flickering video signal and is inputted from the video input terminal 1.

The signal S1o is 510, where K is the field number.
(K), = I (K) · 5o (K). Here, I
(K) is a flicker component.

fso(K) is a flicker-free signal component.

The signal S1o fluctuates up and down around the level of the signal SO, and the average value of the signal is 1.

The averaging circuit 2 averages the signal S1o for one field period and outputs it in synchronization with the vertical flyback. Figure 2 811 is the average circuit 2
is the output signal of "〒0(K) signal S 1o(K:
If l is the averaged signal, then the following relationship holds true. Here, I and So are signal workers.

This is the signal obtained by averaging SO over one field period, and I is 1.
Since it is constant between fields, S11[K]=IC
K-1]・5o(K-1].

The LPF 3 is, for example, a filter having the characteristics as shown in FIG. 12 described above, and is used to obtain a signal by removing the 7-force component from the signal S11, but a simple trap filter shown below may also be sufficient. If the output of LPF3 is 812 (Kl), 812 (K) = (Sl 1 (
K-1)+811 (K-2':1+811(K-3)
)/3 = (I (K-2)5o(K-21+I(K-3)So
(K-3:]+I (K-4)SO[K-4))/3 Here, since there are few changes in adjacent fields, SO
(K-2: l = S million (K-31 s O (K-4) = 30 (K-s). Also, the flicker component is repeated every 3 fields, and the average value of the signal engineer is 1 Therefore, I (K−
2:l+I (K-3]+I (K-4:l=3. Therefore, 312(K):5o(K-3)(I(K-2)+X (
K-3)+I (K-4])/3=SO(K-3). The signal is shown at 512 in FIG.

Delay circuit 4 is a delay circuit for matching the phases of signal S10 and signal S11, and delays signal S1o by three fields. If the output of the delay circuit 4 is 813, s 13 (x) = s 11 (K-2):I [K-3
]5o(K-3:1. The signal is shown at 813 in FIG. 2.

The division circuit 6 performs the following calculations. If the output of the division circuit 5 is S14 (Kl, then 514(K)=S12(ICI/813(K)=sO(
K-3]/I (K-3]S.

(K-s) = 1/I (K-s) Here, from the periodicity of flicker, I (K:] = k[K-3]. Therefore, S14 (K) = 1/I (Kl and Become.

The gain control circuit 6 multiplies the video signal 810 and the output signal 814 of the division circuit 5. The output of gain control circuit 6 is
s(K), then Ss CKI=S10(K'l・814(K)=I(K
)・5o(K)/If:K) =SO([3) Flicker components can be removed.

As described above, according to this embodiment, the same effects as conventional ones can be achieved with a simple configuration having only one LPF.

FIG. 3 is a flicker correction device for a solid-state television camera showing a second embodiment of the present invention. In the figure, 1 is a video signal input terminal, 2 is an average circuit, 3 is an LPF, 4 is a delay circuit, 5 is a division circuit, 6 is a gain control circuit, and 7 is an output terminal, and the above is the same as in the first embodiment. It is. The difference from the first embodiment is that a limiter 2 is provided between the divider circuit 5 and the gain control circuit 6.
The reason is that 0 is set.

The operation of the flicker correction device for a solid-state television camera according to the second embodiment configured as described above will be described below.

FIG. 4 is a diagram showing signals of each part of this embodiment.

This will be explained below based on FIG. In this embodiment, it is assumed that an object crosses in front of the camera lens and blocks light. In Fig. 4, the signal S10 is blocked by K≦3 and becomes the signal DO, and when K≧4, every other field is D.
I, D2. Assume that the signal D3 appears repeatedly.

At this time, average circuit 2. LPF3. Delay circuit 4. The output signals of the division circuit 5 are converted into signals 511, 312, and 813, respectively.
It is shown at ゜814. As is clear from the figure, during several fields where the average level of the video signal changed significantly (K==
5.6) The division circuit 6 outputs a signal different from the intended correction signal.

The output signal of the division circuit 6 is sent to the limiter 2o. FIG. 5 shows an example of the input/output characteristics of the limiter 2o. As shown in the figure, the limiter 2o limits an unnecessarily large output signal and an unnecessarily small output signal of the division circuit 5 to predetermined levels h and 1, respectively. Normally, flicker components can be removed if the gain of the gain control circuit 6 can be varied by about 0.7 to 1.3 times. Therefore, the predetermined level h
1.3.1 to 0.7 and the gain of the gain control circuit e can be varied in the range of 0.7 times to 1.3 times, when the average level of the video signal changes significantly. It is possible to minimize flicker correction errors that occur in the image. Note that the predetermined level h,1 is determined through experiments and the like, and is not limited thereto.

As described above, according to this embodiment, the average level of the video signal changes greatly due to the movement of the subject, etc., and the dividing circuit 6
Even if flicker correction is performed in a case where the output signal differs from the intended correction signal, the range of correction is limited by the limiter 20, so there is no effect of the signal different from the intended correction signal. Good image quality can be obtained.

FIG. 6 is a block diagram of a flicker correction device for a solid-state television camera showing a third embodiment of the present invention. In the figure, 1 is a video signal input terminal, 2 is an average circuit, and 3 is an I, P
F, 6 is a division circuit, 6 is a gain control circuit, 7 is an output terminal,
2o is a limiter and the above is the same as in the second embodiment.

The difference from the second embodiment is that a prediction circuit 25 is provided.

The operation of the flicker correction device for a solid-state television camera according to the third embodiment configured as described above will be described below.

First mentioned above. In the second embodiment, the vertical set frequency rv of the television camera was explained as eoHz, but according to the NTSG standard, it is slightly different and f'v is 59.94)1z.

Further, the power supply frequency fp varies. Therefore, flicker
The components are not signals that repeat exactly every three fields, but have slightly different phases. That is, I(K),
I (K-33, IC: -61°I (K-9)...
... has a slightly different value.

If the deviation between I (K:l and I(K-s:) is α1, then k[K) - I(K-3) = α1 and below,
If the amount of shift is α2, then I(K-3]-I(K-6) = a2. Here, since the short-term phase shift is small, α1 = α2 The output signal 325 of the prediction circuit 25 is Calculate as follows (blank below) S26(K:]=S11 (K-2:]+(S11 C
K-2)-811(K-5:]) =S1o(K-3)+(S1o(K-3:]-81o[K-e]) =I(K-3]5OCK-31+(Eng( K-3) So (K-3) -I (K-e :) So
(:K-e]) Here, from SO(K-3) =SO(K-6], 5
26(K]=I(K-3)So(K-3)+5O(K-
3) (I (K-3) -4(K-6)) =SO(K-3](I(:ni-3)) α2) α1-α2, 525(K) = SO(K- 3](I (K-3)+α1
)=SO(K-311(K).Hereinafter, if flicker correction is performed as shown in the first and second embodiments, the flicker component can be removed with high accuracy.

As described above, according to this embodiment, by providing the prediction circuit 25, the vertical scanning frequency r p of the television camera
:59.94 Hz and flicker can be corrected with high accuracy even when the power supply frequency of the camera fluctuates.

The fourth embodiment uses the LPFa of the third embodiment and the prediction circuit 2.
This is a variation of the function of 5. This example will be explained below.

As mentioned above, when the phases of the flicker components are slightly different, if the amount of deviation between I (K) and I (K-s) is β1, I (K) -4 (K-6): β1 and below. To,
If the amount of shift is β2, then I(K-e]-I(K-12) = β2.Here, since the short-term phase shift is small, β1=β2 Here, e (K-s ), G(K-12) are defined as follows.

G(K-e)=(S11(K-2)+S11 (K-5
)+s11 (K-8])/3 Transforming the above equation, e(K-6:)=(810(K-3)+310(K-6
3+s 1o (K-91) )/3 :(I (K-3)So (K-3)+I(K-6)
o (K-s)+I (K-9)SO(K-9:
))/3 When the movement of the subject is small, SO(K-3):5o(K-6)SO(K-9)==:so(K-e). Therefore, G(K-6)=(I (K-3)-+4 (K-e)+
4(K-9] )So CK-6)/3 Here, since the phase shift of the flicker component is almost equal around the three fields of r(K-e), (I(K-3:
)-I (K-e:]=(I (K-es)-ICK-
1) Therefore, I CK-3)+I (K-9”1=2I (K-6)
Therefore, G (K -6)=Eng [:K -6':l So [:
K −6: ]. Similarly, G(K-12)=(S11(K-8)+311(K-
11)-)-811(K-14) )/3=I (K-
12] So (K-12).

The output signal 825 of the prediction circuit 26 is obtained as follows: 525(K)=G(K-e)+(G(K-e:)-G(
K-12)) =I(K-6:!5o(K-6)+(I(K-6)So
(K-6) -1(K-121SO(K-12)) Here, from 5o(K-81=SO(K-12), 82
5(K″l=technical(K-6″130(K-6:)+5O(
K-e] (I (K-e]-I (x-12
]) =SO(K-e](I(K-eel+β2) where β
Since 1=β2, 525(K)=SO(K-e]CI[K-e]+β1)
=SO(K-6)(1[K]).

The output S 12 (K) of the LPF3 is determined as follows.

512(K)=(S11(K-4:)+S11(K-
s)+811(K-e, :l)/3 =(I(K-s)So(K-5:)+I(K-e″
180(K-6:l+I(K-7180(K-7))
/3 Here, since there are few changes in adjacent fields, S
O(K-5)=SO[K-6] SO[:ni-7]χ5OCK-6]. Also, since the flicker component repeats every 3 fields and the average value of the signal component is 1, I(K-5
)+I(K-6)+I(K-7)=3. Therefore, Sl 2 (K :]=sO(K −e )(I (K
−ts )−+4(K −a )+I (K −7)
)/3, ==SO(K-6) The division circuit 5 performs the following calculation. If the output of the division circuit 5 is 814 [K], then Sl 4 (K:)=512 (K: 11513
(K]=SO(K-e)/(1(K-e:l+β1)S
o(K-e) = 1/(I (K-e:l+β1)=1/I(K).

Hereinafter, the flicker component can be similarly removed by controlling the gain with the gain control circuit 6 as shown in the third embodiment.

In this method, in order to obtain the output signal of the prediction circuit 25, 5o
Since six signals from (K-3) to 30[K-15] are used, even if noise is added to the video signal, it is less affected by the noise, so that highly accurate flicker correction can be performed.

FIG. 7 is a block diagram of a flicker correction circuit for a solid-state television camera showing a fifth embodiment of the present invention. In the same figure, 1 is a video signal input terminal, 2 is an average circuit, and 3 is an LPF.
, 4 is a delay circuit, 5 is a division circuit, 6 is a gain control circuit, 7
is an output terminal, and 20 is a limiter.The rest is the same as the second embodiment.The difference from the second embodiment is that a BPF 30, a level detection circuit 31, and a switching circuit 32 are provided.

The operation of the flicker correction device for a solid-state camera according to the fourth embodiment configured as described above will be described below.

A flickering video signal Sho input from the video input terminal 1 passes through the averaging circuit 2 and becomes a signal 311. Signals 510 and 511 are shown in FIG. The signal S11 is input to the I, PF 3 and delay circuit 4, and undergoes the processing shown in the first embodiment, and the division circuit 6 outputs a signal from which flicker components are removed.

On the other hand, the signal S11 is input to the BPF 30.

For example, the BPF has a characteristic of passing 20)h as shown in FIG. 9, and extracts the flicker component of the signal S11. The output signal of the BPF 3o is shown at 533 in FIG. The level detection circuit 31 detects the output signal of the BPF 30 and detects a level corresponding to the amplitude of the signal 533. The output signal of the level detection circuit 31 is shown at 334 in FIG.

Compared to the level of the signal S34 when a flicker-free video signal is input to the input terminal 1, the level of the signal S34 when a flickering video signal is input to the input terminal 1 becomes very large. Therefore, it is possible to determine whether or not the video signal has flicker based on the level of the output signal 8340 of the level detection circuit 31.

The switching circuit 32 converts the output signal S14 from the division circuit 5 and the predetermined value coN'r into the output signal S of the level detection circuit 31.
It is switched according to the size of the 34 levels. If the level of the signal S34 exceeds the predetermined value X, it is determined that the video signal has flicker, and the switching circuit 32 outputs the output signal 814 of the division circuit 6. On the other hand, if the level of the signal S34 is less than or equal to the predetermined value
Flicker correction is not performed by outputting ONT.

The predetermined value X is determined as necessary.

As described above, according to this embodiment, the BPF 30 extracts the flicker component, the level detection circuit 31 detects the flicker level, and the switching circuit 32 switches whether or not to perform flicker correction. , it is possible to automatically perform flicker correction only on video signals with flicker.

In the above embodiments, fp is 60H7 and rma is θOHz or 59.94Hz, but rp is 60Hz +
When fv is 60H7, the LPF shown in the first embodiment
Similar effects can be obtained by changing the delay circuit 3 and the delay circuit 4 as described below.

For example, when fp is 60)1z and fv is 5oHz, the video signal with flicker is repeated at a period of 5 fields.

Therefore, when K″ItIt field number, 1 (K)
= I (K-53 relationship holds true.

The output s12(K) of LPF3 is S-12(K:):(811(K-2)+511(K
-3)+811(K-a)+811(K-s)+811
[K -61)15 , =B[x-31;o(x-3)-+4(K-4]30
(K-4]+I (K-s:]5o(K,-6]-+
4 (x-e:)CK-7])15 Here, since there are few changes in the adjacent fields, 5o
(K-3:l230(K-53 SO(K-4) = SO(K-cs )5O(K
-6:)Tagu [K-6) So(K-71χ5o(K-5:1) Also, since the flicker component repeats every 6 fields and the average value of the signal component is 1, I (K- 3)+I
(K-4]+X (K-s)+r [:ni-e]
+I (K-7:l]=5 Therefore, s 12 (K:l is S12[K)===SO(K-s)(I[K-3)+1
(K-4,]+I (K-5]+I (K-6) +
(K-7))/6 = SO(K-s).

The output Sf3 of the delay circuit 4 is 813 [K:] = 811 (K-6) = I (K-5) So (K-5) Here, from the periodicity of flicker, I cx) = I (K-
5]o Therefore, = 工(:ni:330 (K-es).

The division circuit 6 performs the following calculations. If the output of the division circuit 5 is 514 (K), then 314 (K) = S12 (K) / 813 (K) = 5 (K -
s)/I(KISO(K-5) = 1/ICK).

Hereinafter, by controlling the gain with the gain control circuit 6 as shown in the first embodiment, it is possible to similarly remove the two-power component.

Note that the delay circuit 4 of the sixth embodiment can also be replaced with a prediction circuit 26 shown in FIG. Furthermore, the switching circuit 32 outputs a signal obtained by dividing the output 7 of the LPF 3 and the output of the delay circuit 4 (hereinafter referred to as M), and a signal obtained by dividing the output of the LPF 3 and the output of the prediction circuit 25 shown in FIG. Below B
) and a predetermined value C0NT are input, and if there is flicker in the video signal, there is no movement in the subject, and the average level of the video signal does not change significantly, select the signal person and output it. However, if there is flicker in the video signal and the average level of the video signal changes greatly due to the movement of the subject, signal B is selected and output, and if there is no flicker in the video signal, the signal B is selected and output. The value C0NT may be output. Accordingly, accurate flicker correction can be performed using the prediction circuit 26 only when there is flicker in the video signal and the average level of the video signal does not change significantly.

Also, 1st. Second. 4th. The delay circuit 4 of the fifth embodiment is
A similar effect can be obtained even if it is provided after the division circuit 6.

Furthermore, in all the embodiments described above, the output of the averaging circuit 2 is output at the vertical scanning frequency. This is Fuku 0
This is a sufficiently slow speed compared to the processing speed of a computer. Therefore, it is possible to input the output of the averaging circuit 2 into a microcomputer, perform calculations to obtain a flicker correction signal, and output the calculation results to the gain control circuit.

The advantage of using a micro combinator is that the circuit configuration is simple and the processing contents can be easily changed.

As described in detail, according to the present invention, the same effects as the conventional example can be achieved with a simple configuration, and even more accurate correction and
Automatically detects flicker and adjusts flicker as necessary
Correction can also be easily realized, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a flicker correction device for a solid-state television camera according to a first embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of the same embodiment, and FIG. 3 is a diagram of a solid-state television camera according to a second embodiment. A block diagram of a camera flicker correction device, FIG. 4 is a signal waveform diagram of each part of the same embodiment, FIG. 6 is an input/output characteristic diagram of the limiter of the same embodiment, and FIG. A block diagram of a flicker correction device for a solid-state television camera according to a fourth embodiment,
FIG. 7 is a block diagram of a flicker correction device for a solid-state television camera according to the fifth embodiment, FIG. 8 is a signal waveform diagram of each part of the same embodiment, FIG. 9 is a characteristic diagram of BPF of the same embodiment, and FIG. The figure is a block diagram of a conventional flicker correction device for a solid-state television camera, and Figure 11 is a signal waveform diagram of each part of the same embodiment.
FIG. 2 is a characteristic diagram of the LPF of the same example. 2... Average circuit, 3... LPF, 4...
... Delay circuit, 6... Division circuit, 6...
...Gain control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure field "false (K) Figure 4 Field *1 Figure 5 Input curre A" area - q method Figure 8 δ3 < ot Figure 9 area - Figure 12

Claims (3)

[Claims] (1) An averaging circuit that detects the average level of a video signal, an LPF that receives the output of the average circuit, a division circuit that receives the output of the LPF and the output of the average circuit, and the output of the division circuit. A flicker correction device for a solid-state television camera, comprising: a gain control circuit that controls the gain of the circuit according to the gain of the circuit. (2) The flicker correction device for a solid-state television camera according to claim 1, wherein the gain control circuit limits the upper and lower limits of the gain of the circuit to predetermined values. (3) When the value determined by the power supply frequency and the vertical synchronization frequency of the camera is N, the division circuit calculates the T-Nth to T-kNth field for the T-th (T is arbitrary) field to be corrected. A prediction circuit is provided for processing L output signals (L≦k) among the output signals of the averaging circuit corresponding to every N fields consecutively up to (k is a natural number). A flicker correction device for a solid-state television camera according to item 1 or 2.