JPH01251148A - Interface protecting circuit for computer peripheral equipment - Google Patents

Abstract

PURPOSE:To protect semiconductor elements against an OFF state of one of two power sources in a safe and satisfactory way by connecting signals showing the application states of the power sources of a computer main body and a peripheral equipment to each other. CONSTITUTION:Electrical interface connection is secured between a computer main body 1 and a peripheral equipment 2 via a DOWN signal 3, an UP signal 4, a peripheral equipment power source ON signal 5 and a main body power source ON signal 6 respectively. The main body 1 contains a signal driver 7a, a signal receiver 8a, an output control part 10a and a power source ON detecting part 9a. While the equipment 2 contains a signal driver 7b, a signal receiver 8b, a power source ON detecting part 9b and an output control part 10b respectively. Then a peripheral equipment power source ON state signal 5 and a main body power supply ON state signal 6 produced by both circuits 9a and 9b and both circuits 10a and 10b function to inhibit the mutual application of voltage between both drivers 7a and 7b as well as both receivers 8a and 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrical interface circuit between a computer main body and a peripheral device V, and in particular, protection of the interface when the power supply of either the main body or the peripheral device is 0N10FF. Regarding circuits.

[Prior Art] Conventionally, this type of protection circuit uses a semiconductor element with a relatively high withstand voltage, such as a bipolar transistor integrated circuit, in the driver/receiver circuit of the interface circuit, and no protection measures are taken on the circuit. , the most common method was to depend on the performance of the semiconductor element.

[Problems to be Solved] The above-described conventional method that depends on the performance of semiconductor elements has the drawback of being limited in the number of elements that can be used.

In other words, CMO3 in line with the trend of power saving and speeding up in recent years.
In the transition to type O3 circuit, the power supply O specific to 0MO8
Since there is a latch-up phenomenon that causes element damage due to voltage application in the FF state, some kind of solution is needed.

In addition, in the conventional method, if the power OFF time of one of the devices is short, even if the element is not damaged, if the power is turned off for a long time, the element deteriorates.
There was also some S damage that led to damage.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned conventional problems and to prevent deterioration or breakage of the cables without depending on the performance of the semiconductor element and even when the power is turned off for a long time. An object of the present invention is to provide an interface protection circuit for a computer peripheral device that does not occur.

[Means for Solving Problems] The protection circuit of the present invention connects signals indicating the power-on state of the main unit and peripheral devices to each other, and outputs voltage only when the power of the other device is on. The computer main body and the peripheral device are both provided with a driver circuit that generates the signal and a receiver circuit that applies a voltage to the input side only when the power of the other device is in the ON state.

Here, the signal indicating the power ON state can be either a non-voltage contact such as a mechanical relay or a transistor oven collector, or a voltage contact capable of driving a mating connection part.

Example of Practical Rejection] Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block circuit diagram of an embodiment of the present invention (
The protection conditions are shown in (a) and (b) and (c) of the same figure, respectively.

The computer main body 1 receives each signal of a downstream signal 3, an upstream signal 4, a peripheral device power ON signal 5, and a main body power ON signal 6.
It is designed to be electrically interfaced with the peripheral device 2.

A signal driver 7a is provided on the computer main body 1 side.
, a signal receiver 8a, an output control section 10a, and a power ON detection section 9a are respectively provided, and the peripheral device 2 is provided with a signal driver 8b, a signal receiver 7b, a power ON detection section 9b, and an output control section tab, respectively. It is provided.

Further, in order to protect the semiconductor elements of the signal driver EPIs 7a and 7b and the signal receiver circuits 8a and 8b connected to the downlink signal 3 and uplink signal 4, the power ON detection circuit 9a of the other device is connected.

Power ON state signal 5 or signal 6 generated from 9b
The output control circuits 10a and 10b control the signal driver circuits 7a and 7b and the signal receiver circuits FI@8a and 8b.
It is prohibited to apply voltage to the other device.

That is, as shown in FIGS. 1(a) and (b), the power supply O
81 only when N signal 5 is logic 1 (ON state)
Since voltage output to the hand side is permitted, voltage application when the power is off is reliably prevented, latch-up phenomenon can be prevented, and the semiconductor element can be reliably protected.

FIG. 2 shows a specific circuit of the embodiment for one device; in reality, the same circuit is also provided for the other device. Here, the figure (a) shows the case where the signal of the power ON state is a non-voltage contact, and the figure (b) shows the case where the signal of the power ON state is a voltage contact.

In FIG. 2(a), resistors R1, R2 and transistor Q1 are connected to the power supply ON/OFF detection section i@ of the computer main body 1.
9a, the resistor HR3 on the peripheral device 2 side, the transformer transistor inverter ICI, the output control circuit 10b, and the receiver circuit pull-up resistors R11 to R1! and receiver CMO3IC2, receiver circuit f18b, driver circuit pull-up resistor R21~R2m and driver CM
Each O3IC3 constitutes a driver circuit 7b.

In addition, in the same figure (b), the resistors R31 to R33 and the transistor Q3 connect the power ON detection circuit 9a of the computer main body 1, and the photocoupler Pct and inverter IC4 on the peripheral bag v, 2 side connect the output control circuit 10b to the receiver. Pull-up resistors R41-R41 and receiver CMO3I
C5 constitutes a receiver circuit 8b, and driver pull-up resistors R51 to R5rr and driver CMO3IC6 constitute a driver circuit 7b.

In either case of Fig. 2 (a) or (b), if the power of the other device is OFF, resistors R11 to R11 and R2
1 to R2m or R41 to R41 and R51 to R5m
Application of voltage to is prohibited by transistor Q2 or photocoupler Pct. Also, inverter IC, IC
I or IC4 prohibits voltage output of IC2 and IC3 or IC5 and IC6 to the partner device side.

As mentioned above, when the connected device is powered off, driver circuit #I7a, 7b and receiver circuit #I7a, 8b
No power is applied to the driver, ff87
a, 7b and receiver circuit 8a.

Even if a CMOS element is used for 8b, element damage due to latch-up phenomenon does not occur and the element is well protected.

Note that the present invention is not limited to the above embodiments,
Various modifications can be made within the scope of the invention.

[Effects of the Invention] As explained above, the present invention provides an electrical interface between the main body of the computer and the peripheral devices by interconnecting signals indicating the power-on states of the main body and the peripheral devices. C in the circuit
Even if an element such as MO3 that is prone to damage such as latch-up is used, the semiconductor element can be well and safely protected by turning off one side of the power supply.

[Brief explanation of the drawing]

FIG. 1 is for explaining one embodiment of the present invention, and FIG. 1(a) is a block circuit diagram, and FIG. 1(b) is a block circuit diagram. (c) is a characteristic diagram showing the protection conditions, Figure 2 shows the specific circuit of the embodiment for one device, and (a) of the same figure shows the case where the power ON state signal is a non-voltage contact. , FIG. 3(b) is a circuit diagram showing a preferred embodiment in which the power supply ON state signal is a voltage contact. 1; Computer body, 2: Peripheral equipment, 3; Down signal,
4: Upstream signal, 5: Peripheral device power ON signal, 6: Main unit power ON signal, 7: Signal driver circuit, 8: Signal receiver circuit, 9: Power ON detection circuit, 10: Output control circuit, Q1 to Q3: Transistor , PCl, photocoupler, R1-R3: resistor, R11~
RII! Receiver circuit pull-up resistor, R21~R2m; Driver circuit pull-up resistor, ICI, inverter IC1 IC2; Receiver CMO3IC1 IC3; Driver CMOSIC1 R41~F, 41. Resistor puller, knob resistor, R5
1 to R5m; Driver pull-up resistor, IC4, inverter IC1 IC5, receiver CMO3IC1 IC6, driver CMOSIC.

Claims (1)

[Scope of Claims] In an electrical interface circuit between a computer main body and a peripheral device, signals indicating the power-on state of the main body and peripheral device are mutually connected, and the power of the other device is in an ON state. The driver circuit generates voltage output only when the power of the other device is OFF.
An interface protection circuit for a computer peripheral device, characterized in that a receiver circuit that applies a voltage to the input side only when in the N state is provided in both the computer main body and the peripheral device.