JPS61264916A - Surge absorbing circuit - Google Patents

Surge absorbing circuit

Info

Publication number
JPS61264916A
JPS61264916A JP60107320A JP10732085A JPS61264916A JP S61264916 A JPS61264916 A JP S61264916A JP 60107320 A JP60107320 A JP 60107320A JP 10732085 A JP10732085 A JP 10732085A JP S61264916 A JPS61264916 A JP S61264916A
Authority
JP
Japan
Prior art keywords
surge
logic circuit
resistor
capacitor
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60107320A
Other languages
Japanese (ja)
Inventor
Hidetoshi Gotanda
五反田 英利
Shinkichi Asaka
信吉 浅加
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60107320A priority Critical patent/JPS61264916A/en
Publication of JPS61264916A publication Critical patent/JPS61264916A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection

Abstract

PURPOSE:To protect a logic circuit by providing a capacitor between a signal line and an earth of the logic circuit and connecting the 2nd diode to the earth so as to allow the circuit to show a low impedance to a negative surge voltage. CONSTITUTION:A resistor 24 is arranged to discharge an electric charge of a capacitor 23 and a resistor 28 is arranged to limit a current flowing to a contact 4 by the discharge of the capacitor 23 when the contact 4 is closed. When a positive surge is fed to an input terminal 6 of a device 27, since the diode 22 exists in reverse polarity to the positive surge, the surge is absorbed by the capacitor 23 and the surge voltage is divided by the resistor 25 so as to protect the logic circuit 8. When a negative surge is fed to the input terminal 6, the surge path is short-circuited by the diode 21 and the surge is absorbed and blocked by the capacitor 23 and the resistor 25 to protect the logic circuit 8.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は論理回路等をサージから保護するためのサージ
吸収回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a surge absorption circuit for protecting logic circuits and the like from surges.

従来の技術 近年、情報化の波はさまざまな分野に進出し、とシわけ
各種センサーを用いた管理システムは既に普及しはじめ
ている。その中で谷センサーからの信号を制御装置の論
理回路まで信号を伝送する信号線が長くサージが印加す
る可能性の高い場合、論理回路及びこれを保護するフォ
トカプラの破壊を防ぐため第2図に示すように、サージ
吸収素子としてZN)tとダイオードがよく用いられて
いる。
Conventional Technology In recent years, the wave of informatization has expanded into various fields, and management systems using various sensors have already begun to spread. If the signal line that transmits the signal from the valley sensor to the logic circuit of the control device is long and there is a high possibility that a surge will be applied, the logic circuit and the photo coupler that protects it should be protected from damage as shown in Figure 2. As shown in the figure, ZN)t and diodes are often used as surge absorbing elements.

以下、第2図を基にその従来の一例を説明する。An example of the conventional method will be described below with reference to FIG.

第2図において熱やガス等のセンサー1が感シ応動した
ときセンサ側機器2は他の機器3へその情報を出力する
ため接点4を閉じる。この接点4の閉状態が出力信号と
して伝送線5を介して機器3の入力端子6,6′に渡さ
れる。すなわち、接点4が閉じている状態では機器3の
電源E1からフォトカプラ7の発光ダイオードに電流が
流れ論理回路入力端子12がLOVVレベルとなり、接
点4が開いている状態ではフォトカプラ7の発光ダイオ
ードに電流が流れず論理回路80入力端子12はf(f
ghレベルとなってセンサー1の状態によって勧り接点
の状態が論理回路゛8で把握することができる。
In FIG. 2, when the sensor 1 for heat, gas, etc. responds, the sensor side device 2 closes the contact 4 in order to output the information to other devices 3. The closed state of the contact 4 is passed as an output signal to the input terminals 6, 6' of the device 3 via the transmission line 5. That is, when the contact 4 is closed, a current flows from the power supply E1 of the device 3 to the light emitting diode of the photocoupler 7, and the logic circuit input terminal 12 becomes the LOVV level, and when the contact 4 is open, the light emitting diode of the photocoupler 7 flows. Since no current flows through the input terminal 12 of the logic circuit 80, f(f
The state of the contact point can be grasped by the logic circuit 8 based on the state of the sensor 1 at the gh level.

このような使用状況の中で、伝送線6が長くす−ジが入
力端子6,6′に印加された時、ZNR9、抵抗10で
サージを吸収、阻止し、ダイオード11でフォトカプラ
7の発光ダイオードの逆方向電圧に対し保護じている。
Under such usage conditions, when the transmission line 6 is long and a surge is applied to the input terminals 6 and 6', the ZNR 9 and the resistor 10 absorb and block the surge, and the diode 11 prevents the photocoupler 7 from emitting light. Protects against diode reverse voltage.

さらに、フォトカプラ7にて論理回路8を保護している
Furthermore, the logic circuit 8 is protected by a photocoupler 7.

発明が解決しようとする問題点 しかしながら上記した@2図に示す従来の構成では、論
理回路駆動用電源E2とフォトカプラ7の発光ダイオー
ドの駆動電源L1の2つの電源が必要となる欠点を有し
ている。かつ、論理回路駆動用電源E2は通常6ボルト
であるのに対し、発光ダイオード駆動用電源E1は、サ
ージ電圧阻止用の抵抗1oによって5ボルト以上の電源
が必要となるのが一般的である。
Problems to be Solved by the Invention However, the conventional configuration shown in FIG. ing. In addition, while the power supply E2 for driving the logic circuit is normally 6 volts, the power supply E1 for driving the light emitting diode generally requires a power supply of 5 volts or more due to the surge voltage blocking resistor 1o.

tた、入力端子6,6’、ZNRg、抵抗1o、ダイオ
ード11、フォトカプラ7は、上述したサージからの保
護回路を構成しているが、接点4の数が多くなれば、こ
の保護回路の数も多くなり、保護回路の数に比例した電
源容量が電源E1に要求される。従って、保護回路数が
多くなった場合、電源E1が機器3に与える形状的、価
格的影響が俟めて大きくなる欠点を有している。
In addition, the input terminals 6, 6', ZNRg, resistor 1o, diode 11, and photocoupler 7 constitute the above-mentioned surge protection circuit, but as the number of contacts 4 increases, this protection circuit becomes The number of protection circuits also increases, and the power supply E1 is required to have a power supply capacity proportional to the number of protection circuits. Therefore, when the number of protection circuits increases, the power source E1 has a disadvantage in that the influence on the device 3 in terms of shape and cost increases.

本発明は、入力信号速度が極めて遅く、かつ、印加され
るサージ電圧が低く、印加される頻度が少ない機器の入
力信号回路を保護するためのサージ吸収回路で、上記従
来例での問題点を解決するものである。
The present invention is a surge absorption circuit for protecting the input signal circuit of equipment in which the input signal speed is extremely slow and the applied surge voltage is low and is applied infrequently.The present invention solves the problems of the conventional example. It is something to be solved.

問題点を解決するための手段 この目的を達成するため、本発明のサージ吸収回路は、
フォトカプラ、ZNRを用いずにダイオードとコンデン
サと抵抗で構成し論理回路を保護するものである。
Means for Solving the Problems To achieve this objective, the surge absorption circuit of the present invention comprises:
It protects the logic circuit by consisting of a diode, capacitor, and resistor without using a photocoupler or ZNR.

作  用 本発明は上記した構成によって電源回路を論理回路駆動
用のもの1つとし電源回路を小型化し、かつ、論理回路
を保護することとなる。
Operation The present invention uses the above-described configuration as one power supply circuit for driving the logic circuit, thereby reducing the size of the power supply circuit and protecting the logic circuit.

実施例 以下本発明の実施例について、図面を参照しながら説明
する。第1図は本発明の一実施例におけるサージ吸収回
路を示すものである0 第1図において、センサー1、接点4、機器2、伝送線
6、入力端子6,6′、論理回路8、論理回路の入力端
子12は第2図に示す従来例と同一である。
EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 shows a surge absorption circuit according to an embodiment of the present invention. In FIG. The input terminal 12 of the circuit is the same as the conventional example shown in FIG.

接点4が閉じているときは抵抗26と抵抗26の接点a
はLOWレベルとなり論理回路8入力端子12はLOW
レベルとなり、また、接点4が開いておれば、接点aが
Highレベルになって論理回路80入力端子12がH
ighレベルになるように抵抗24,25.26を定め
る。抵抗24はコンデンサ23の電荷を放電させるため
に配置されるものである。抵抗28は、接点4が閉じた
とき、コンデンサ23の放電によって接点4に流れる電
流を制限するために配置されるものである。
When contact 4 is closed, resistor 26 and contact a of resistor 26
becomes LOW level and the logic circuit 8 input terminal 12 becomes LOW.
If contact 4 is open, contact a becomes high level and input terminal 12 of logic circuit 80 goes high.
Resistors 24, 25, and 26 are set so that the level is high. The resistor 24 is arranged to discharge the charge of the capacitor 23. Resistor 28 is arranged to limit the current flowing through contact 4 due to discharge of capacitor 23 when contact 4 is closed.

機器−27の入力端子6に正極性のサージが印加された
場合、この正極性サージに対し、逆方向でダイオード2
2があるため、また、コンデンサ23で吸収し、かつ抵
抗25で分圧され論理回路8を保護することができる。
When a positive surge is applied to the input terminal 6 of the device 27, the diode 2 is connected in the opposite direction to this positive surge.
2, the logic circuit 8 can be protected by being absorbed by the capacitor 23 and divided by the resistor 25.

入力端子6に負極性のサージが印加された場合、ダイオ
ード21によってアース側に短絡され、かつ、コンデン
サ23、抵抗25によって吸収・阻止され論理回路8を
保護することができる。
When a negative polarity surge is applied to the input terminal 6, it is short-circuited to the ground side by the diode 21, and is absorbed and blocked by the capacitor 23 and the resistor 25, so that the logic circuit 8 can be protected.

このように構成することにより、電源は論理回路8の駆
動用電源と同一の電源を用いることができるため、従来
例の欠点である電源回路を複数用意することが不要とな
り、かつ、論理回路8でLoWレベル、Hi g hレ
ベルを検出するための電源E2から抵抗26、ダイオー
ド22、抵抗28、は 接点4を流れる電流1omA程度でよく保護回路数が多
い場合でも電源の容量が機器27に与える形状的、価格
的影響を極めて小さくなる。
With this configuration, the same power source as the power source for driving the logic circuit 8 can be used, which eliminates the need to prepare multiple power supply circuits, which is a drawback of the conventional example, and The resistor 26, diode 22, resistor 28 from the power supply E2 for detecting the LoW level and High level at The impact on shape and price is extremely small.

発明の効果 以上のように本発明によれば、ZhRを取り除き、ダイ
オード、抵抗、コンデンサを用いることにより、低電圧
電源回路が使用でき、これにより電源回路部の機器の価
格、形状に及ぼす影響を大幅に軽減し、また電源容量の
変化が従来のものと比べ、非常に小さくなるため、保護
すべき回路数の多少に拘わらず同一の電源回路の共用化
が答易となり、かつ機器の形状の共用化も容易となる。
Effects of the Invention As described above, according to the present invention, by removing ZhR and using diodes, resistors, and capacitors, a low-voltage power supply circuit can be used, which reduces the impact on the price and shape of equipment in the power supply circuit section. Since the power supply capacity is significantly reduced and the change in power supply capacity is much smaller compared to conventional ones, it is easy to share the same power supply circuit regardless of the number of circuits to be protected, and the shape of the equipment can be reduced. Sharing is also facilitated.

【図面の簡単な説明】[Brief explanation of the drawing]

g1図は発明の一実施例におけるサージ吸収回路の回路
図、第2図は従来のサージ吸収回路の回路図である。 1・・・・・・センサ、2・・・・・・センサ側機器、
4・・・・・接点、6・・・・・・伝送線、6,6’、
12・・・・・・入力端子、8・・・・・・論理回路、
21.22・・・・・・ダイオード、23・・・・・・
コンデンサ、24〜26.28・・・・・・抵抗、27
・・・・・・機器。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名ブ・
・・センサ 2・・・センサタ1本E区 21、22・・・ダイ4−ド 23・・・コンデ゛ンす 24、.25.26.2,9.、、 Jシ4九27、・
・機・、器
Figure g1 is a circuit diagram of a surge absorption circuit according to an embodiment of the invention, and Figure 2 is a circuit diagram of a conventional surge absorption circuit. 1...Sensor, 2...Sensor side equipment,
4...Contact, 6...Transmission line, 6,6',
12...Input terminal, 8...Logic circuit,
21.22...Diode, 23...
Capacitor, 24-26.28... Resistor, 27
······device. Name of agent: Patent attorney Toshio Nakao and one other person
...Sensor 2...1 sensor E section 21, 22...Die 4-de 23...Conductor 24, . 25.26.2,9. ,,Jshi4927,・
·device

Claims (1)

【特許請求の範囲】[Claims] 誘導などによるサージから論理回路を保護するために正
極性のサージ電圧に対しては高インピーダンスになる様
に第1のダイオードを配置し、さらに上記サージ電圧を
吸収するようコンデンサを上記論理回路の信号線とアー
スとの間に設け、負極性のサージ電圧に対しては低イン
ピーダンスになる様にアース側に接続された第2のダイ
オードを有するサージ吸収回路。
In order to protect the logic circuit from surges caused by induction, etc., a first diode is placed so that it has a high impedance against positive surge voltage, and a capacitor is connected to the signal of the logic circuit to absorb the surge voltage. A surge absorption circuit that is provided between the line and the ground and has a second diode connected to the ground side so as to have a low impedance against surge voltages of negative polarity.
JP60107320A 1985-05-20 1985-05-20 Surge absorbing circuit Pending JPS61264916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60107320A JPS61264916A (en) 1985-05-20 1985-05-20 Surge absorbing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60107320A JPS61264916A (en) 1985-05-20 1985-05-20 Surge absorbing circuit

Publications (1)

Publication Number Publication Date
JPS61264916A true JPS61264916A (en) 1986-11-22

Family

ID=14456074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60107320A Pending JPS61264916A (en) 1985-05-20 1985-05-20 Surge absorbing circuit

Country Status (1)

Country Link
JP (1) JPS61264916A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202241A (en) * 1989-01-31 1990-08-10 Matsushita Electric Works Ltd Apparatus having noise elimination circuit
KR100383997B1 (en) * 2000-12-28 2003-05-14 현대자동차주식회사 Wiper driving circuit in a vehicle

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202241A (en) * 1989-01-31 1990-08-10 Matsushita Electric Works Ltd Apparatus having noise elimination circuit
JP2607664B2 (en) * 1989-01-31 1997-05-07 松下電工株式会社 Equipment with noise elimination circuit
KR100383997B1 (en) * 2000-12-28 2003-05-14 현대자동차주식회사 Wiper driving circuit in a vehicle

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