JPH01248857A - Automatic answering telephone set - Google Patents

Abstract

PURPOSE:To execute the sound recording of the response message to a memory and the musical interval of a double speed voice with a simple and inexpensive circuit constitution by executing the data processing of the digital data from the memory at the time of converting the musical interval of the double speed voice and outputting the data at the time of reproducing a response message at it does. CONSTITUTION:An analog signal column is converted to the digital data of one bit, simultaneously, the analog signal column is supplied to a level deciding circuit 2 and the way of silence voice part data or sound voice part data are detected. Writing and reading are executed at a period T, reading has two systems of reading 1 and reading 2 and is executed at a period 2T. Thus, out of a dynamic RAM 11 of 256k bits, the voice processing area of 8k bits is used and the musical interval conversion of the double speed voice is executed. Thus, the dynamic RAM 11 can be divided into a voice processing area for the musical interval conversion of the double speed voice and an area 2 for reproducing the sound signal without the silence part data and can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an answering machine having a tape recorder and recording a message from a caller on the tape recorder.

2. Description of the Related Art Conventionally, this type of answering machine plays back a tape recorder on which a business message is recorded at the same speed as when it was recorded. However, with such an answering machine, it takes time to listen to the message, especially when the owner uses remote control to listen to the message recorded on the tape recorder via the telephone line. At the same time, high call charges are required.

For this reason, some tape recorders try to play back the tape at high speed, but simply playing back at high speed increases the audio frequency and makes it difficult to open the tape. Therefore, in recent years, some devices have a pitch conversion function that reproduces the audio signal at high speed and returns the increased frequency to the original frequency.

Problems to be Solved by the Invention However, the above-mentioned answering machine has a response storage means such as a memory or a tape recorder for storing the called party's response message, and a response message for storing the caller's business message. Memorandum storage means such as a tape recorder,
Furthermore, each pitch conversion means is required independently, which increases the circuit scale of the entire device. Since 3JL is a large amount, the cost and
I had to go up.

In view of the above-mentioned problems, the present invention stores the called party's response message in a memory and tape-records the calling party's business message.
In an answering machine that records on a recorder, the analog-to-digital conversion operation for writing the response message into memory, which is necessary when recording and playing back the response message, the writing, reading, and control operations of the data into the memory, and the operation when playing back the response message. When performing a digital-to-analog conversion operation that converts digital data from memory into an analog signal string and a pitch conversion process for double-speed audio, an analog signal that converts the necessary double-speed audio into digital data is used.
Analog conversion during each operation: digital conversion operation, control operation for writing and reading the digital data into memory, and digital-to-analog conversion operation for converting the digital data after pitch conversion processing into an analog signal string. The digital conversion operation, memory control operation, and digital-to-analog conversion operation are performed in a common circuit, and the tape recorder on which the message was recorded is played back at double speed with a simple and inexpensive configuration, and the pitched voice is reproduced as normal. To provide an answering machine with a pitch conversion function that converts pitches into pitches.

Means for Solving the Problems In order to achieve the above object, the present invention provides an A/D conversion circuit that converts an analog signal string into digital data, and a first circuit that writes audio reproduced at double speed to convert pitch. a storage means, a second storage means for writing digital data obtained by converting a called person's response message using the A/D conversion circuit, and controls the first storage means and the second storage means, respectively. A storage means control circuit that controls writing and reading, a data processing means that processes data for pitch conversion of double-speed audio, and a D/A that converts digital data from the data processing means into an analog signal string. It is constructed from a conversion circuit.

Function: With this configuration, the double-speed voice before pitch conversion and the recorded response message are converted into digital data by a common A/D conversion circuit. The converted digital data is written to memory by a common storage means control circuit,
Or read from memory. The data processing means processes the digital data from the memory when converting the pitch of the double-speed audio, and outputs the data as is when reproducing the response message. The D/A conversion circuit converts digital data from the data processing means into an analog signal sequence.

In this way, it becomes possible to record the response message in the memory and convert the pitch of the double-speed voice with a simple and inexpensive circuit configuration.

Embodiment FIGS. 1 and 2 are schematic configuration diagrams of an embodiment of the present invention. 1 and 2, 1 is an A/D conversion circuit, and in this embodiment, ADM (Adapt-Live
By the Delta Modulation) method,
Assume that a manually generated analog signal string is converted into 1-bit digital data. Reference numeral 2 denotes a level determination circuit, which is constructed as shown in FIG. 3 in this embodiment. The input analog signal train passes through a coupling capacitor C1, and then is charged into a capacitor C2 by a resistor R1 and an internal resistance r of a diode D1. The charged charges are discharged through the resistor R2 in the silent section. In this way, the voltage of the capacitor 02 varies depending on the input audio level. This fluctuating voltage of capacitor 02 is compared with a certain threshold value, and if the voltage of capacitor C2 is greater than a certain threshold value, "H" is output. Here, the specific threshold value is the value of the variable resistor VR that is adjusted so that "H" is always output in the voiced part data of the analog signal train as shown in FIG. 3 is the output YK of the level determination circuit 2 which divides the source oscillation and inputs it;
A control signal 5TART from a control device (not shown) and W/
This is a timing generation circuit that generates various timing signals shown in FIG. 5 using R and BAI. here,
Control signals 5TART, W/R, and BAI control the entire system of this embodiment, and are as follows.

5TAR"I':"H" - Starts the system.

“L” - Puts the system in standby mode.

W/R: "H" - Instructs writing.

"L" - Instructs to read.

BAI: “H” - Instructs double-speed voice pitch conversion.

“L” - Instructs recording/playback.

Reference numeral 4 denotes a latch circuit A that takes in input 1-bit digital data with a signal Ll and outputs determined 1-bit digital data. Reference numeral 5 designates a launch circuit B which takes in input 1-bit digital data as a signal L2 and outputs determined 1-bit digital data. 6
captures the input 1-bit digital data with signals L31 and L32, and outputs the 1-bit digital data determined by L31 from output 01 and the 1-bit digital data determined by L32 from output 02, respectively. This is a latch circuit C. Reference numeral 7 denotes a selector that switches between two input data using a signal DS and outputs the same. 8 always performs a count up operation with the input count up clock CLK 1, and the address data aO=a1
This counter A is composed of 14 stage counters each outputting 3. A counter B 9 is constituted by an 18-stage counter that performs a count-up operation based on the input count-up clock CLK2 and outputs address data bO to b17, respectively. In this embodiment, starting from the initial value "2000H" where b13 is set, b.

When all signals .about.b17 reach "3FFFFH", which is "H", an end signal EO8 is output to the timing generation circuit 3. 10 is the input 5 types of address signals SEL 1
This is an address switching circuit that switches and outputs 5EL2, RC3, and 5ELWR. Figure 6 shows signal 5EL
This shows the relationship between 1.5EL2, RC3°5ELWR, and five types of addresses. Reference numeral 11 denotes a memory controlled by a signal from the timing generation circuit 3, and in this embodiment, 25
6, a dynamic RAM with a bit x 1 bit configuration is used.

The dynamic RAM 11 can read from 0 to 255 within 4ms.
RA S (Row-Addre
RAS-only refresh by specifying the falling timing of the ss-5trobe) signal.
A refresh method is used. 12 is a data processing circuit, and 13 is a D/A conversion circuit that converts input 1-bit digital data into an analog signal train using a double integrator.

Next, the operation of the above embodiment will be explained.

In the above embodiment, the analog signal string shown in FIG. 4, which is composed of silent part data, unvoiced sound part data, and sound part data, is converted into 1-bit digital data by the A/D conversion circuit 1 (ADM method). converted. At the same time, the analog signal train is supplied to the level determination circuit 2. The level determination circuit 2 detects the middle of the unvoiced sound part data (B) or the voiced sound part data (C) of the analog signal train as shown in FIG. 4, and outputs an output YK"H".

Here, the output signal of the timing generation circuit 3 is divided into four mode states as shown in FIG. Divided into.

As an operation common to the above four states, a refresh operation is performed in order to retain the memory.

In order for the 256-bit dynamic RAM II to perform a refresh operation, addresses 1 to 256 must be generated within 4 ms. Figure 5 (B), Figure 5 (C
), as shown in FIG. 5(D), the timing generation circuit 3 outputs the count up clock CLK1, and the counter A
Enter 8. The counter A8 performs a count-up operation four times in 60 μs at the rising edge (V) of the count-up clock CLKI. From equation (1), which will be described later, counter A8 stores the row address data of refresh addresses 0 to 255 in 3.84m5 as ao-a7.
Output each from. Row address data aO-
a7 is input to the address switching circuit 10. The address switching circuit 10 has three input signals SEL1, 5EL2 and RC3 as shown in FIG.
"L" (i), 5EL2="H" (k), RC3=
``L'(m), so the row address data aO of the refresh address from the input counter A8
~a7 is output to AO~A7 of dynamic RAMII, and 6L'' is output to A8.Dynamic RAMII
60 in synchronization with the fall (a) of the RAS signal from the timing generation circuit 3 for each refresh address data of O to 255 input from AO to A8.
Refresh operations are performed four times during μs.

60μs X256+ 4 #3.84m5 (
1) In Figure 5 (A), the count up clock CLK1 is raised once every 4 μs and the RAS signal is lowered, so from the following equation (2), 1.024 m5
It can be seen that a refresh operation is performed.

4μs X256=1.024m5 (2)
The operation of each of the four states shown in FIG. 7 will be explained.

(1) Mode 1 The output from the timing generation circuit 3 is as shown in FIG. 5(A). The respective address data during operation can be seen from FIG.

The A/D conversion circuit 1 converts input double speed audio into 1-bit digital data and outputs it. Output digital
Data ■ is input to input l of launch circuit A4. Launch circuit A receives digital data input from input I,
Signal L from timing generation circuit 3 input from input C
It is held at the rising edge of 1 (29) and output from output O.

The output data ■ is input to the input ■1 of the selector 7. In mode 1, the DSO value manually generated by human force C is always “L”.
” Therefore, the selector 7 selects the data ■ from the input ■1 and outputs it from the output O.The output data ■ is input to the input DIN of the dynamic RAM II.

Here, in the operation of mode 1, as shown in FIG. 8(a), writing and reading are performed at a cycle T, but there are two systems for reading, read 1 and read 2, each with a cycle 2.
I'm going with T.

At the time of writing, the address switching circuit lO receives the signal input from the timing generation circuit 3 at 5E as shown in FIG.
L = "L", 5EL2 = "H", RC3 = "L",
Since S E LWR=“L”, aO~ of counter A8
The data of a8 is outputted to AO to A8 of the dynamic RAM 11 as row address data of the audio processing area. The dynamic RAM 1l holds the row address data of the audio processing area inputted from the inputs AO to A8 at the falling edge (1) of the RAS signal.

Similarly, as shown in FIG. 6, the address switching circuit 10 receives a signal input from the timing generation circuit 3 when 5EL="L".
, 5EL2="H", RC3="H", 5ELWR="
Since it is L', data from a9 to a12 of counter A8 is output to AO to A3 of the dynamic RAM 11 as column address data of the audio processing area, and data from A4 to A8 is '
Outputs “L”.

Dynamic RAM II holds the column address data of the audio processing area input from inputs AO to 88 at the falling edge (5) of the CAS signal.

At the falling edge (5) of the CAS signal, WE
Since the signal is “L” (9), the dynamic RAMI
I is D to the memory cell in the audio processing area specified by row address data and column address data.
Write the data ■ input from IN.

During readout, in readout 1, the address switching circuit 10 selects the signals input from the timing generation circuit 3 as 5EL="L", 5EL2="H", and R as shown in FIG.
Since C3="L" and SE LWR="H", the data from a1 to a9 of counter A8 is used as the row address data of the audio processing area to AO~ of the dynamic RAM II.
Output to A8.

Dynamic RAM II holds the row address data of the audio processing area input from inputs AO to A8 at the falling edge (2) of the RAS signal.

Similarly, as shown in FIG.
, 5EL2= “H”, RC3= “H”, 5ELWR=
Since it is “H”, the data of alO to a12 of counter A8 is output to AO to A2 of dynamic RAMII as column address data of the audio processing area, and the data of counter A
The Ex-ORed data of a13 of 8 and CKa13 is output to A3, and "H" is output to A4 to A8. The dynamic RAM 1l holds the column address data of the audio processing area inputted from the inputs AO to A8 at the falling edge (6) of the CAS signal.

At the falling edge (6) of the CAS signal, WE
Since the signal is H" (10), the dynamic RAM II
reads the data written in the memory cell of the audio processing area designated by the row address data and column address data, and outputs it from DOUT.

The read data output from DOUT is latch circuit B.
5 Input Input Summer.

The latch circuit B5 is a dynamic RA input from input I.
The read data (2) from M11 is held at the rising edge (31) of the signal L2 from the timing generation circuit 3 inputted from the input C, and outputted from the output O. The data (2) output from the output O is input to the input (1) of the data processing circuit 12.

Similarly, in readout 2, the dynamic RAM 11
Reads the data written in the memory cell of the audio processing area specified by the address data held by the falling edge (4) of the RAS signal and the falling edge (8) of the CAS signal, and outputs it from DOUT. do. D
The read data outputted from OUT is the latch circuit C6.
input to input I of

The latch circuit C6 is a dynamic RA input from input I.
Data read from the MII is held at the rising edge (32) of the signal L3 from the timing generation circuit 3 inputted from the input C, and outputted from the output 0. The data (2) output from the output O is input to the input I2 of the data processing circuit 12.

In this way, the operation as shown in FIG. 8(a) is repeated. The relationship between the write address, read address 1, and read address 2 at this time is briefly shown in FIGS. 8(b), (C), and (d). Here, the feature is that read address 1 and read address 20M5B are reversed. In reality, since an 8-bit audio processing area is used, it takes about 65.6 ms for the reading system to read out the 8-bit audio processing area at a period of 2T. A data string read out by each reading system over a period of approximately 65.6 ms constitutes one frame. The time to write to the 8-bit audio processing area with writing cycle T is:
It takes about 32.8ms. The relationship between write and read frames is shown in FIGS. 8(e), (f), and (g).

The data processing circuit 12 receives data from the latch circuit B5.
is input from input 11, and the data from latch circuit C6 is
is input from the input I2, and each data string is applied to the weighting function Wl for each frame as shown in FIGS. 8(h) and (i).
(t) and W2 (t) are combined and then added.

As a result, weighted data {circle around (J)} as shown in FIG. 8(j) is output from the output 0 of the data processing circuit 12.

The D/A conversion circuit 13 converts the data (2) output from the output 0 of the data processing circuit 12 into an analog signal string.

In this way, 256 bits of dynamic RAM
Of II, an 8-bit audio processing area is used to convert the pitch of double-speed audio.

(2) Mode 2 The A/D conversion circuit 1 converts the input analog signal string into 1-bit digital data and outputs it.

The output digital data ■ is input to latch circuit A4 ■
Enter. The latch circuit A4 holds the digital data (2) input from the input I at the rising edge (q) of the signal L1 from the timing generation circuit 3 input from the input C, and outputs it from the output O. The output data ■ is input to the input 11 of the selector 7. The selector 7 selects the data ■ from the input 11 according to the DS value "L" (s) input from the input C, and outputs it from the output O. The output data (■) is input to the input DIN of the dynamic RAMII.

As described above, the analog signal string is converted into digital data (2) by the A/D conversion circuit 1, held by the rising edge (q) of the signal L1, and the value is inputted to the dynamic RAM II as data (2).

Next, the operation of reading and writing data to area 1 of the dynamic RAM II will be explained.

As shown in FIG. 6, the address switching circuit 10 receives three signals input from the timing generation circuit 3 when 5EL1="H".
(j), 5EL2="L"(k), RCS="L"(
At the time of m), the data of a2 to alO of counter A8 is used as the row address data of area 1 to dynamic RA.
Output to MII's AO-A8. Dynamic RAMI
I is the input AO at the falling edge (b) of the RAS signal.
- Holds the row address data of area 1 manually input from A8.

Similarly, the address switching circuit 10, as shown in FIG.
1 = “H” (j), 5EL2 = “L” (k),
When RC3="H" (n), counter A8 all~
Output the data of a12 as column address data of area 1 to AO-AI of dynamic RAM II and
~ Outputs "L" to A8. Dynamic RAMII
is the input AO- at the falling edge (d) of the CAS signal.
Holds the column address data of area l input from A8.

At the falling edge (d) of the CAS signal, WE
Since the signal is doubled “H” (f), the dynamic RAM II
reads the data written in the memory cell of area 1 specified by the row address data and column address data, and outputs it from DOUT. DOU
Read data (2) output from T is input to input I of latch circuit B5.

Launch circuit B5 receives dynamic RA input from input I.
Data read from Mll is held at the rising edge (r) of the signal L2 from the timing generation circuit 3 inputted from the input C, and outputted from the output O.

The dynamic RAM II writes the data (2) input manually from the DIN into the memory cell of the designated area 1 in response to the falling edge (g) of the WE double signal.

In this way, in the state of mode 1, the device of this embodiment:
The operation of reading the data written in the memory cell with bit memory in area 1-2 designated by a2 to a12 of the counter A8 and simultaneously rewriting it with new data is repeated. By repeating this operation, the data will be approximately 123m5, as seen from the following equation (3).
will be temporarily stored in the memory of open area 1.

60μs X204B#123m5 (3
) (3) Mode 3 Similar to mode 2, the A/D conversion circuit 1 converts the input analog signal string into 1-bit digital data and outputs it. The output digital data ■ is input to the input ■ of the latch circuit A4. The latch circuit A4 synchronizes the digital data ■ input from the input ■ with the rising edge (q
) and output from output O. The output data ■ is input to the input 11 of the selector 7. The selector 7 selects the data ■ from the input 11 according to the DS value "L" (S) input from the input C, and outputs it from the output O. The output data ■ is input to the input DIN of the dynamic RAM 1l.

As described above, the analog signal string is converted into digital data (2) by the A/D conversion circuit 1, held by the rising edge (q) of the signal L1, and the value is inputted as data (2) to the dynamic RA Mll.

Next, the operation of reading and writing data to area 1 and area 2 of the dynamic RAM II will be explained.

As shown in FIG. 6, the address switching circuit 10 receives three signals inputted from the timing generation circuit 3 when 5EL1="H".
(j), 5EL2='''L''' (k), RC3=
When “L” (m), a2 to alo of counter A8
The data is output to AO-A8 of the dynamic RAM II as row address data of area 1. Dynamic RAM II detects the falling edge (b) of the RAS signal.
) holds the row address data of area 1 input from input AO-A8.

Similarly, as shown in FIG. 6, the address switching circuit 10 receives three signals inputted from the timing generation circuit 3 as
= “H” (j), 5EL2 = “L” (k), R
When C3="H" (n), counter A8 all~a
12 data is output as column address data of area 1 to AO-AI of dynamic RAMII, and A2
~ Outputs "L" to A8. Dynamic RA Ml
l is the input AO at the falling edge (d) of the CAS signal.
- Holds the column address data of area l input from A8.

At the falling edge (d) of the CAS signal, WE
Since the signal is doubled “H” (f), the dynamic RAM II
reads the data written in the memory cell of area 1 specified by the row address data and column address data, and outputs it from DOUT. DOU
The read data (2) output from T is input to the input (2) of the latch circuit B5.

The latch circuit B5 is a dynamic RA input from input I.
The read data (2) from the MII is held at the rising edge (r) of the signal L2 from the timing generation circuit 3 inputted from the input C, and outputted from the output 0. The output data ■ is input to the input I2 of the selector 7.

The dynamic RAM II writes the data (2) input from the input DIN into the memory cell of the specified area (1) in response to the falling edge (g) of the WE double signal.

Selector 7 selects the DS value “H” input from input C (
1) selects the data ① from the human input I2 and outputs it from output 0. The data ■' output from the output 0 of the selector 7 is input to the input DIN of the dynamic RAM 1l.

Next, as shown in FIG. 6, the address switching circuit 1o receives three signals inputted from the timing generation circuit 3 as SEL1
= “H” (j), 5EL2 = “H” (1), R
When C3="L" (o), counter B9's bO~b
The data of 8 is output as row address data of area 2 to AO to A8 of the dynamic RAM II. Dynamic RAMII uses the falling edge of the RAS signal (
C) holds the row address data of area 2 input from input AO-A8.

Similarly, the address switching circuit 10, as shown in FIG.
1 = “H” (j), 5EL2 = “H” (1),
When RC3="H" (p), counter B 9 (7)
Data from b9 to b17 to the column address of area 2.
It is output as data to AO to A8 of the dynamic RAM II. Dynamic RAM II holds the column address data of area 2 input from inputs AO to A8 at the falling edge (e) of the CAS signal.

At the falling edge (e) of the CAS signal, WE
Since the signal is doubled “L” (h), the dynamic RAMII
writes the data ■' input from the input DIN into the memory cell of area 2 specified by the row address data and column address data.

Counter B9 counts once every 60 μs at the rising edge (W) of count up clock CLK2.
Perform an up movement. When bo-b17 of counter B9 are all “H”, counter B9 outputs EOS,
Return to mode 2.

In this way, in the state of mode 3, the device of this embodiment:
The operation of reading data written approximately 123m5 ago and rewriting it with new data at the same time that was written in the memory cell with bit memory in area 1-2 specified by a2 to a12 of counter A8, and 12
An operation is performed in which data from 3n+s ago is written into a certain memory cell of the memory in area 2 designated by bO to b17 of counter B9.

By repeating these operations, data can be written to the memory in area 2 with a delay of about 123 m5.

(4) Mode 4 Similar to mode 2, the A/D conversion circuit 1 converts the input analog signal string into 1-bit digital data and outputs it. The output digital data ■ is input to the input I of the latch circuit A4. The launch circuit A4 receives the digital data inputted from the input I at the rising edge (q) of the signal L1 from the timing generation circuit 3 inputted from the input C.
It is held at output 0 and output from output 0. The output data ■ is input to the input 11 of the selector 7. The selector 7 selects the data ■ from the input 11 according to the DS value "L" (s) input from the input C, and outputs it from the output 0. The output data ■ is input to the input DIN of the dynamic RAM 1l.

As described above, the analog signal string is converted into digital data (2) by the A/D conversion circuit 1, which is held by the rising edge (q) of the signal Ll, and the value is manually inputted to the dynamic RAM II as data (2).

Next, the operation of reading and writing data to area 1 and area 2 of the dynamic RAM Mll will be described.

As shown in FIG. 6, the address switching circuit 10 receives three signals inputted from the timing generation circuit 3 as SF.

Ll=1H" (j), 5EL2="L" (k),
When RC3="L" (m), a2~ of counter A8
The data in alO is output as row address data of area 1 to AO to A8 of the dynamic RAM II. Dynamic RAM II inputs the row signal from area 1 from inputs AO to A8 at the falling edge (b) of the RAS signal.
Holds address data.

Similarly, the address switching circuit 10, as shown in FIG.
1 = “H” (j), 5EL2 = “L” (k),
When RC3="H" (n), counter A8 all~
Output the data in a12 as column address data for area 1 to A0 to A1 of the dynamic RAM II, and
"L" is output to 2 to A8. Dynamic RAMI
I is the input AO at the falling edge (d) of the CAS signal.
Holds the column address data of area 1 input from ~A8.

At the falling edge (d) of the CAS signal, WE
Since the signal is doubled “H” (f), the dynamic RAM II
reads the data written in the memory cell of area 1 specified by the row address data and column address data, and outputs it from DOUT. DOU
Read data (2) output from T is input to input I of latch circuit B5.

The latch circuit B5 is a dynamic RA input from input I.
The read data (2) from the MII is held at the rising edge (r) of the signal L2 from the timing generation circuit 3 inputted from the input C, and outputted from the output 0.

The dynamic RAM II writes the data (2) input from the input DIN into the memory cell of the designated area 1 in response to the falling edge (g) of the WE double signal.

Next, as shown in FIG. 6, the address switching circuit 10 selects three signals input from the timing generation circuit 3 as SEL 1
= “H” (j), 5EL2 = “H” (1), RC
When 3='L'' (0), counter B9's bO~
The data of b8 is outputted to AO to A8 of the dynamic RAM II as row address data of area 2. Dynamic RAM II holds the row address data of area 2 input from inputs AO to A8 at the falling edge (c) of the RAS signal.

Similarly, as shown in FIG.
="H" (j), 5EL2="H" (1), RC
3=“H” (when p>, b9 to b1 of counter B9
7 is output to AO to A8 of the dynamic RAM II as column address data of area 2. Dynamic RAM II has an area of 20 columns that is manually input from inputs A0 to A8 at the falling edge (e) of the CAS signal.
Holds address data.

At the falling edge (6) of the CAS signal, WE
Since the signal is doubled 'H' (f), dynamic RAM
ll reads the data written in the memory cell of area 2 designated by the row address data and column address data, and outputs it from DOUT. D
The read data outputted from OUT is the latch circuit C6.
input to input I of

The latch circuit C6 is a dynamic RA input from input I.
The data read from the MII is held at the rising edge (u) of the signal L3 from the timing generation circuit 3 inputted from the input C, and outputted from the output 0. The output data ■ is input to the input 12 of the data processing circuit 12. The data processing circuit 12 outputs the data ■ input from the input I2 to 0.
Output as is. The output data is input to the D/A conversion circuit 13. The D/A conversion circuit 13 converts the input 1-bit digital data into an analog signal using a double integration circuit and outputs the analog signal.

Counter B9 counts once every 60 μs at the rising edge (W) of count up clock CLK2.
Performs amplifier operation. When bQ to b17 of counter B9 all become “H”, counter B9 outputs EOS,
Return to mode 2.

In this way, in the state of mode 4, the device of this embodiment:
The operation of reading out the data approximately 123m5 ago written in the memory cell with bit memory in area 1-2 specified by a2 to a12 of counter A8 and rewriting it to new data at the same time, and the bO of counter B9. ~
The data written in the memory of area 2 specified by b17 is sequentially read out. By these operations, it is possible to simultaneously rewrite the memory in area 1 and read out the data written in the memory in area 2.

As described above, according to this embodiment, in order to perform the pitch conversion function of the double-speed voice and the function of deleting silent part data of the message, by providing the 14-stage counter A8 and the 18-stage counter B9, the 256-bit bit Dynamic RAMI
I is the audio processing area (8 bits) for pitch conversion of double-speed audio, and area 1 (2 bits) for deleting silence data.
It can be divided into an area 2 (248 bits) and an area 2 (248 bits) for writing sound part data and reproducing an audio signal without silent part data, and area 1 is included in the audio processing area. Therefore, one memory can be used effectively as if there were three memories. Also,
Although the storage capacity is reduced to 8 bits, it is only about 50°n's, so there is almost no difference in storage time, and it has the function of being able to record without cutting off the beginning of words.

Effects of the Invention As is clear from the above embodiments, the present invention can realize the pitch conversion function of double-speed playback sound and the message recording/playback function in memory with a simple and inexpensive circuit configuration. Moreover, 1
It has the advantage that it can be implemented using only one memory. Furthermore, it has the advantage that by simply installing a simple level judgment circuit, it can also be used as the pitch conversion processing area for double-speed audio, and can record and play back messages with silent parts deleted. The device is effective. In addition, since it is possible to convert the pitch of double-speed audio, the time required to play back and listen to the tape recorder on which the message was recorded can be cut in half, especially when listening to the message through a telephone line by remote control. This has the effect of reducing charges because the call time is shortened.

[Brief explanation of the drawing]

Fig. 1 is a schematic block diagram of an embodiment of the answering machine of the present invention, Fig. 2 is a more detailed block diagram of the embodiment, and Fig. 3 is the electrical wiring of the level determination circuit constituting the embodiment. Figure 4 is an explanatory diagram illustrating the silent part and sound part systems, Figures 5 (A) to (D) are waveform diagrams of each part, respectively, and Figure 6
7 is a diagram showing an overview of addresses and data in each state, FIG. 7 is a diagram showing states in each mode, and FIG. 8 is a timing chart showing write and read operations. 1... A/D conversion circuit, 2... Level determination circuit, 3... Timing generation circuit, 4.5
．． 6... Launch circuit, 7... Selector, 8.9... Counter, 10...
Address switching circuit, 11...Dynamic RA
M, 12... Data processing circuit, 13...
・D/A conversion circuit. Name of agent: Patent attorney Toshio Nakao 1 person, 0 comments - To the deaf - ~
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Claims (2)

[Claims] (1) An A/D conversion circuit that converts an analog signal string supplied from the outside into digital data, and the digital data converted using the A/D conversion circuit is written for pitch conversion of double-speed audio. a first storage means; a second storage means for writing digital data converted using the A/D conversion circuit in order to reproduce an analog signal sequence;
A storage means control circuit that controls writing and reading by controlling the first storage means when converting the pitch of double-speed audio and controlling the second storage means when recording and playing back an analog signal string; A data processing means outputs the digital data as it is when performing playback, and processes the input digital data at double speed when converting the pitch of double speed audio;
1. An answering machine comprising a D/A conversion circuit that converts data into an analog signal string. (2) A level determination circuit that detects either unvoiced part data or voiced part data out of an analog signal string composed of externally supplied silent part data, unvoiced part data, and voiced part data. writing digital data obtained by converting silent part data and unvoiced part data using an A/D conversion circuit into a first storage means until the level determination circuit determines the sound part data; A storage means control circuit having a function of writing the silent part data and unvoiced part data written in the first storage means into a second storage means when the sound part data is determined by the level determination circuit. An answering machine as set forth in claim (1), characterized in that: