JPH01248548A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH01248548A JPH01248548A JP63077122A JP7712288A JPH01248548A JP H01248548 A JPH01248548 A JP H01248548A JP 63077122 A JP63077122 A JP 63077122A JP 7712288 A JP7712288 A JP 7712288A JP H01248548 A JPH01248548 A JP H01248548A
- Authority
- JP
- Japan
- Prior art keywords
- island
- hybrid integrated
- circuit
- integrated circuit
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007789 sealing Methods 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 1
- 230000005855 radiation Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to hybrid integrated circuit devices.
従来、この種の混成集積回路装置は第２図（ａ）。 Conventionally, this type of hybrid integrated circuit device is shown in FIG. 2(a).
（ｂ）に示すように、金属性のリードフレーム１のアイ
ランドＩＡ上に接着された回路基板２上に１半導体ＩＣ
等の回路素子３を搭載し、この回路素子３と回路基板２
及び金属細線４等を樹脂６により封止した構造となって
いた。As shown in (b), one semiconductor IC is mounted on a circuit board 2 bonded to an island IA of a metal lead frame 1.
The circuit element 3 and the circuit board 2 are mounted.
It had a structure in which thin metal wires 4 and the like were sealed with resin 6.
上述した従来の混成集積回路装置はリードフレームのア
イランドＩＡ上に接着剤をもちいて回路基板２を貼り付
けているが、この構造は回路基板２の基板材料がアルミ
ナ、ベリリア等比較的熱伝導率の良好な場合には、基板
のもつ伝導効果によりパッケージの放熱性は維持されて
いた。In the conventional hybrid integrated circuit device described above, the circuit board 2 is attached to the island IA of the lead frame using an adhesive, but in this structure, the circuit board 2 is made of a material with relatively high thermal conductivity such as alumina or beryllia. In the case of good conditions, the heat dissipation of the package was maintained due to the conduction effect of the substrate.
しかし、混成集積回路装置の軽量化、価格低減の対応等
により、回路基板の有機材料化が進められている。回路
基板がフェノール基板、ガラスエポキシ基板等の場合に
は一般には熱伝導率は悪く、熱伝導効果による放熱効果
は期待できるものではない。従って、消費電力量の大き
い半導体ＩＣ又はトランジスタのチップを搭載すること
が不可能となるという欠点があった。その為、各種半導
体ＩＣ等を搭載したこの種の混成集積回路装置の応用分
野は大きく制約されていた。However, in order to reduce the weight and cost of hybrid integrated circuit devices, the use of organic materials for circuit boards is progressing. When the circuit board is a phenol board, a glass epoxy board, etc., the thermal conductivity is generally poor, and the heat dissipation effect due to the heat conduction effect cannot be expected. Therefore, there is a drawback that it is impossible to mount a semiconductor IC or a transistor chip that consumes a large amount of power. Therefore, the field of application of this type of hybrid integrated circuit device equipped with various semiconductor ICs and the like has been greatly restricted.
本発明の混成集積回路装置はリードフレームのアイラン
ド表面に固着された回路基板と、該回路基板上に固着さ
ｎた回路素子と、前記アイランドと回路基板と回路素子
とを封止する封止樹脂とからなる混成集積回路装置であ
って、前記アイランドの裏面に放熱板を固着したもので
ある。The hybrid integrated circuit device of the present invention includes a circuit board fixed to the island surface of a lead frame, a circuit element fixed to the circuit board, and a sealing resin sealing the island, the circuit board, and the circuit element. This is a hybrid integrated circuit device consisting of a heat dissipation plate fixed to the back surface of the island.
次に、本発明について図面全参照して説明する。 Next, the present invention will be explained with reference to all the drawings.
第１図（ａ） 、 （ｂ）は本発明の一実力市例の平面
図及びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of one example of the present invention.
第１図（ａ） 、 （ｂ）において、金属性のリードフ
レーム１のアイランドＩＡの表面にはＭ機基板をペース
とした回路基板２が接着剤によ）接着されている。そし
て、アイランドＩＡの裏面には、厚さ１．９ｍｍのＭ板
７が熱伝導性接着剤により固着されている。Ｍ板を固着
する場所は、少なくとも回路基板上の回路素子３の裏１
１１１ Ｋ位置するようにｖ！４整する。尚第１図（ａ
） 、 （ｂ）においてψは金Ｍ細線、６は封止樹脂で
ある。In FIGS. 1(a) and 1(b), a circuit board 2 based on an M machine board is adhered to the surface of an island IA of a metal lead frame 1 using an adhesive. An M plate 7 having a thickness of 1.9 mm is fixed to the back surface of the island IA with a thermally conductive adhesive. The place where the M board is fixed is at least the back side 1 of the circuit element 3 on the circuit board.
111 V to position K! 4 Adjust. Furthermore, Figure 1 (a
), (b), ψ is a gold M thin wire, and 6 is a sealing resin.
このように構成された本実施例によれば、回路素子等で
発生する熱はＭ板７によシ放熱されるので、消費電力の
大きい回路素子を搭載できる。According to this embodiment configured in this way, the heat generated by the circuit elements and the like is radiated through the M board 7, so that circuit elements with large power consumption can be mounted.
上記実施例においては放熱板としてＭ板を用いたが他の
金属板や、グラファイトやアルミナセラミック等の板を
用いてもよい。In the above embodiment, an M plate was used as the heat sink, but other metal plates, graphite, alumina ceramic plates, etc. may also be used.
以上説明したように本発明は、リードフレームのアイラ
ンドの裏面に放熱板を固着することによシ放熱特性が向
上するため、混成集積回路装置に消費電力の大きい回路
素子を搭載できる効果がある。As described above, the present invention has the effect that circuit elements with high power consumption can be mounted on a hybrid integrated circuit device, since the heat dissipation characteristics are improved by fixing the heat dissipation plate to the back surface of the island of the lead frame.
第１図（ａ） 、 （ｂ）は本発明の一実施例の平面図
およびＡ−Ａ’線断面図、第２図（ａ） 、 （ｂ）は
従来の混成集積回路装置の一例の平面図及びＢ−Ｂ’線
断面図である。
１・・・・・・リードフレーム、ＩＡ・・・・・・アイ
ランド、２・・・・・・回路基板、３・・・・・・回路
素子、４・・・・・・金属細線、６・・・・・・封止樹
脂、７・・・・・・Ｍ板。
代理人 弁理士 内 原 音
声 １ 図FIGS. 1(a) and (b) are a plan view and a sectional view taken along line A-A' of an embodiment of the present invention, and FIGS. 2(a) and (b) are plan views of an example of a conventional hybrid integrated circuit device. FIG. 1...Lead frame, IA...Island, 2...Circuit board, 3...Circuit element, 4...Metal thin wire, 6 ...Sealing resin, 7...M plate. Agent Patent Attorney Uchihara Audio 1 Diagram
Claims (1)
板と、該回路基板上に固着された回路素子と、前記アイ
ランドと回路基板と回路素子とを封止する封止樹脂とか
らなる混成集積回路装置において、前記アイランドの裏
面に放熱板を固着したことを特徴とする混成集積回路装
置。A hybrid integrated circuit device comprising a circuit board fixed to an island surface of a lead frame, a circuit element fixed to the circuit board, and a sealing resin sealing the island, the circuit board, and the circuit element, A hybrid integrated circuit device characterized in that a heat sink is fixed to the back surface of the island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63077122A JPH01248548A (en) | 1988-03-29 | 1988-03-29 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63077122A JPH01248548A (en) | 1988-03-29 | 1988-03-29 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01248548A true JPH01248548A (en) | 1989-10-04 |
Family
ID=13624991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63077122A Pending JPH01248548A (en) | 1988-03-29 | 1988-03-29 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01248548A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969414A (en) * | 1994-05-25 | 1999-10-19 | Advanced Technology Interconnect Incorporated | Semiconductor package with molded plastic body |
| WO2014094754A1 (en) * | 2012-12-20 | 2014-06-26 | Conti Temic Microelectronic Gmbh | Electronic module with a plastic-coated electronic circuit and method for the production thereof |
-
1988
- 1988-03-29 JP JP63077122A patent/JPH01248548A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5969414A (en) * | 1994-05-25 | 1999-10-19 | Advanced Technology Interconnect Incorporated | Semiconductor package with molded plastic body |
| WO2014094754A1 (en) * | 2012-12-20 | 2014-06-26 | Conti Temic Microelectronic Gmbh | Electronic module with a plastic-coated electronic circuit and method for the production thereof |
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