JPH01246965A - Synchronizing separator circuit - Google Patents

Abstract

PURPOSE:To make stable synchronizing signals always separable by detecting the step-out of the lowest level of the synchronizing signals caused by spike-like noises and waveform distortion and separating the synchronizing signals based on the detected step-out. CONSTITUTION:The step-out of synchronizing signals caused by spike-like noises and waveform distortion is detected by means of the 1st and 2nd peak clampers 2 and 4, an LPF 3, the 1st and 2nd integrators 5 and 6, and a difference circuit 7. The comparison voltage of a comparator 8 is corrected based on the detected step out and position of the synchronizing signals are accurately detected. The position of the edge of the synchronizing signals is detected by means of the 2nd comparator 9 and gate pulse generator 10, and the component other than the edge of the synchronizing signals is removed by means of a synchronizing signal detecting circuit 11. Thus stable synchronizing signals are always separated from input signals (a).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization separation circuit that separates a synchronization signal from an input signal, such as a television signal, on which a synchronization signal is superimposed.

[Conventional technology]

Television signal hiko How to digitally process a signal in which a synchronization signal and an image signal are superimposed, and when sampling with a sampling clock synchronized with the signal synchronization signal, it is necessary to extract the synchronization signal. This is generally performed using a synchronous separation circuit.

In the conventional sync separation circuit, the lowest level of the sync signal is clamped to a constant level, a judgment level is set based on the - constant level, and a voltage comparator is used to compare the voltage. The synchronization signal was detected and separated.

[Problem to be solved by the invention]

In the conventional synchronization separation circuit described above, synchronization occurs when there is a signal that is caught at the voltage comparator's judgment level due to spike-like pulses being superimposed on the input signal or waveform distortion due to over-equalization of the frequency characteristics of the transmission path. There was a problem that it could be mistakenly judged as a signal. In addition, when peak clamping is used, there is a problem that if periodic pulse-like noise is superimposed and the amplitude is large, the noise will be detected by the voltage comparator and the synchronization signal will not be detected.

[Means to solve the problem]

The synchronization separation circuit of the present invention is a synchronization separation circuit that separates a synchronization signal from an input signal on which the synchronization signal is superimposed, such as a television signal. a peak clamper, a low-pass filter that removes spike-like noise and waveform distortion from the input signal, and a second peak clamper that peak-clamps the output of the low-pass filter to a predetermined level. and a first integrator and a second integrator that integrate each output of the first peak clamper and the second peak clamper, respectively, and an output of the first integrator and the second integrator. a first comparator that compares a comparison voltage changed by the output of the difference circuit with the output of the first peak clamper; and a second peak clamper. a second comparator that compares the output of the input signal with a predetermined comparison level, and generates a gate pulse from the output of the second comparator that indicates the range of positions where edges of the synchronization signal of the input signal exist. It is composed of a gate pulse generation circuit and a synchronization signal detection circuit that detects a synchronization signal from the output of the first comparator and the output of the gate pulse generation circuit, and always stably separates the synchronization signal from the input signal. This is how it was done.

[Effect]

In the present invention, first. a second peak clamper and a low-pass filter; The second integrator and difference circuit detect the shift in the lowest level of the synchronization signal due to sysbic noise and waveform distortion, and correct the comparison voltage of the first comparator to accurately detect the position of the synchronization signal. , the position of the edge of the synchronization signal is detected by the second comparator and the gate pulse generation circuit, and the synchronization signal detection circuit removes components other than the edges of the synchronization signal to always generate a stable synchronization signal from the input signal. To separate.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

The first factor is a block diagram showing an embodiment of the present invention.

In the figure, 1 is a synchronization signal such as a television signal! an input terminal to which an i-folded input signal is applied; 2;
is a peak clamper that peak-clamps the input signal from input terminal 1 to a predetermined level, and 3 is a low-pass filter that removes spike-like noise and waveform distortion from the input signal. The filter 3 is composed of a buffer amplifier 3-1 and a low-pass filter 3-2. 4 is this low-pass filter 3
5 is an integrator that integrates the output of the peak clamper 2 to a predetermined level, and this integrator 5 is composed of a buffer amplifier 5-1 and a low-pass filter 5-2. ing.

6 is an integrator that integrates the output of the peak clamper 4, 7 is a difference circuit that takes the difference between the output of the integrator 5 and the output of the integrator 6, and 8
9 is a comparator that compares the comparison voltage changed by the output of this difference circuit T with the output of the peak clamper 2; 9 is a comparator that compares the output of the peak clamper 4 with a predetermined comparison level; A gate pulse generation circuit 11 generates a gate pulse indicating the position range of the edge of the synchronization signal of the input signal from the output of the comparator 9; A synchronous signal detection circuit 12 detects a signal, and 12 is an output terminal from which a 9 synchronous signal is obtained.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS.

First, the television signal 1 from the input terminal 1 is peak-clamped to the level of voltage A (see b in FIG. 4) by the peak clamper 2. Then, this peak clamper 2
The comparator 8 compares the output voltage with the reference voltage B (see b in FIG. 4) controlled by the output of the difference circuit T, detects the edge of the synchronizing signal, and further generates a game pulse in the synchronizing signal detection circuit 11. Gate pulse l from circuit 10
Components other than the synchronizing signal are removed, and the synchronizing signal is correctly detected and output from the output terminal 12.

On the other hand, the output of the peak clamper 2 is set to the buffer amplifier 5.
-1 and an integrator 5 consisting of a low-pass filter 5-2, and the average value of the output of the peak clamper 2 is determined. Also,
A low-pass filter 3 consisting of a buffer amplifier 3-1 and a low-pass filter 3-2 removes spike-like noise and waveform distortion superimposed on the television signal 1 from the input terminal 1, and removes peaks. The clamper 4 clamps the peak at the level of the stain pressure A, and the integrator 6 integrates it to obtain the average value of the output of the peak clamper 4. The difference between the output e of the integrator 5 and the output f of the integrator 6 is determined by a difference circuit T. And this difference circuit 1
The output is the deviation value when the lowest level of the synchronization signal of the television signal a from the input terminal 1 is deviation due to noise or the like.

Next, the output voltage of the peak clamper 2 is compared with a predetermined reference voltage B (see b in FIG. 4) by a comparator 8, and a synchronization signal is detected. At this time, the value of the reference voltage B is controlled by the output of the difference circuit 1 so that the correct edge of the synchronizing signal is always detected.

However, here, if there is noise in the input signal that is caught by the reference voltage B, it will be detected as a synchronization signal. Then, the output d of the peak clamper 4 is compared with a predetermined reference value C (see d in FIG. 4) by a comparator 9, a synchronizing signal is detected, and a pulse gate generating circuit 10 is used to detect only the edge portion of the synchronizing signal. A gate pulse l is generated to select.

FIG. 2 is a block diagram showing an example of the configuration of this gate pulse generation circuit 10. This gate pulse generation circuit 10 includes a delay circuit 10-2 which delays the output of the comparator 9 from the input terminal 10-1 by a gate pulse width TW (see 11 in FIG. 4), and this delay circuit. If the output of 10-2 is k, then it consists of a logic operation circuit 10-3 that performs the logical operation of -h, and a logic operation circuit 10-4 that performs the logical operation of -h, and this logic operation circuit 10-3 and Logic operation circuit 10-4
The output of each of the two types of gate pulses 11°1'z
(Refer to '1+12 in Figure 4) is the synchronization signal detection circuit 1.
Output to 1. Note that 10-5 and 10-6 are output terminals of the logical operation circuits 10-3 and 10-4, respectively.

FIG. 3 is a block diagram showing an example of the configuration of the synchronization signal detection circuit 11 shown in FIG. 1.

This synchronization signal detection circuit 11 converts the output g of the comparator 8 from the input terminal 11-1 into the delay numerator of the low-pass filter 3 +, pr (
(see h in Figure 4) and half the time T of the gate pulse width Tw.
A delay circuit 11-2 that delays by 1, PF + TV/2 (see 0 in FIG. 4), an output O of this delay circuit 11-2, and a gate pulse 11 from an input terminal 11-3, 11-4, 1. Logic circuit that takes the AND of 11-5.11-6
and a set/reset flip-flop 11-1 which is set when the output of the logic circuit 11-5 falls and is reset when the output of the logic circuit 11-6 rises. The output of this set/reset flip 70 switch 11-7 obtained at the output terminal 11-8 becomes the output of the synchronous separation circuit.

FIG. 4 is an operation waveform diagram of each part used to explain the operation of FIGS. 1 to 3, and shows operation waveforms corresponding to the symbols shown in FIGS. 1 to 3. And this figure 4 is
(
1) and 01).

〔Effect of the invention〕

As explained above, according to the present invention, even if spike noise or waveform distortion is superimposed on the synchronization signal, the synchronization signal can be correctly separated, and the input signal actually used as an edge is Since it is not subject to distortion caused by a low-pass filter, etc., it has the effect of obtaining a synchronization signal at the correct position and without jitter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the gate pulse generation circuit of FIG. 1, and FIG. 3 is an example of the configuration of the synchronization signal detection circuit of FIG. 1. FIG. 4 is an operation waveform diagram of each part to explain the operation of FIGS. 1 to 3. 2. Skewer/kai peak clamper, 3. Low-pass filter, 4
@aha beak clamper, 5.5a 〇・integrator, 7・
Meeting/O difference circuit, 8, 9, 11ψ conflict comparator, 10...
Gate pulse generation circuit, 11... synchronous signal detection circuit.

Claims (1)

[Claims] A sync separation circuit that separates a sync signal from an input signal on which a sync signal is superimposed, such as a television signal, includes a first peak clamper that peak-clamps the input signal to a predetermined level; a low-pass filter that removes spike-like noise and waveform distortion from the low-pass filter; a second peak clamper that peak-clamps the output of the low-pass filter to a predetermined level; a first integrator and a second integrator that respectively integrate each output of a second peak clamper; and a difference circuit that takes the difference between the output of the first integrator and the output of the second integrator. , a first comparator that compares a comparison voltage changed by the output of the difference circuit with the output of the first peak clamper, and a first comparator that compares the output of the second peak clamper with a predetermined comparison level. a second comparator for
a gate pulse generation circuit that generates a gate pulse from the output of the second comparator to indicate a range of positions where edges of the synchronization signal of the input signal exist; and an output of the first comparator and the gate pulse generation circuit. 1. A synchronization separation circuit comprising: a synchronization signal detection circuit for detecting a synchronization signal from the output of a synchronization signal, and always stably separating the synchronization signal from the input signal.