JPH01246907A - Oscillation circuit device - Google Patents

Abstract

PURPOSE:To make the threshold voltage of a complementary transistor(TR) circuit lower, to reduce the number of manufacturing processes of the title oscillation circuit device, and to obtain stable oscillations at a low voltage by using the complementary TR circuit whose one conductive TR is of depression type for the device. CONSTITUTION:An oscillating operation area is provided in such a way that a low threshold voltage is set by using a D-type (n) channel TR Q2N having a low threshold voltage V1 and setting a relation of V1<V2 between the threshold voltage V1 and the voltage V2 of another transistor TR Q2P against a supply voltage +VDDL. The input V1 and output V0 of a CMOS inverter 10 form a waveform around the threshold voltage of a circuit and the waveform of the output V0 becomes a sine wave-like waveform having s small amplitude since the supply voltage +VDDL is low. Since the threshold voltage of the circuit of another CMOS inverter is equal to that of the circuit of the inverter 10, the output of the inverter becomes imperfect square waves even when the amplitude of the waveform of the output V0 of the inverter 10 is small. Therefore, this oscillation circuit device is constituted in such a way that the oscillation output 9 of a CMOS inverter 3 can become perfect square waves.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an oscillation circuit device used for supplying clocks to internal circuits in semiconductor integrated circuit devices, and in particular to an oscillation circuit device that uses complementary transistors such as the 0M08 circuit. The invention relates to an oscillation circuit device.

[Conventional technology]

FIG. 4 is a circuit diagram showing a conventional oscillation circuit device. Three CMOS inverters configured with enhancement type (hereinafter abbreviated as E type) transistors 1.2.
3 are connected in series.

Output V of CMOS inverter 1. is connected to the input of CMOS inverter 2, the output of CMOS inverter 2 is connected to the input of CMOS inverter 3, and the output of CMOS inverter 3 is connected to oscillation output 9. The resistor 4 and the oscillating resonator 5 are connected in parallel, and both ends thereof are connected to the input V1 and the output vo of the CMOS inverter 1, respectively. Also, between the input v1 of the CMOS inverter 1 and the ground level, and the output V. A capacitor 6.7 is connected between the ground level and the ground level. The resistor 4 operates as a feedback resistor, the oscillating resonator 5 and the capacitors 6.7 operate as a resonant circuit, and together with the CMOS inverter 1 constitute an oscillating circuit 8.

FIG. 5 is a circuit diagram showing the configuration of a CMOS inverter. The E-type P-channel transistor 05P has its source connected to the power supply voltage +VDO, its gate connected to the input V, and its drain connected to the output ■. connected to. The E■ type N-channel transistor 05N has its source at ground level, its gate at input VI, and its drain at output V.

connected to.

FIG. 6 is a graph showing the input/output characteristics of the CMOS inverter shown in FIG.

If the input V1 takes a value from OV to the first threshold voltage V1, then the output V. is the power supply voltage +V00.

When the input ■I takes a value from the second threshold voltage V2 to the power supply voltage terminal ■, the output V. becomes OV.

O Output voltage V if the input V takes a value from the first threshold voltage V1 to the second threshold voltage V1. is a function of the gate voltage ■1 of transistors Q and Q and is 5P
5N is determined by the ratio of each resistance. This region is defined as the oscillation operating region. The H/L threshold voltage □1 at which the input V1 and the output □ become equal has a value approximately intermediate between the first threshold V 1 and the second threshold V 2 .

FIG. 7 shows the input V1. during oscillation of the CMOS inverter. Output■. 7 is a timing chart showing the relationship between the waveform and the input/output characteristics shown in FIG. 6, and the output of the CMOS inverter 2. FIG. CMOS inverter input V1
The waveform of is input ■ and output ■ due to the feedback loop including the oscillating resonator 5 connected between its input and output. It becomes a sine wave shape centered on the H/L threshold value V1H where the values are equal. The waveform of the output Vo becomes a sinusoidal waveform with a larger amplitude, and the center voltage is the H/L threshold voltage v11[.

CMOS inverter 2 receives this output V. Takes as input and outputs an incomplete square wave. This incomplete rectangular wave is turned into an almost perfect rectangular wave by the CMOS inverter 3 at the subsequent stage. Also, the H/L threshold voltage V of the CMOS inverter is 2°3.
By making 111 equal, the duty ratio of this rectangular wave becomes 1. The frequencies of the sine wave and the rectangular wave become the resonant frequencies of the oscillation sensor 5.

In such an oscillation circuit, the operation when the power supply voltage +VDD is lowered will be described. As the power supply voltage VDo is gradually lowered, the first threshold voltage (2) hardly changes, but the second threshold voltage (2) gradually decreases.

The first threshold voltage (1) is determined by the characteristics of the transistor 05N, and the second threshold voltage (2) is determined by the power supply voltage V. The value minus 0,
In other words, the negative value “”v −v” is 2
This is because it largely depends on the characteristics of the DD transistor Q5P and remains almost constant.

There is an oscillation operating region while maintaining V < V2, but the power supply voltage +■. If it is made low, the oscillation operating region no longer exists and oscillation becomes impossible. Also, if the threshold values of both P-channel and N-channel transistors are lowered, V
Although the relationship 2 is maintained even for a relatively low power supply voltage +DO, the effect is small and the El manufacturing process increases.

[Problem to be solved by the invention]

Since the conventional oscillation circuit device is configured as described above, if the power supply voltage is set to a low voltage such as 1.5V, there is a possibility that the oscillation will stop. In addition, in order to maintain stable oscillation even at such low voltage, CM
There is a problem in that the threshold voltages of both channels of the transistors of the OS inverter must be lowered, which increases the number of manufacturing steps.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to suppress the increase in manufacturing steps and to obtain an oscillation circuit device that stably oscillates even at a low power supply voltage.

[Means to solve the problem]

The oscillation circuit device according to the present invention includes: a first complementary transistor circuit in which one conductivity type transistor is a depletion type (hereinafter abbreviated as D type) and has a predetermined threshold; and the first complementary transistor circuit. a second complementary transistor circuit whose input is connected to the output of the first complementary transistor circuit, the transistor having the same conductivity type as that in the first complementary transistor circuit is of type D, and has a predetermined threshold; The feedback loop includes a resonator provided between the input and output of a type transistor circuit.

[Effect]

Since the oscillation circuit device according to the present invention uses a complementary transistor circuit in which one conductivity type transistor is a D type, the )l/L@ value voltage becomes low.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 1 is a circuit diagram showing an oscillation circuit device according to an embodiment of the present invention. A CM composed of a D-type N-channel transistor and an F-type P-channel transistor.
An OS inverter 10.11 is incorporated in place of the CMOS inverter 1.2 shown in FIG. Oscillation circuit section 12 includes a CMOS inverter 10. The rest of the configuration is similar to the conventional oscillation circuit device shown in FIG.

FIG. 2 is a circuit diagram showing the configuration of the CMOS inverter 10. The CMOS inverter 10 is composed of a D-type N-channel transistor 02N and an E-type P-channel transistor Q2P, and their connection relationship is the same as that of the CMOS inverter 1 shown in FIG.

FIG. 3 is a graph showing the input/output characteristics of CMOS inverter 0 shown in FIG. Since a D-type N-channel transistor is used, the H/L threshold voltage V□1 is lower than conventional
1. is set. In addition, the first threshold voltage v1 mentioned above is also lower, so the power supply voltage +VDOL is lower than before.
Also, the relationship v<v2 holds true with the second threshold voltage V, and an oscillation operation region exists.

Similar to the conventional oscillation circuit device described above, the input V and output V of CMOS inverter 0. is H/L threshold voltage vT
A waveform centered on HL is formed.

Since the power supply voltage +VDOL is low, the waveform of the output (2) is a sinusoidal waveform with a small amplitude. H/L threshold voltage of CMOS inverter 1 ■THL is CMOS inverter 0
The H/L threshold voltage V is the same as i11, and the oscillation output 9 output from the CMOS inverter 3
is configured to be a perfect rectangular wave with a duty ratio of 1. Note that by changing the configuration, it is also possible to output a rectangular wave with a duty ratio other than 1.

In the above embodiment, a CMOS inverter using D-type N-channel transistors has been described, but if the CMOS inverter is configured using D-type P-channel transistors, the second threshold voltage v2 described above increases and the same effect can be obtained. is obtained. The same applies to complementary transistor circuits other than CMOS inverters.

Note that if both transistors are of the D type, the manufacturing process will increase and the power consumption will also increase, which is not practical.

〔Effect of the invention〕

As described above, according to the present invention, since the oscillation circuit device is configured using a complementary transistor circuit in which one of the conductivity type transistors is the D type, the oscillation circuit device can be stabilized even at a low power supply voltage while suppressing the increase in manufacturing steps. An oscillation circuit device that oscillates can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an oscillation circuit device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an oscillation circuit device according to an embodiment of the present invention.
A circuit diagram of a MOS inverter, Fig. 3 is a graph showing the input/output characteristics of the CMOS inverter, Fig. 4 is a circuit diagram showing a conventional oscillation circuit device, and Fig. 5 is a graph of a CMOS inverter used in a conventional oscillation circuit device. The circuit diagram, FIG. 6 is a graph showing the input/output characteristics of the CMOS inverter, and FIG. 7 is a timing chart of the oscillation operation of the conventional oscillation circuit device. In the figure, 4 is a feedback resistor, 5 is an oscillation resonator, 6.7 is a capacitor, 10 is a CMOS inverter, and 12 is an oscillation circuit section. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) One of the conductivity type transistors is a depression type, and has an input connected to a first complementary transistor circuit having a predetermined threshold, and an output of the first complementary transistor circuit; A transistor of the same conductivity type as in the first complementary transistor circuit is a depletion type transistor, and is provided between a second complementary transistor circuit having a predetermined threshold and an input/output of the first complementary transistor circuit. An oscillator circuit device comprising a feedback loop including an oscillator.