JPH01246844A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01246844A JPH01246844A JP7520088A JP7520088A JPH01246844A JP H01246844 A JPH01246844 A JP H01246844A JP 7520088 A JP7520088 A JP 7520088A JP 7520088 A JP7520088 A JP 7520088A JP H01246844 A JPH01246844 A JP H01246844A
- Authority
- JP
- Japan
- Prior art keywords
- film
- isolation
- isolation region
- grooves
- locos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000005856 abnormality Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体装置の製造方法に係り、誘電体による素
子分離法に関する6
〔従来の技術]
従来、Si半導体基板の表面から極めて細い線巾で素子
分離法としてトレンチ・アイソレーションによる誘電体
分離法があった。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and relates to a device isolation method using a dielectric material. As an element isolation method, there was a dielectric isolation method using trench isolation.
〔発明が解決しようとする課題1
しかし、上記従来技術によるとトレンチ・アイソレーシ
ョンのみでは大面積のアイソレーション領域を要する部
分(例へばパッドや配線部分等)を要する集積回路装置
に於ては適用が出来ないと云う課題があった。そこで、
当然の事だがトレンチ・アイソレーションとLOGOS
アイソレーションの併用と云う事が考えられるが、この
場合にもLOGOSアイソレーションのアイソレージジ
ン部端の形状に異常が発生し、例へばLOCOSアイソ
レーション部端に極めて細い溝が形成されたりして、該
細い溝を埋め込む為に再度トレンチ・アイソレーション
形成と同様の処理をせねばならないと云う課題等があっ
た。[Problem to be Solved by the Invention 1] However, according to the above-mentioned prior art, trench isolation alone cannot be applied to integrated circuit devices that require large-area isolation areas (for example, pads and wiring areas). There was a problem that I couldn't do. Therefore,
Naturally, trench isolation and LOGOS
It is possible that isolation is used in combination, but in this case as well, an abnormality may occur in the shape of the end of the isolation part of LOGOS isolation, for example, an extremely thin groove may be formed at the end of the LOCOS isolation part. There was a problem in that in order to fill in the narrow trenches, the same process as trench isolation formation had to be performed again.
本発明は、かかる従来技術の課題を解決し、トレンチ・
アイソレーションとLOGOSアイソレーションの併用
によって細いアイソレーションと大面積を要する部分の
アイソレーションとをLOGOSアイソレーション端部
においても異常な形状を現出させずに、又、簡単な工程
で製造することができる方法を提供する事を目的とする
。The present invention solves the problems of the prior art and
By combining isolation and LOGOS isolation, it is possible to manufacture thin isolation and isolation in areas that require a large area without creating abnormal shapes even at the edges of LOGOS isolation, and with a simple process. The purpose is to provide a method that can be used.
[課題を解決するための手段]
本発明は上記課題を解決するために、半導体装置の製造
方法に関し、半導体基板の表面からドライ・エッチング
により溝(トレンチ)が形成され、該溝内にCVD5
i O、膜や燐ガラス膜等を埋め込んだ、いわゆるトレ
ンチ・アイソレーションによる誘電体素子分離領域を形
成後、半導体基板表面の大面積にわたってアイソレーシ
ョン領域を要する部分にいわゆるLOGOSによるアイ
ソレーション領域を形成する手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor device, in which a groove (trench) is formed from the surface of a semiconductor substrate by dry etching, and a CVD5
After forming a dielectric element isolation region by so-called trench isolation, which is filled with iO, a phosphorous glass film, etc., an isolation region by so-called LOGOS is formed over a large area of the semiconductor substrate surface where an isolation region is required. take measures to do so.
[実 施 例] 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.
第1図は本発明の一実施例を工程順に示したものである
。すなわち、
(a)Si基板lの表面にドライ・エッチングにより細
い溝(トレンチ)を形成し、熱酸化S i Ox膜(1
)2を全面に形成後、例へばCV D S i Ox膜
を全面に形成したり、あるいはCVDりんガラス膜を形
成後、熱処理したりして、トレンチ内に埋め込みガラス
3を形成し、表面のこれらガラス層をエッチ・バックに
より除去する事により、トレンチ・アイソレーション部
4を形成することができる0次に、
(b)熱酸化SiO2膜(2)とCV D +、m J
:6si sNa膜6を形成し、ホト・エツチングによ
り素子部これら熱酸化5iO−膜(2)5と5iiN4
膜6を残して除去する。これら残存膜端部は通常トレン
チ・アイソレーション部4の内側に形成するが、オーバ
ー・ラップ部7に示す如く、少々S1面にはみ出して形
成されても良い。FIG. 1 shows an embodiment of the present invention in the order of steps. That is, (a) a thin groove (trench) is formed on the surface of the Si substrate l by dry etching, and a thermally oxidized SiOx film (1
) 2 on the entire surface, for example, a CVD Si Ox film is formed on the entire surface, or a CVD phosphorous glass film is formed and then heat treated to form an embedded glass 3 in the trench, and these on the surface are removed. By removing the glass layer by etching back, the trench isolation part 4 can be formed. (b) Thermal oxidation SiO2 film (2) and CV D +, m J
: 6si sNa film 6 is formed, and the element portions are thermally oxidized 5iO- films (2) 5 and 5iiN4 by photo-etching.
It is removed leaving the film 6 behind. These remaining film ends are normally formed inside the trench isolation section 4, but as shown in the overlap section 7, they may be formed slightly protruding from the S1 surface.
次で、
(c)熱酸化によりL OCOS S i O2膜8を
大面積にアイソレーションを要する部分に形成をし、S
i s N a膜6と熱酸化5iOz膜(2)を除去
することにより、素子部9にSiを現出させることがで
きる、尚前記オーバー・ラップ部7にはバーズ・ピーク
部lOに示す如く、LOGO3端部が前記トレンチ・ア
イソレーション部4内に5isN4膜6の端部を形成し
た部分から延在せるL OCOS S i O2膜8の
場合に現出する形状とは異った形で形成される事になる
が、比較的大きなアイソレージ3ン領域部では前記バー
ズ・ピーク部lOが現出しても実用上問題はないことと
なる。Next, (c) a LOCOS SiO2 film 8 is formed in a large area where isolation is required by thermal oxidation, and the S
By removing the i s Na film 6 and the thermally oxidized 5iOz film (2), Si can be made to appear in the element portion 9. Furthermore, in the overlap portion 7, as shown in the bird's peak portion lO, Si can be exposed. , the end of LOGO3 is formed in a shape different from the shape that appears in the case of the LOCOS SiO2 film 8 extending from the part where the end of the 5isN4 film 6 is formed in the trench isolation part 4. However, in a relatively large isolation region, there is no practical problem even if the bird's peak portion IO appears.
本発明はSi基板の場合のみならず絶縁体あるいは絶縁
膜上のS1単結晶膜基板の如く、いわゆるS OI (
Silicon On In5ulator)構造にも
適用できることは云うまでもない。The present invention applies not only to Si substrates but also to so-called SOI (S1 single crystal film substrates on insulators or insulating films).
Needless to say, the present invention can also be applied to a silicon on inductor structure.
[発明の効果]
本発明により、半導体装置の製造方法に関し、トレンチ
・アイソレーションとLOGOSアイソレージ3ンの併
用によって細いアイソレーションと大面積を要する部分
のアイソレージジンとをLOCOSアイソレーション端
部における異状な形状を現出させずに、又、簡単な工程
で容易に行なうことができる効果がある。[Effects of the Invention] According to the present invention, in a method of manufacturing a semiconductor device, by combining trench isolation and LOGOS isolation 3, thin isolation and isolation gin in a portion requiring a large area can be reduced to abnormalities at the ends of LOCOS isolation. This has the advantage that it can be easily carried out in a simple process without creating a strange shape.
第1図(a)〜(c)は本発明の一実施例を製造工程順
に示したものである。
l・・・Si基板
2・・・熱酸化5iOz膜(1)
3・・・埋め込みガラス
4・・・トレンチ・アイソレーション部5・・・熱酸化
5iOz膜(2)
6・・・S i x N 4膜
7・・・オーバー・ラップ部
8・・・LOCO3SiO□膜
9・・・素子部
10・・・バーズ・ピーク部
以上
出願人 セイコーエプソン株式会社FIGS. 1(a) to 1(c) show an embodiment of the present invention in the order of manufacturing steps. 1...Si substrate 2...Thermal oxidation 5iOz film (1) 3...Embedded glass 4...Trench isolation part 5...Thermal oxidation 5iOz film (2) 6...S i x N4 film 7...Overlap part 8...LOCO3SiO□ film 9...Element part 10...Birds peak part and above Applicant Seiko Epson Corporation
Claims (1)
トレンチ)が形成され、該溝内に CVDSiO_2膜や燐ガラス膜等を埋め込んだ、いわ
ゆるトレンチ・アイソレーションによる誘電体素子分離
領域を形成後、半導体基板表面の大面積にわたってアイ
ソレーシヨン領域を要する部分にいわゆるLOCOS(
LocalOxidationStructure)に
よるアイソレーシヨン領域を形成する事を特徴とする半
導体装置の製造方法。[Claims] Grooves (
After forming a dielectric element isolation region by so-called trench isolation, in which a CVDSiO_2 film, a phosphorous glass film, etc. is embedded in the trench, a large area of the semiconductor substrate surface requires an isolation region. The so-called LOCOS (
1. A method for manufacturing a semiconductor device, comprising forming an isolation region using a local oxidation structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7520088A JPH01246844A (en) | 1988-03-29 | 1988-03-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7520088A JPH01246844A (en) | 1988-03-29 | 1988-03-29 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01246844A true JPH01246844A (en) | 1989-10-02 |
Family
ID=13569315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7520088A Pending JPH01246844A (en) | 1988-03-29 | 1988-03-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01246844A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10593787B2 (en) | 2015-05-14 | 2020-03-17 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
-
1988
- 1988-03-29 JP JP7520088A patent/JPH01246844A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10593787B2 (en) | 2015-05-14 | 2020-03-17 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US10943997B2 (en) | 2015-05-14 | 2021-03-09 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
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