JPH01245617A - Gate array input cell - Google Patents

Abstract

PURPOSE:To prevent a short-circuit current from flowing in a transistor on which the signal is impressed even when an external input signal is in an unstable condition by providing a means with the output of the OR of an internal cell output signal and the external input signal as an internal cell input signal. CONSTITUTION:The title cell consists of diodes 2 and 3 and a resistance 1 for electrostatic protection, and P-channel transistors 4 and 5, N-channel transistors 6 and 7 and a driver 8 for driving to compose the OR. Since an input cell with the output of the OR of an internal cell output signal 11 and an external input signal 10 as an internal cell input 12 is built, the propagation of the external input signal 10 through the internal cell can be controlled by the internal cell output signal 11. Thus, even when the external input signal 10 is in the unstable condition, the condition is prevented from propagating to the inside and the short-circuit current can be prevented from flowing also inside the input cell to which the condition is inputted directly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semi-custom semiconductor integrated circuits, which are attracting particular attention among various semiconductor devices.

[Summary of the invention]

The present invention applies to a gate array in which input/output cells are arranged on the periphery of an integrated circuit and internal cells are arranged inside the input/output cells.
- By having an input cell whose internal cell input signal is the output of the logical sum of an internal cell output signal and an external input signal, 1. Even if the level of the external input signal is in an undefined state, the internal cell output signal allows A stable output at a certain fixed level is obtained.

2. It can be configured with OR or input cells, which was conventionally configured with internal cells.

It made things possible.

[Conventional technology]

In the case of a CMOS transistor, when the input signal is in an unstable state such as high impedance, the N-channel and P-channel transistors become conductive, and a short-circuit current flows from the positive power supply to the negative current through the transistors of both channels, resulting in current consumption. This will adversely affect the circuit, such as an increase in energy consumption and the resulting heat generation. Moreover, its output also becomes unstable.

Therefore, if there is a possibility that an unstable state may occur in the external input signal level, use an input cell with a pull-up resistor or pull-down resistor to avoid the unstable signal being input to the input cell. The method used is used.

[Problems that inventions aim to solve]

However, in the case of the conventional method of using an input cell with a 1-lua-tube resistor or a pull-town resistor, if a negative external input signal enters the input cell with a pull-up resistor, it will pass through the pull-up resistor and be connected to the positive power supply. Since a short-circuit current flows to the negative power supply of the external input signal, there is a problem in that it becomes a source of heat generation, power supply noise, etc. The present invention solves these conventional problems by prohibiting short-circuit current from flowing through the transistor to which the external input signal is applied, even when the external input signal is unstable. The purpose is to output a level signal.

[Means to solve the problem]

The gate array input cell of the present invention has a structure in which input/output cells are arranged at the periphery of an integrated circuit, and internal cells are arranged inside the input/output cells. It is characterized by having means for using the output of the logical sum as an internal cell input signal.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
The figure shows a chip configuration model of a conventional gate array. One pad corresponds to one input/output cell, the input/output cells are arranged at the periphery, and signal propagation to internal cells is uniquely determined by external input signals.

FIG. 3 is a model diagram of an input cell, which is configured so that it can be replaced by the master slice method, such as an input cell 32 with a pull-up resistor or an input cell 33 with a pull-down resistor, if necessary. has been done.

Figure 1 is a WJ construction schematic diagram and a model diagram of a special cell (hereinafter referred to as IBR) according to the present invention, which includes a diode 2.3 for electrostatic protection, a resistor 1, and a P channel for configuring a logical sum. It is composed of a transistor 4.5, an N-channel transistor 6.7, and a driving driver 8, and the above configuration is represented by a model 9.

The operation of the IBR will be explained below using the model diagram shown in FIG. When the signal 11 is "H", the output 12 always outputs "'H'" regardless of whether the external input signal 10 is "'H", "L", or in an unstable state. When the signal 11 is L''', the output 12 outputs the state of the external signal 10 as it is □.In other words, by switching the signal 11 between "H" and "L'°", the external input signal 10 can be sent to the internal cell. By controlling the propagation, even if 10 is in an unstable state, an unstable state is not outputted, and it is possible to prevent short-circuit current from flowing inside the IBR.

The I'B R is used as an input cell that serves as a data input terminal of a memory card, a circuit that has the function of inputting signals from a data bus such as a CPU, and controlling the propagation of external input signals depending on the internal state of the integrated circuit. Possible applications include.

〔Effect of the invention〕

In the present invention, an input sail is configured in which the output of the logical sum of an internal cell output signal and an external input signal is used as an internal cell input signal, so that internal cell propagation control of an external input signal is controlled by the internal cell output signal. Therefore, (1) Even if the external input signal is in an unstable state, it is possible to prevent that state from propagating internally, and also to prevent short-circuit current from flowing inside the input cell to which the state is directly input. Since this can be prevented, an increase in current consumption can be suppressed.

(2) The number of parts can be reduced because the input cell can be configured as a logical sum.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a schematic diagram and a model diagram of the structure of a cell according to the present invention. FIG. 2 is a chip configuration diagram of the gate array. FIGS. 3(a) and 3(b) are model diagrams of conventional input cells. 1...Resistor 2.3...Diode 4.5...P channel 1-Ransistallo, 7...
N channel 1 to transistor 8...driver 10...external input signal 11...internal cell output signal 12...input cell output signal 21... ...Input/output cell 22...Internal cell 31...Budzufer type input cell 32...
- Input cell with pull-up resistor 33... Input cell with pull-town resistor 34... Invert type input cell 35... Input cell with pull-town resistor 36
...Input cells with pull-up resistors and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masaharu Kamiyanagi (1 other person) qb) Cap 3

Claims (1)

[Claims] In a gate array that has a configuration in which input/output cells are placed on the periphery of an integrated circuit and internal cells are placed inside the input/output cells, the output of the logical sum of the internal cell output signal and the external input signal is used as the internal cell input signal. A gate array input cell characterized by having an input cell.