US20020027448A1 - Pull up/pull down logic for holding a defined value during power down mode - Google Patents

Pull up/pull down logic for holding a defined value during power down mode Download PDF

Info

Publication number
US20020027448A1
US20020027448A1 US09096489 US9648998A US2002027448A1 US 20020027448 A1 US20020027448 A1 US 20020027448A1 US 09096489 US09096489 US 09096489 US 9648998 A US9648998 A US 9648998A US 2002027448 A1 US2002027448 A1 US 2002027448A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
integrated circuit
mode
circuit
operation
output pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09096489
Other versions
US6448812B1 (en )
Inventor
Tommaso Bacigalupo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A circuit and a method for setting a digital potential at an integrated circuit output pin in which pull up/pull down circuitry holds a defined value at the output pin during the power down of the integrated circuit. A primary driver responsive to a state of the integrated circuit sets the output pin while the integrated circuit is in an active mode of operation, and secondary driver sets the output pin while the integrated circuit is in an inactive mode of operation. Control logic is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating a control signal relative to the state of the integrated circuit. The secondary driver logic is responsive to the control signal generated by the control logic and the state of the integrated circuit upon the change in the mode of operation of the integrated circuit from a powered up mode to a powered down mode for driving the output pin while the integrated circuit is in its inactive mode of operation.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field Of The Invention [0001]
  • The present invention relates to circuits and methods for setting a digital potential at an integrated circuit output and/or a bi-directional input/output pin, and more particularly to pull up/pull down circuitry which holds a defined value at the output and/or bi-directional input/output pin during the power down of the integrated circuit. [0002]
  • 2. Description Of The Related Art [0003]
  • Presently many integrated circuits (ICs) are provided with capabilities for entering a power-down mode in order to save energy during phases of inactivity. During inactive power down modes, the output and/or bi-directional input/output pins of integrated circuits should keep their defined values, otherwise other parts of the system utilizing the integrated circuits may become corrupted. For example, random access memory (RAM) contents may be modified or even lost if the IC output pins in the system connected to RAM are allowed to change state during periods of inactivity. [0004]
  • On the other hand, it would be useful if the values kept at the output and/or bi-directional input/output pins of inactive integrated circuits may be allowed to be overwritten by other, perhaps active IC sections of a computer system. Thus, access to a device, e.g., RAM, may be achieved using connections to the powered down integrated circuit. [0005]
  • In conventional microprocessors however, the output drivers keep on driving the last value which was valid prior to entering the power-down mode. Typically this value cannot be overwritten, because normally, high current capacity output drivers are used for driving the prior valid value. Accordingly, it is then necessary to switch off the output completely before entering the power-down mode. If it is desired that the signal should be used by another active device during the power down mode of the inactive device, additional software must be provided for switching off an output driver prior to power down, and additional hardware may be required to keep a defined value on a circuit output pin which has been switched off. Accordingly, it would be desirable to provide logic for use with an integrated circuit pin for holding a defined value at that pin during a power-down mode. Additionally, it would be advantageous to hold the digital potential at the integrated circuit pin at either a current or last value driven prior to a power-down. [0006]
  • SUMMARY OF THE INVENTION
  • In a described embodiment, a circuit embodying the invention sets a digital potential at an integrated circuit output and/or bi-directional input/output pin in which pull up/pull down circuitry holds a defined value. Separate primary and secondary driver circuits set the output and/or bi-directional input/output pin when the integrated circuit is in particular modes of operation. Control logic is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating control signals relative to the state of the integrated circuit. The control logic is connected to pull-up and pull-down transistors of the secondary driver logic for pulling up and pulling down the output and/or bi-directional input/output pin. The second driver circuit transistors are of less current-sourcing capability than the primary inverter circuit for driving the output and/or bi-directional output/input pin while the integrated circuit is in its powered down mode of operation. [0007]
  • Briefly summarized, the present invention relates to a circuit and a method for setting a digital potential at an integrated circuit output and/or bi-directional input/output pin in which pull up/pull down circuitry holds a defined value at the output and/or bi-directional input/output pin during the power down of the integrated circuit. A primary driver responsive to a state of the integrated circuit sets the output and/or bi-directional input/output pin while the integrated circuit is in an active mode of operation, and secondary driver sets the output and/or bi-directional input/output pin while the integrated circuit is in an inactive mode of operation. Control logic is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating a control signal relative to the state of the integrated circuit. The secondary driver logic is responsive to the control signal generated by the control logic and the state of the integrated circuit upon the change in the mode of operation of the integrated circuit from a powered up mode to a powered down mode for driving the output and/or bi-directional input/output pin while the integrated circuit is in its inactive mode of operation.[0008]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other features, objects and advantages of the present invention will become readily apparent and understood upon consideration of the following detailed description and attached drawings, wherein: [0009]
  • FIG. 1 is a schematic diagram showing a logic inverter circuit; and [0010]
  • FIG. 2 illustrates pull up and pull down logic for holding a defined value during power down mode for use with primary inverter logic for driving the output pin in accordance with an embodiment of the present invention.[0011]
  • DETAILED DESCRIPTION OF THE INVENTION
  • Exemplary embodiments of the invention are illustrated in the accompanying drawings relating to circuit design techniques that may be employed in integrated circuits. One embodiment for a circuit for setting a digital potential according to the present invention provides logic at an integrated circuit output and/or bi-directional input/output pin, e.g., a parallel port pin of a microcontroller, for holding a defined value at that pin during a power down mode. As depicted in FIG. 1, a CMOS inverter [0012] 10 is shown as representing a conventional logic inverter circuit, including a p-channel field effect transistor 12 and a n-channel field effect transistor 14. As discussed further below, an input signal at the inverter input 16 is thus logic inverted at output 18. An additional input logic 17 and 19 coupled to transistors 12 and 14 is connected to a power down indication signal 42 discussed below, to disable the inverter 10 during power down. The inverter 10 thus provides for inversion of a digital potential, and a buffered signal output in accordance with the current-sourcing capabilities of transistors 12 and 14.
  • The driver [0013] 10 is provided as a primary driver in FIG. 2, which illustrates a circuit 20 for setting a digital potential at an integrated circuit output pin 22 using pull up/pull down logic described below for holding a defined value during an inactive or power down mode in accordance with the invention. Herein, the circuit 20 sets a digital potential at an integrated circuit output pin 22 in which pull up/pull down circuitry holds a defined value. The primary driver inverter 10 is responsive to a state, e.g., digital potential values driven at output pin 22, of the integrated circuit to set the output pin 22 while the integrated circuit is in an active mode of operation.
  • With reference to FIG. 1, the transistors [0014] 12 and 14 of the CMOS driver 10 may be enhancement-mode MOSFET devices. The source of the transistor 12 is connected to the positive terminal of the power supply (VDD), and the source of transistor 14 is connected to the negative terminal (e.g., electrical ground) of the power supply (Vss). In the described inverter circuit configuration, the drains and the gates of transistors 12 and 14 are coupled to input 16 through logic gates 17 and 19. A single power supply is used and the circuit operates satisfactorily for power supply voltages in the range of 3 to 18 Volts.
  • When the driver is enabled, with the power down indication signal [0015] 42 low, and the driver input 16 low (i.e., zero volts), transistor 14 will be off and transistor 12 will be on. In the absence of an external load, the current conducted by transistor 12 will be negligibly small (in the nanoamp range) and the power dissipation will be correspondingly small. The voltage drop across transistor 12 will be very small (a few millivolts) and the output high level (VOH) will be almost equal to VDD. In this state transistor 12 (the pull-up transistor) provides a low impedance between the output terminal and the positive supply VDD.
  • When the driver is enabled and the driver input [0016] 16 is high (i.e., VDD volts) transistor 14 will be on and transistor 12 will be off. The operation in this state is the complement of that described above, and the output low voltage (VOL) will be within a few millivolts of Vss. In this state the current-sinking capability of the inverter 10 is determined by the i-v characteristics of transistor 14 (the pull-down transistor). When the driver is disabled, on the other hand, the driver output 18 is not driven and floats in a high impedance state, to provide tristate capabilities.
  • Since the input resistances of a CMOS gate such as the described driver [0017] 10, are very high, a gate input left unconnected will float at an unknown voltage. Usually, however, leakage currents are such that the input devices enter the active mode, allowing large currents to flow and causing overheating to result. Accordingly it is important that spare gate inputs be connected to an appropriate local power supply pin or paralleled with another input (keeping in mind the effect of this on the gate-switching threshold.) As discussed, the embodiment described below provides useful output logic for setting the value of output pin 22, while allowing kept values to be overwritten to allow access to the integrated circuit during the inactive powered down mode.
  • In FIG. 2, a secondary driver circuit [0018] 24 sets the output pin 22 while the integrated circuit is in an inactive mode of operation. The secondary driver circuit 24 has a pull-up transistor 26 and a pull-down transistor 28. The first driver circuit 10 and the second driver circuit 24 are connected together as a wired OR output at the pin 22, providing a common point for the separate circuits such that the combination of their outputs results in an OR function, i.e., the point at which the circuits are wired together will be a logic true if either circuit feeding it is at the corresponding digital potential.
  • Control logic [0019] 30 which may be an integrated circuit decoder or a selector circuit for controlling the transistors 26 and 28. A selector circuit embodiment of the control logic 30 is provided in which current or last values for controlling the transistors 26 and 28 are determined from inputs to the control logic 30, as discussed below. Alternatively, the control logic 30 may generate control signals under program control using a microcontroller, programmable logic or the like. The control logic 30 thus is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating plural control signals 32 and 34 relative to the state of the integrated circuit. The control logic 30 is connected to the pull-up transistor 26 via control line 32 and to the pull-down transistor 28 via control line 34 for pulling up or pulling down the output pin 22. The secondary driver logic 24 thus is responsive to one or more control signals 32 or 34 generated by the control logic 30. Herein, the active mode is a powered up mode of operation and the inactive mode is a powered down mode of operation of the integrated circuit respectively, with the first driver logic primary driver circuit 10 being of sufficient current-sourcing capability to drive the output pin 22 while the integrated circuit is in its powered up mode of operation. The second driver circuit logic 24 provides pull up/down functions that can be used during normal operation, and has secondary inverter circuit transistors 26 and 28 of less current-sourcing capability than the primary inverter circuit 10 for driving the output pin 22 while the integrated circuit is in its powered down mode of operation, the circuit 10 being disabled during power down. Accordingly, the primary inverter circuit 10 has relatively strong transistors 12 and 14 for the active powered up mode of operation, while the secondary inverter circuit 24 has relatively weak transistors 26 and 28 for the inactive powered down mode of operation of the integrated circuit.
  • The pull up/down circuit control logic [0020] 30 takes advantage of several inputs that are used for generating signals 32 and 34. In particular, the current value 36 and the (inverted) last value 38 are provided as inputs to control 30. The selector logic of the control logic 30 uses the current value 36 or the last value 38 to control transistors 26 and 28 of the secondary inverter circuit in FIG. 2. Thus, representative values of the output pin 22 being driven by the primary driver circuit 10 during the power-up mode prior to the power-down mode as the integrated circuit enters the power-down mode of operation is provided for use with the control logic 30 receiving such values for generating the control signal relative to the state of the integrated circuit. In particular, the representative current value 36 and last value 38 may be used selectively depending on the mode of operation of the control 30. Herein, a pull-up/down (normal operation) mode indication 40 provides for the control 30 signal operating relative to the state of the integrated circuit, and further the mode indication 40 serves to enable and disable the controlling of the pull-up transistor 26 and the pull-down transistor 28 for driving the output pin 22. As indicated in the table below, the mode of the integrated circuit may be selected with the selector circuit for operation in a normal mode of operation wherein user has the choice of having a pull-up or pull-down function, or the power-down mode may be provided as either pulling to the current value 36 or alternatively the last value 38.
    Mode of IC Pull Up/Down Mode Description
    Normal operation Pull up or down or The user has the choice
    turned off depending on of having a pull up or
    the control signals pull down function or to
    “pull up/down” disable it.
    (Enabled or disabled in
    control logic 30)
    Power down Pull to current value or The current value of the
    pull to last value. pin will be driven by
    Selected by control logic 30 the pull up/down logic.
    The last value before
    entering power down will
    be driven by the pull
    up/down logic.
  • The power-down indication [0021] 42 provides a signal representative of the system state of the integrated circuit for the control 30. An input signal 46 to the control 30, provides the function of selecting during the last value or holding the current value during power down. Accordingly, the control 30 receives the signal indication representative of a power-down status for the system during the power-up mode prior to the power-down mode, which indication is used by the control logic 30 receiving the power-down indication 42 for generating the control signal relative to the state of the integrated circuit. An input driver 44, optionally employed with bi-directional input/output integrated circuit pads is shown in schematic form, also is coupled to pin 22 for receiving digital signals received at the integrated circuit.
  • The control logic [0022] 30 is provided as selector control logic described in a logic table, as follows:
    Signal Level Condition
    32 low (normal_operation AND
    pullup_function = true)
    OR
    (power_down AND drive_last_value =
    true AND inverted_last_value = low)
    OR (power_down AND hold_current_value =
    true AND current_value = high)
    32 high otherwise
    34 high (normal_operation AND pulldown_function =
    true) OR
    (power_down AND drive_last_value = true
    AND inverted_last_value = high) OR
    (power_down AND hold_current_value = true
    AND current_value = low)
    34 low otherwise
  • As discussed, the pull-up/down control [0023] 30 controls the operation of the weak pull-up/down transistors 26 and 28, such that the control 30 provides operation in accordance with the above described pull-up/down operation mode, or a combination of such modes of operation for use in the inactive power-down state of the integrated circuit. The pull-up/pull-down logic for holding the defined value during the power down mode may be used for microprocessors or other integrated circuits such as the Siemens C167 microprocessor output drivers keeping the last driven value active. The described pull-up/down transistors 26 and 28 may be provided as any pull-up/down elements such as a combination of switchable elements with a resistor depending upon the technology employed, e.g., BICMOS, CMOS, NMOS and the like.
  • Thus the described logic provides for a weak driver for a BUS HOLD function which may be responsive to external events to the integrated circuit device, such as setting the output pin [0024] 22 logic level with a second driver logic active device connected to the bus for generating control signals allowing the output pin 22 logic level to be overwritten by such external devices upon power-down of the integrated circuit. Thus a method for setting a digital potential at an integrated circuit device output pin 22 is described using the steps of driving output pin 22 with first driver logic responsive to a state of the integrated circuit when the integrated circuit is in its active mode of operation, driving the bi-directional input/output pin with second driver logic when the integrated circuit is in an inactive mode of operation, generating a control signal relative to the state of the integrated circuit in response to a change in the mode of operation of the integrated circuit from the active mode to the inactive mode, and then setting the output pin logic level with the second driver logic in response to the generated control signal and the state of the integrated circuit while the integrated circuit is in the inactive mode of operation.
  • The control signal generating step of the described method may further be used to generate control signals in response to an event external to the integrated circuit device, allowing the output pin logic level to be overwritten by external devices upon power down of the integrated circuit device. [0025]

Claims (21)

    What is claimed is:
  1. 1. A circuit for setting a digital potential at an integrated circuit output pin, comprising:
    first driver logic responsive to a state of the integrated circuit for driving the output pin while the integrated circuit is in an active mode of operation;
    second driver logic for driving the output pin while the integrated circuit is in an inactive mode of operation; and
    control logic responsive to a change in the mode of operation of the integrated circuit from said active mode to said inactive mode for generating a control signal relative to the state of the integrated circuit;
    said second driver logic being responsive to said control signal generated by said control logic and the state of the integrated circuit upon the change in the mode of operation of the integrated circuit from said active mode to said inactive mode for driving the output pin while the integrated circuit is in said inactive mode of operation.
  2. 2. A circuit as recited in claim 1, wherein said output pin comprises a bi-directional input/output integrated circuit pin.
  3. 3. A circuit as recited in claim 1, wherein said first driver circuit and said second driver circuit are connected together as a wired OR output to the output pin in the integrated circuit.
  4. 4. A circuit as recited in claim 1, wherein said active mode is a powered up mode of operation and said inactive mode is a powered down mode of operation of the integrated circuit respectively, said first driver logic comprising a primary driver with tristate capability of sufficient current-sourcing capability to drive the output pin while the integrated circuit is in the powered up mode of operation.
  5. 5. A circuit as recited in claim 4, wherein said second driver logic comprises a secondary driver circuit of less current-sourcing capability than said primary inverter circuit for driving the output pin while the integrated circuit is in the powered down mode of operation.
  6. 6. A circuit as recited in claim 5, wherein said primary circuit comprises relatively strong transistors for the powered up mode of operation, and said secondary circuit comprises relatively weak transistors for the powered down mode of operation of the integrated circuit.
  7. 7. A circuit as recited in claim 5, wherein said secondary comprises a pull-up transistor and a pull-down transistor, said control logic being connected to said pull-up transistor and to said pull-down transistor for driving the output pin while the integrated circuit is in the powered down mode of operation.
  8. 8. A circuit as recited in claim 5, wherein the state of the integrated circuit is representative of a value of the output pin being driven by said primary inverter during the powered up mode prior to the powered down mode as the integrated circuit enters the powered down mode of operation, said control logic receiving said value of the output pin for generating the control signal relative to the state of the integrated circuit.
  9. 9. A circuit as recited in claim 5, wherein the state of the integrated circuit is representative of a current value and a last value of the output pin being driven by said primary inverter during the powered up mode prior to the powered down mode as the integrated circuit enters the powered down mode of operation, said control logic receiving said current and last values for generating the control signal relative to the state of the integrated circuit.
  10. 10. A circuit as recited in claim 4, wherein the state of the integrated circuit is representative of a power down indication of the integrated circuit during the powered up mode prior to the powered down mode, said control logic receiving said power down indication for generating the control signal relative to the state of the integrated circuit.
  11. 11. A circuit as recited in claim 10, wherein said secondary inverter comprises a pull-up transistor and a pull-down transistor, said control logic being connected to said pull-up transistor and to said pull-down transistor for driving the output pin while the integrated circuit is in the powered down mode of operation.
  12. 12. A circuit as recited in claim 11, wherein said control logic generates plural control signals for controlling each of said pull-up transistor and said pull-down transistor for driving the output pin while the integrated circuit is in the powered down mode of operation.
  13. 13. A circuit as recited in claim 12, wherein the state of the integrated circuit includes a pull up/down mode indication, said control logic generating control signals relative to the state of the integrated circuit and said mode indication to enable and disable the controlling of said pull-up transistor and said pull-down transistor for driving the output pin.
  14. 14. A circuit as recited in claim 13, wherein the state of the integrated circuit is representative of a current value and a last value of the output pin being driven by said primary inverter during the powered up mode prior to the powered down mode as the integrated circuit enters the powered down mode of operation, said control logic receiving said current and last values for generating the control signal relative to the state of the integrated circuit.
  15. 15. A circuit as recited in claim 14, wherein said control logic is responsive to said pull up/down mode for generating control signals for controlling said pull-up transistor and said pull-down transistor for driving the output pin to either of said current and last values relative to the state of the integrated circuit.
  16. 16. A circuit for holding a defined value at an output pin during power down of an integrated circuit, comprising:
    means for driving the output pin with first driver logic responsive to a state of the integrated circuit when the integrated circuit is in an active mode of operation;
    means for driving the output pin with second driver logic when the integrated circuit is in an inactive mode of operation;
    means for generating a control signal relative to the state of the integrated circuit in response to a change in the mode of operation of the integrated circuit from said active mode to said inactive mode; and
    means for setting the output pin logic level with the second driver logic in response to said control signal generating means and the state of the integrated circuit while the integrated circuit is in said inactive mode of operation.
  17. 17. A circuit as recited in claim 16, wherein said active mode is a powered up mode of operation and said inactive mode is a powered down mode of operation of the integrated circuit respectively, said first driver logic comprising a primary circuit of sufficient current-sourcing capability to drive the output pin while the integrated circuit is in the powered up mode of operation.
  18. 18. A circuit as recited in claim 17, wherein said second driver logic comprises a secondary circuit of less current-sourcing capability than said primary inverter circuit for driving the output pin while the integrated circuit is in the powered down mode of operation.
  19. 19. A circuit as recited in claim 18, wherein said primary circuit comprises relatively strong transistors for the powered up mode of operation, and said secondary circuit comprises relatively weak transistors for the powered down mode of operation of the integrated circuit.
  20. 20. A method for setting a digital potential at an integrated circuit device output pin, comprising the steps of:
    driving the output pin with first driver logic responsive to a state of the integrated circuit when the integrated circuit is in an active mode of operation;
    driving the output pin with second driver logic when the integrated circuit is in an inactive mode of operation;
    generating a control signal relative to the state of the integrated circuit in response to a change in the mode of operation of the integrated circuit from said active mode to said inactive mode; and
    setting the output pin logic level with the second driver logic in response to the generated control signal and the state of the integrated circuit while the integrated circuit is in said inactive mode of operation.
  21. 21. A method as recited in claim 20, wherein said generating step generates the control signal in response to an event external to the integrated circuit device, said setting step setting the output pin logic level with the second driver logic in response to the generated control signal allowing the output pin logic level to be overwritten by external devices upon power down of the integrated circuit device.
US09096489 1998-06-11 1998-06-11 Pull up/pull down logic for holding a defined value during power down mode Expired - Lifetime US6448812B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09096489 US6448812B1 (en) 1998-06-11 1998-06-11 Pull up/pull down logic for holding a defined value during power down mode

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09096489 US6448812B1 (en) 1998-06-11 1998-06-11 Pull up/pull down logic for holding a defined value during power down mode
DE1999125374 DE19925374A1 (en) 1998-06-11 1999-06-02 Circuit for setting digital potential at digital IC output or bi-directional input/output pin

Publications (2)

Publication Number Publication Date
US20020027448A1 true true US20020027448A1 (en) 2002-03-07
US6448812B1 US6448812B1 (en) 2002-09-10

Family

ID=22257573

Family Applications (1)

Application Number Title Priority Date Filing Date
US09096489 Expired - Lifetime US6448812B1 (en) 1998-06-11 1998-06-11 Pull up/pull down logic for holding a defined value during power down mode

Country Status (2)

Country Link
US (1) US6448812B1 (en)
DE (1) DE19925374A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030028815A1 (en) * 2001-07-18 2003-02-06 Gregory Rose Power saving
US20030231635A1 (en) * 2002-06-18 2003-12-18 Kalkunte Suresh S. Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US20040071152A1 (en) * 1999-12-29 2004-04-15 Intel Corporation, A Delaware Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US20040085901A1 (en) * 2002-11-05 2004-05-06 Hooper Donald F. Flow control in a network environment
US20040186921A1 (en) * 1999-12-27 2004-09-23 Intel Corporation, A California Corporation Memory mapping in a multi-engine processor
US20060069882A1 (en) * 1999-08-31 2006-03-30 Intel Corporation, A Delaware Corporation Memory controller for processor having multiple programmable units
USRE41849E1 (en) 1999-12-22 2010-10-19 Intel Corporation Parallel multi-threaded processing
WO2011097116A3 (en) * 2010-02-04 2011-12-22 Carefusion 303, Inc. Inventory control device
US20130134942A1 (en) * 2011-11-29 2013-05-30 Atsushi Sakurai Charge/discharge control circuit and battery device

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10103052C1 (en) * 2001-01-24 2002-09-12 Infineon Technologies Ag Circuit for generating an asynchronous signal pulse
US7276939B2 (en) * 2003-01-20 2007-10-02 Renesas Technology Corp. Semiconductor integrated circuit
US20050270064A1 (en) * 2004-06-07 2005-12-08 Renesas Technology Corp. Semiconductor device
US7102380B2 (en) * 2004-07-07 2006-09-05 Kao Richard F C High speed integrated circuit
US7679396B1 (en) 2004-07-07 2010-03-16 Kao Richard F C High speed integrated circuit
US7196567B2 (en) * 2004-12-20 2007-03-27 Rambus Inc. Systems and methods for controlling termination resistance values for a plurality of communication channels
KR100666484B1 (en) * 2005-02-04 2007-01-09 삼성전자주식회사 Input/output circuit and input/output method of a semiconductor memory device
WO2007031937A3 (en) * 2005-09-12 2007-10-11 Nxp Bv Power management for buses in cmos circuits
KR20070069972A (en) * 2005-12-28 2007-07-03 동부일렉트로닉스 주식회사 Apparatus for controlling drive capacity in semiconductor integrated circuit devices
US20090259864A1 (en) * 2008-04-10 2009-10-15 Nvidia Corporation System and method for input/output control during power down mode
US8793091B2 (en) * 2008-04-10 2014-07-29 Nvidia Corporation System and method for integrated circuit calibration
US8570068B2 (en) 2010-04-28 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit for reducing negative bias temperature instability
US8564335B1 (en) * 2010-10-15 2013-10-22 Marvell International Ltd. Low power pad
CN103095278B (en) * 2010-12-02 2016-05-25 瑞昱半导体股份有限公司 Integrated circuit and its control method
US20130054997A1 (en) 2011-08-22 2013-02-28 Nvidia Corporation Method and Apparatus to Optimize System Battery-Life for Static and Semi-Static Image Viewing Usage Models
US9602101B2 (en) * 2013-10-07 2017-03-21 Microchip Technology Incorporated Integrated device with auto configuration
US9417640B2 (en) * 2014-05-09 2016-08-16 Macronix International Co., Ltd. Input pin control

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6234830U (en) * 1985-08-19 1987-02-28
US5063308A (en) * 1988-12-21 1991-11-05 Intel Corporation Output driver with static and transient parts
JP3118472B2 (en) * 1991-08-09 2000-12-18 富士通株式会社 Output circuit
JPH0879047A (en) * 1994-09-02 1996-03-22 Toshiba Corp Semiconductor integrated circuit and its manufacture
US5500611A (en) * 1994-09-30 1996-03-19 Cirrus Logic, Inc. Integrated circuit with input/output pad having pullup or pulldown
US5852579A (en) * 1997-06-19 1998-12-22 Cypress Semiconductor Corporation Method and circuit for preventing and/or inhibiting contention in a system employing a random access memory

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8316191B2 (en) 1999-08-31 2012-11-20 Intel Corporation Memory controllers for processor having multiple programmable units
US20060069882A1 (en) * 1999-08-31 2006-03-30 Intel Corporation, A Delaware Corporation Memory controller for processor having multiple programmable units
USRE41849E1 (en) 1999-12-22 2010-10-19 Intel Corporation Parallel multi-threaded processing
US9830284B2 (en) 1999-12-27 2017-11-28 Intel Corporation Memory mapping in a processor having multiple programmable units
US9824038B2 (en) 1999-12-27 2017-11-21 Intel Corporation Memory mapping in a processor having multiple programmable units
US9824037B2 (en) 1999-12-27 2017-11-21 Intel Corporation Memory mapping in a processor having multiple programmable units
US20040186921A1 (en) * 1999-12-27 2004-09-23 Intel Corporation, A California Corporation Memory mapping in a multi-engine processor
US8738886B2 (en) 1999-12-27 2014-05-27 Intel Corporation Memory mapping in a processor having multiple programmable units
US9830285B2 (en) 1999-12-27 2017-11-28 Intel Corporation Memory mapping in a processor having multiple programmable units
US9128818B2 (en) 1999-12-27 2015-09-08 Intel Corporation Memory mapping in a processor having multiple programmable units
US7751402B2 (en) 1999-12-29 2010-07-06 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US20040071152A1 (en) * 1999-12-29 2004-04-15 Intel Corporation, A Delaware Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US7254728B2 (en) 2001-07-18 2007-08-07 Intel Corporation Power saving circuit having a keeper stage to hold a signal line in a weakly held state
US7058827B2 (en) 2001-07-18 2006-06-06 Intel Corporation Power saving circuit has an input line coupled to an external host and a keeper to hold the line in a weakly held state
US20060179336A1 (en) * 2001-07-18 2006-08-10 Gregory Rose Power saving circuit having a keeper stage to hold a signal line in a weakly held state
US20030028815A1 (en) * 2001-07-18 2003-02-06 Gregory Rose Power saving
US20030231635A1 (en) * 2002-06-18 2003-12-18 Kalkunte Suresh S. Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US20040085901A1 (en) * 2002-11-05 2004-05-06 Hooper Donald F. Flow control in a network environment
US8508378B2 (en) 2010-02-04 2013-08-13 Carefusion 303, Inc. System and method for extending the battery life in inventory control devices
WO2011097116A3 (en) * 2010-02-04 2011-12-22 Carefusion 303, Inc. Inventory control device
US9142868B2 (en) * 2011-11-29 2015-09-22 Seiko Instruments Inc. Charge/discharge control circuit and battery device
US20130134942A1 (en) * 2011-11-29 2013-05-30 Atsushi Sakurai Charge/discharge control circuit and battery device

Also Published As

Publication number Publication date Type
US6448812B1 (en) 2002-09-10 grant
DE19925374A1 (en) 1999-12-16 application

Similar Documents

Publication Publication Date Title
US5589783A (en) Variable input threshold adjustment
US5534795A (en) Voltage translation and overvoltage protection
US4866304A (en) BICMOS NAND gate
US5661414A (en) Output circuit for use in a semiconductor integrated circuit
US4473758A (en) Substrate bias control circuit and method
US4472647A (en) Circuit for interfacing with both TTL and CMOS voltage levels
US4963766A (en) Low-voltage CMOS output buffer
US5187389A (en) Noise resistant low voltage brownout detector with shut off option
US5578941A (en) Voltage compensating CMOS input buffer circuit
US5444404A (en) Scan flip-flop with power saving feature
US5886561A (en) Backup battery switch
US4877978A (en) Output buffer tri-state noise reduction circuit
US6353346B1 (en) Apparatus and method for a programmable adaptive output driver
US5933021A (en) Noise suppression method and circuits for sensitive circuits
US6242948B1 (en) Semiconductor integrated circuit device
US6911860B1 (en) On/off reference voltage switch for multiple I/O standards
US6064226A (en) Multiple input/output level interface input receiver
US20020149392A1 (en) Level adjustment circuit and data output circuit thereof
US5995010A (en) Output buffer providing testability
US4754160A (en) Power supply switching circuit
US4556804A (en) Power multiplexer switch and method
US20010047506A1 (en) System and method for controlling current in an integrated circuit
US5448182A (en) Driver circuit with self-adjusting impedance matching
US4680487A (en) Input/output port including auxiliary low-power transistors
US5450025A (en) Tristate driver for interfacing to a bus subject to overvoltage conditions

Legal Events

Date Code Title Description
AS Assignment

Owner name: SIEMENS MICROELECTRONICS, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BACIGALUPO, TOMMASO;REEL/FRAME:009270/0285

Effective date: 19980610

AS Assignment

Owner name: SIEMENS AKTIENGESELLSCHAFT, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIEMENS MICROELECTRONICS, INC.;REEL/FRAME:009617/0846

Effective date: 19981020

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: INFINEON TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SIEMENS AKTIENGESELLSCHAFT;REEL/FRAME:026358/0703

Effective date: 19990331

FPAY Fee payment

Year of fee payment: 12