JPH01245616A - Gate array input cell - Google Patents

Abstract

PURPOSE:To prevent a short-circuit current from flowing in a transistor on which the signal is impressed even when an external input signal is in an unstable condition by providing a means with the output of the AND of an internal cell output signal and the external input signal as an internal cell input signal. CONSTITUTION:The title call consists of diodes 2 and 3 and a resistance 1 for electrostatic protection, and P-channel transistors 4 and 5, N-channel transistors 6 and 7 and a driver 8 for driving to compose the AND. Since an input cell with the output of the AND of an internal cell output signal 11 and an external input signal 10 as an internal cell input 12 is constituted, the propagation of the external input signal 10 through the internal cell can be controlled by the internal cell output signal 11. Thus, even when the external input signal 10 is in the unstable condition, the condition is prevented from propagating to the inside and the short-circuit current can be prevented from flowing also inside the input cell to which the condition is inputted directly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semi-order semiconductor integrated circuit, which has been attracting particular attention among various semiconductor devices.

[Summary of the invention]

The present invention provides an input cell in which an output of a logical product of an internal cell output signal and an external input signal is used as an internal cell input signal in a gate array in which input/output cells are arranged at the periphery of an integrated circuit and internal cells are arranged inside the input/output cells. By having: 1. Even if the level of the external input signal is in an undefined state, a stable output at a certain fixed level can be obtained by the internal cell output signal.

2. The logical product, which was conventionally made up of internal cells, can now be made up of input cells.

It made things possible.

[Conventional technology]

In the case of CM OS +- transistors, when the input signal is in an unstable state such as high impedance, the 1-run transistors of N and P transistors become conductive.
A short-circuit current flows from the positive power supply to the negative current through the transistors of both channels, which adversely affects the circuit, such as increased current consumption and associated heat generation. Moreover, its output also becomes unstable.

Therefore, if there is a possibility that an unstable state may occur in the external input signal level, use an input cell with a pull-up resistor or pull-down resistor to avoid a state in which unstable signals are input to the input cell. The method used is used.

[Problem to be solved by the invention]

However, in the case of using the conventional pull-up resistor or pull-town resistor 1-inch human power cell, if a negative external input signal enters the pull-up resistor, the positive power supply will pass through the pull-up resistor. Short-circuit current flows from the external input signal to the negative power supply, causing heat generation and
This has the problem of becoming a source of power supply noise.

The present invention solves these conventional problems by prohibiting short-circuit current from flowing in the 1-run sister to which the external input signal is applied, even when the external input signal is unstable. The purpose is to output a certain stable signal.

[Means to solve the problem]

The 1-input input cell of the present invention is a gate array having a configuration in which input/output cells are arranged at the periphery of an integrated circuit, and internal cells are arranged inside the input/output cells. It is characterized by having means for using the output of AND with a signal as an internal cell input signal.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
The figure shows a chip configuration model of a conventional gate array. One pad corresponds to one input/output cell, the input/output cells are arranged in the peripheral area, and signal propagation to internal cells is uniquely determined by an external input signal.

FIG. 3 is a model diagram of an input cell, which is constructed so that it can be replaced by a master slice method, such as a pull-azo resistor Ainu Kasel 32 or an input cell 33 with a pull-town resistor, if necessary. ing.

Figure 1 shows a structural schematic diagram and model diagram of a special cell (hereinafter referred to as IBA) according to the present invention, including a diode 2.3 for electrostatic protection, a resistor 1, and a p-7 for forming an AND. - It is composed of a transistor 4.5, an N-channel transistor 67, and a driving driver 8, and the structure shown in F is represented by a model 9.

The operation of the IBA will be explained below using the model diagram shown in FIG. When the signal 11 is ``L'', the output 12 always outputs ``L'' regardless of whether the external input signal 10 is ``H'', ``L'', or in an unstable state.When the signal 11 is ``H'' ′″
In this case, the output 12 outputs the state of the external signal 10 as is. In other words, by switching the signal 11 between ``H'' and ``L'', the propagation of the external input signal 10 to the internal cell is controlled, so that even if 10 is in an unstable state, the output will not be in an unstable state. There is no output, and it becomes possible for no short-circuit current to flow inside the IBA.

This FBA can be used to input signals from input cells that serve as data input terminals of memory cards, from data buses such as CPUs, and to circuits that have the function of controlling the propagation of external input signals based on the internal state of the integrated circuit. Possible applications.

〔Effect of the invention〕

In the present invention, since an input cell is configured in which the output of the logical product of an internal cell output signal and an external input signal is used as an internal cell input signal, internal cell propagation control of an external input signal can be controlled by the internal cell output signal. (1) Even if the external input signal is in an unstable state, the state can be prevented from propagating internally, and short-circuit current can also be prevented from flowing inside the input cell to which the state is directly input. , it is possible to suppress the increase in current consumption.

(2) Since logical products can be constructed using input cells, the number of parts can be reduced.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a schematic diagram and a model diagram of the structure of a cell according to the present invention. FIG. 2 shows the chip configurations of Goo 1 to Array. FIGS. 3(a) and 3(b) are model diagrams of conventional input cells. 1... Resistance -6-゛2.3... Diode 4.5... L-Lancistalo for Pchi A/Cine, 7...
・N channel 1-Runsistor 8...I pivot driver 10...External input signal 11...Internal cell output is one 12...Input cell output signal 21... ... Input/output cell 22 ... Internal cell 31 ... Buffered input cell 32 ...
- Input cell with pull-up resistor 33... Input cell with pull-town resistor 3.1... Invert input type input cell 35... Pull-up resistor [■ Input cell 36...・Put the pull-up resistor r=
To the above applicant: Seiko Epson Co., Ltd. agent Patent attorney Masaru Kamiyanagi (1st person) -7- (b) Yu 32

Claims (1)

[Claims] In a gate array that has a configuration in which input/output cells are placed on the periphery of an integrated circuit and internal cells are placed inside the input/output cells, the output of the logical product of the internal cell output signal and the external input signal is used as the internal cell input signal. A gate array input cell characterized by having an input cell.