JPH0124449B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a radio receiver, a television receiver,
Related to PLL (phase lock loop) devices for digital tuners used in other communication devices, etc.
Regarding PLL integrated circuits and control integrated circuits.

[Technical background of the invention]

For example, in a composite device that combines a digital tuner, a clock, and a timer, there is a PLL integrated circuit that has a built-in PLL circuit for a digital synthesizer, a control integrated circuit that has a function to control this, and a clock and timer function. may be separated. In such a case, conventionally, as shown in FIG. 1, the PLL integrated circuit 1 has a PLL circuit 2 and
For example, a crystal oscillation circuit 3 is built in to generate a comparison reference signal necessary for PLL operation, and the signal is generated from the oscillation frequency of the crystal oscillation circuit 3 (with built-in frequency divider circuit) from the frequency designation circuit 5 of the control integrated circuit 4. It supplies frequency control data and PLL frequency division data for selecting and specifying comparison reference frequencies.
This determines the output frequency of the PLL integrated circuit 1, making it possible to receive a desired frequency.
Further, the control integrated circuit 4 has a clock function other than the PLL function, for example, and the operating clock of the clock circuit 6 for this purpose is supplied from the crystal oscillation circuit 3 of the PLL integrated circuit 1. There is. Note that 7 is a crystal oscillator.

[Problems with background technology]

Incidentally, in the above-mentioned multifunction devices, only the clock and timer functions are often operated while reception is stopped. In this way, in the reception standby state, in the PLL integrated circuit 1, the PLL
Although this operation is not necessary, an oscillation operation is necessary to generate a reference clock necessary for the operation of the clock circuit 6 of the control integrated circuit 4. For this reason, it is necessary to supply operating power to the PLL integrated circuit 1 as well as the control integrated circuit 4, and the same current consumption is required in the reception standby state as in the reception operation. In other words, in the reception standby state, current consumption for unnecessary PLL operations was wasted.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
The present invention provides a PLL device for a digital tuner that can reduce current consumption in a reception standby state.

[Summary of the invention]

That is, in the PLL device for a digital tuner of the present invention, the PLL integrated circuit is not provided with an oscillation circuit for the PLL circuit, but the control integrated circuit is provided with an oscillation circuit, and the output signal of this oscillation circuit is used for control. Used as an operating clock for the integrated circuit, and used as the PLL integrated circuit for the PLL.
The present invention is characterized in that it is configured to be supplied as a comparison reference signal for a circuit.

Therefore, reception operation is possible by supplying operating power to each of the above two integrated circuits, and in the reception standby state, there is no need to operate the PLL integrated circuit, and only the control integrated circuit operates. The operation becomes possible by supplying power. In other words, in the reception standby state, there is no need to supply operating power to the PLL integrated circuit, making it possible to cut its current consumption.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a part of a digital tuner with an electronic clock, for example, and 11 is a PLL integrated circuit that functions as a PLL type digital synthesizer, and has a built-in PLL circuit 12.
Reference numeral 13 denotes a control integrated circuit, which includes a frequency specifying circuit 14 that generates frequency division data for specifying the output frequency of the PLL circuit 12 in accordance with an external frequency control input, and a clock circuit 15 and, for example, a crystal. It has a built-in oscillation circuit 16 (with built-in frequency dividing circuit). 17 is a crystal resonator connected externally.
The oscillation circuit 16 serves as an operating clock source for the control integrated circuit 13, and also serves as an operation clock source for the PLL integrated circuit 1.
A comparison reference signal is supplied to the PLL circuit 12 of No. 1.

Therefore, in the reception tuning operation of the digital tuner, if operating power is supplied to the two integrated circuits 11 and 13, the comparison reference signal is generated from the oscillation circuit 16.
The signal is supplied to the PLL circuit 12 to enable PLL operation. Then, the PLL is controlled by the frequency division data generated from the frequency specifying circuit 14 according to the frequency control input.
The output frequency of circuit 12 is set and the receive tuning frequency is selected by the frequency control input. In addition,
At this time, since the clock circuit 15 is also enabled, the clock function is also working.

On the other hand, in the reception standby state, the PLL integrated circuit 1
No operating power is supplied to the control integrated circuit 13.
Supply operating power only to the Therefore, although the clock function is performed by the operation of the oscillation circuit 16 and the clock circuit 15, the PLL integrated circuit 11 does not operate, so its current consumption is cut.

In other words, for digital tuners such as those mentioned above.
According to the PLL device, current consumption can be reduced in the reception standby state, and the unique function (clock function in this example) of the control integrated circuit 13 can be performed.

Note that even if a crystal oscillator circuit is provided in both the PLL integrated circuit 11 and the control integrated circuit 13, operating power is supplied only to the control integrated circuit during reception standby to operate the clock function, and the PLL Although the current consumption of the integrated circuit can be reduced, the number of parts used (such as a crystal resonator) increases, which is not preferable.

〔Effect of the invention〕

As mentioned above, for the digital tuner of the present invention
According to the PLL device, it is possible to cut the current consumption of the PLL integrated circuit in the reception standby state, and the specific functions of the control integrated circuit can be operated without any trouble, and the digital tuner, clock, etc. It can be conveniently applied to complex equipment.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a conventional PLL device for a digital tuner, and FIG. 2 is a configuration explanatory diagram showing an embodiment of a PLL device for a digital tuner according to the present invention. 11...PLL integrated circuit, 12...PLL circuit,
13... Control integrated circuit, 14... Frequency specification circuit, 15... Clock circuit, 16... Oscillation circuit.

Claims (1)

[Claims] 1. A PLL integrated circuit incorporating a PLL circuit, an oscillation circuit that provides a comparison reference signal to the PLL circuit, a frequency designation circuit that provides a frequency designation control signal to the PLL circuit, and a frequency designation circuit that provides a frequency designation control signal to the PLL circuit; and a control integrated circuit incorporating a clock function circuit that operates using the output. During reception operation, operating power is supplied to each of the two integrated circuits, and when operating the clock function circuit in a reception standby state, A PLL device for a digital tuner, characterized in that operating power is not supplied to the PLL integrated circuit, but operating power is supplied to the control integrated circuit.