JPH01243574A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a device isolation capacity from being lowered at a contact region by a method wherein a width in the short-piece direction of a semiconductor activation region is formed in such a way that a contact part used to make this region conductive is narrower than other parts. CONSTITUTION:In a semiconductor device where an activation region 11 has been formed in a semiconductor substrate 10, e.g., a DRAM, a width LSDG in the short-piece direction in the activation region 11 is formed in such a way that a contact part 15 used to make this region conductive is narrower than other parts. By this setup, even when, during formation of a contact, a dislocation of a contact region is caused on a part where a diffusion length of an impurity has been extended, it is possible to prevent a device isolation capacity from being lowered in the contact region without narrowing the width LSDG of the substrate activation region. Accordingly, it is possible to increase a driving capacity for a transistor and to increase a capacitance for a capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a structure for increasing the degree of integration thereof.

(Conventional technology) In recent years, demands for higher integration and higher performance in semiconductor integrated circuit devices have been increasing, and it is important to realize these demands using design rules and technology that are allowed by the process. It has become a challenge.

On the other hand, advances in contact formation technology have led to the direct contact method in which impurities are directly diffused from the polycrystalline silicon layer constituting the contact to form an active region, and the direct contact method in which impurities are diffused directly from the polycrystalline silicon layer constituting the contact, and silicon is selectively removed only from the contact portion in the active region. The 5EG (SSG) growth method and the like have been developed, and it has become possible to make contact with the semiconductor active region in one direction or in a completely self-aligned manner.

For example, a dynamic RAM (DRAM) has a width LSD as shown in FIG. The active region 1 is the element isolation interval. Bit lines (not shown) are formed in the upper layer of each active region 1 via contact portions 2, respectively. Further, a gate 3 is formed perpendicularly to the arrangement direction of the activation region 1 and constitutes a word line, and a capacitor plate 4 is formed on the right side of the gate 3 to conduct charge between it and the substrate activation region. configured to accumulate.

(Problem that Komei is trying to solve) By the way, when forming such a cell array, multiple contact technology is used, but how can such contact technology be used to create self-adhesion in the substrate activation area? Even if you try to form a contact in a specific manner, you have to take into account the misalignment Δa when forming the contact hole, and the element separation interval. There was a problem in that Lnin had to be larger than the minimum separation width Lnin in order to maintain the characteristics.

Furthermore, even if it were possible to eliminate the misalignment and make the misalignment Δa=O, with this contact technology, impurity diffusion would occur from the contact part to the substrate activation region, so The diffusion length of will become large. Therefore, the separation width LG in this region is 1
m ≧L 10 D Iun Δa+Δy.

However, in order to achieve high integration, the isolation width must be as small as possible, and the substrate active region width'SDG must be made as large as possible for reasons such as increasing the driving ability of the transistor or increasing the capacitance of the capacitor. There is. For example, a decrease in the area of a capacitor for storing and recording information means a decrease in accumulated charge, which may lead to problems such as destruction of memory information due to disturbances if memory information is read incorrectly.

As described above, even with the latest contact technology, the isolation width of the contact region must be larger than the minimum isolation width 'nin. There has been a conflicting problem between high integration and high performance, which leads to a decrease in performance.

In order to solve the problem that the area of the capacitor is inevitably reduced due to high integration, a MOS capacitor is stacked on the memory cell area, and one electrode of the capacitor is formed on the semiconductor substrate. A memory cell called a stacked memory cell has been proposed, which has a structure in which the capacitance Q of a MOS gapacitor is substantially increased by connecting one electrode of a MOS gapacitor to one electrode of a switching transistor.

This stacked memory cell is shown in FIGS. 10(a) and 10(a).
Figure (b) shows an example of the plan view (this figure shows a memory cell for 2 bits) and its A-AI! As shown in the li-plane view, M as a switching transistor is provided in one memory cell area separated by an element isolation insulating film 102 formed in a p-type silicon substrate 101.
In addition to forming an OSFET, a MOSFET is also formed on this upper layer.
The gate voltage of the MOSFET f! is in contact with the source or drain region 103 of the MOSFET. MOS as a switching transistor of 104a and adjacent memory cells
A capacitor is formed by sandwiching an insulating film 107 between a lower electrode 105 formed on the gate electrode 104b (word line) of the FET with an insulating film 109 interposed therebetween, and an upper electrode 106.

In such a configuration, although the capacitor area can be increased and the capacitance can be increased, the problem of the short distance between the contacts 108a and 108b of adjacent 2-bit memory cells remains unsolved, and the stored Information is easily lost in the punch-through between these two cells.

Further, the gate electrode 104a of the switching transistor of this memory cell has a different height from the gate electrode 104b (word line) of the switching transistor of the adjacent memory cell running on the element isolation insulating film 102, and the lower electrode 104a
A step is generated in the insulating film 109 formed prior to the formation of the insulating film 5. Therefore, a contact hole 110 is formed in the insulating film 109.
When forming a cell, dimensional accuracy may be reduced, and electrode material may remain along the side of the word 1104b (location A) due to etching such as reactive ion etching, which may cause the lower electrode to intersect between adjacent cells. Ta.

The present invention was made in view of the above-mentioned circumstances, and its purpose is to improve the reliability of highly integrated circuit devices including semiconductor active regions.

[Structure of the invention]

(Means for Solving the Problems) Therefore, in the present invention, in a semiconductor device in which a plurality of semiconductor activation regions are formed in a semiconductor substrate, the width of the semiconductor activation region in the short side direction is This is a contact portion for providing electrical conduction to the region, and is formed narrower than other portions.

(effect) According to the above configuration, the contact is accompanied by impurity diffusion.

When forming contacts using contact technology, even if the impurity diffusion length is increased and the contact area is misaligned,
Since the width of the semiconductor activation region in the short side direction is narrower in the contact portion for establishing conduction to the semiconductor activation region than in other portions, the substrate method a4b region L8,
6, it is possible to prevent the element isolation ability from decreasing in the contact 1- region. Therefore, the other substrate activation region width 'SDG can be made as wide as device isolation allows.

This means, for example, that a transistor can have a large driving capacity, and a capacitor can have a sufficiently large capacitance Q, and the performance of the element can be improved.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIGS. 1A to 1C are diagrams showing an example of an oven bit line type DRAM in which the present invention is applied to the memory cell region. Here, FIG. 1(a) and FIG. 1(b) are diagrams showing the AA cross section (bit line contact region) and the B-B cross section (one source/drain region) of FIG. 1(C), respectively. It is.

This DRAM has a width L in a p-type silicon substrate 10.
Activated regions 11 with a diameter of 1.0 μm are arranged at device isolation DG intervals, and a contact hole 12 with a size of 0.9×1.0 μm is formed in the upper layer of each activated region 11. The area width L is ΔL on both sides.
The SDG is narrowed by sDG=0.25 μm. The channel width is 1.0 μm.

Bit lines 15 are formed through these contact holes 12, respectively. Further, a gate 13 is formed perpendicularly to the arrangement direction of the active region 11, and constitutes a word line, and further to the right of the gate 13 is a capacitor plate 1.
4 is formed and configured to accumulate charge between the substrate activation region 11 and the substrate activation region 11 . Reference numerals 16a and 16b are a source and a drain, respectively, made of diffusion layers of opposite conductivity type. Furthermore, the first
Although the bit line 15 is omitted in FIG. 1C, the bit line is arranged in the longitudinal direction of the substrate activation region 11.

The same applies to the following examples.

Next, a method for manufacturing this DRAM will be explained.

First, in Fig. 2(a) and Fig. 2(b), A-A, B-
As shown in cross section B, an element made of a silicon oxide film is formed in the p-type silicon JJ temporary 10 by the usual method.
Once the region 17 is formed, the activation region 11 is then formed. Although not shown in this figure, a capacitor plate 14 constituting a capacitor is subsequently formed on this upper layer. And the transformer 71 gate 13 that constitutes the word line
is formed, and after surface oxidation of about 2,000 yen is performed, 4×10 13 cm −2 phosphorus ions are implanted at 30 KeV to form n − type sources and drains 16a and 16b.

Subsequently, as shown in FIGS. 3(a) and 3(b), an interlayer insulating film 18 is formed and a contact hole 12 is formed.

After depositing I[11,000 polycrystalline silicon ribs 15a, arsenic ion AS+ was applied at 50KeV, 5X10
Ion implantation is carried out using 15cIJ-2, and heat treatment is performed to diffuse impurities into the contact area to form an n'' layer and establish electrical connection with the active region 11. Note that instead of arsenic ion implantation, phosphorous Ion implantation may be used instead.Ion implantation into polycrystalline silicon is deep enough to reach the substrate interface and destroy the native oxide film.In addition to ion implantation, thermal diffusion of phosphorus into polycrystalline silicon is also performed. You can.

After this, in order to lower the resistance of the bit line, a film 8300 is applied.
A zero-layer molybdenum silicide layer Mo5i15b is deposited to form a polycide structure and patterned to complete the RAM as shown in FIG.

Here, in FIG. 1 (b>), if the diffusion length in the activation region 11 other than the contact portion is y, ~0.2 μm, then the distance L between the activation regions 11 separated by the element isolation region
1 is approximately O06 μm. On the other hand, in FIG. 1(a), the distance ML2 between the other active regions W1.11 separated by the element isolation region in the contact portion is approximately 0.6 to 0.7.
am, and Ll and Ll are approximately equal.

In this way, assuming that the element isolation interval is the minimum element isolation dimension, the active region width L8,6 is calculated by Δ on both sides and 5D.
Since G is narrowed by 0.25μm, if it is 0.1μ
Misalignment of about m and 5 μm at the contact part compared to y.
Even if the diffusion length increases by a certain degree, sufficient separation is possible.

Embodiment 2 Next, as a second embodiment of the present invention, a case where a contact is formed using silicon selective epitaxial growth technique (SEG) will be described.

In this DRAM, as shown in FIG. 4(a) to FIG. 4(C), a source or drain region 1 is used as a contact.
A silicon layer 21 selectively epitaxially grown on the surfaces of 6a and 16b is used, and although the cross-sectional view is different, the plane is exactly the same as the first embodiment shown in FIG. 1(C), and each Since the dimensions of the area and each part are the same, a description thereof will be omitted.

Here, Fig. 4(a) and Fig. 4(b) are respectively Fig. 4(a) and Fig. 4(b).
A-AIIIi side view and CC sectional view of C) are shown.

In manufacturing, first, as shown in FIG. 5(a) (A-Aai plane) and FIG. 5(b) (C-C cross section), a silicon oxide film is formed in the p-type silicon substrate 10 by a normal method. In addition to forming the element valve U region 17, the activation region 11 is also formed. Although not shown in this figure, there is a capacitor plate 1 forming the ′+ capacitor in the upper layer.
form 4.

Then, a transfer gate constituting a word line is formed, but here, after depositing a polycrystalline silicon layer 19a to a thickness of 4000, silicon oxide l1i19b of WAJi7300OA is further deposited by the CVD method, and both are patterned. Create a layered structure.

Then, as in the previous embodiment, n' type sources and drains 16a and 16b are formed by impurity diffusion.

Subsequently, as shown in FIGS. 6(a) and 6(b), a silicon oxide film 20 is further deposited by the CVD method, and then the entire surface is anisotropically etched by reactive ion etching etc. to form the gate. After forming a contact region in a self-aligned manner in the activation region 11 (CVOMI film sidewall leaving step in which a silicon oxide gap 20 is left only on the sidewall), phosphorus or arsenic is added to the concentration in this contact region by the SEG method. A doped silicon layer 21 is grown. Note that this silicon layer 21 also extends onto the element isolation film 17, but on the element isolation film 17 it becomes a silicon layer 21' with poor crystallinity.

Further, an interlayer insulating film 18 is formed, a contact hole 12' is opened therein, and an aluminum wiring layer pattern 2 is formed.
2 to complete the RAM as shown in FIG.

Here, in FIGS. 4(a) and 4(b), a silicon layer 21 is formed in the contact region by the SEG method.
contains a high concentration of impurities, so the diffusion length in the contact region is further extended.

However, since the active region width in the contact region is narrowed, the distance L between the diffusion layers under the element isolation region
3 is approximately 1.0 μm, and sufficient element isolation is possible.

Embodiment 3 Next, as a third embodiment of the present invention, an example of application to a stacked memory cell will be described.

This +Fill type memory is adjacent to the gate electrode 104a (word line) of the MOSFET, as shown in FIG. 7(a) and FIG. The lower type ff1105 of the capacitor made of polycrystalline silicon doped with a high concentration of impurities is formed on the gate electrode 104b (word line) of the MOSFET as a switching transistor of a memory cell via an insulating film 109, and is a MOS FET. At the contact portion that contacts the n-type source or drain region 103, the width in the short side direction of the memory cell region (activation region) isolated by the device isolation insulating film 102 is the same as the width in the short side direction of the region other than the contact portion. It is formed to be smaller than the width in the side direction.

Further, the width of the active region is reduced at the contact portion and widened under the pass gate electrode 104b of the switching transistor of the memory cell.

The other parts are the same as the stacked memory cell shown in FIG. Identical parts are given the same reference numerals.

With such a configuration, not only can the area of the capacitor be increased and the capacitance can be increased to improve performance, but also the distance between the contacts 108a and 108b of adjacent 2-bit memory cells can be shortened. However, since the memory cell region (activation region) is formed so that the width in the short side direction is smaller than the width in the short side direction of the area other than the contact portion, misalignment of the contact ball may occur. Even if punch-through occurs, it is possible to obtain a highly reliable stacked memory without punch-through between adjacent memory cells.

Further, since the activation region partially overlaps with the gate electrode 104b (word line) of the switching transistor of the adjacent memory cell, the gate electrode 104a and the gate electrode 104b are at the same level around the contact. . Therefore, contact hole 1 to insulating film 109
Position control when forming 10 becomes easier, and it becomes possible to further improve reliability.

FIG. 7(C) shows a modified example in which a pad electrode doped with impurities is provided in the bit line contact portion in the same process as the lower electrode 105 of the capacitor. Note that in the examples shown in FIGS. 7(a) to (C), the width of the active region in the contact portion of the capacitor is made narrower than in other regions.
Dots even on the bit line contacts! As shown in IC, the width of the activated region may be made narrower than other regions.
This further improves reliability.

Embodiment 4 Next, as a fourth embodiment of the present invention, a trench type DRAM will be described.
An example of its application will be explained.

Figure 8(a) and Figure 8(b) are respectively Figure 8(C)
FIG. 2 is an AA sectional view and a BB sectional view.

In the trench type memory cell, deep grooves V several μm deep are placed at predetermined intervals in a P-type silicon substrate 40 next to an n+ type source or drain region 43a, and a trench V is formed on the side wall of the groove V. Silicon oxide WA46 and a polycrystalline silicon plate electrode 47 embedded in a groove constitute a capacitor, and although it occupies a small area on the silicon substrate surface, the capacitor area is large and the capacitor is large.
can be made large, but in this example,
At the contact portion of the bit line 50 to the drain or source region [43b of the MOSFET], the width of the element region 41 separated by the element isolation WA42 is made smaller than the width of the element region in other regions. Here, the bit line 50 is in contact with the n-type drain or source region 43b via a pad portion 50a made of polycrystalline silicon doped with impurities at a high concentration. Further, 44 is a word line. 47 is an n-layer. Further, W indicates a contact portion between the pad electrode and the bit line.

With such a configuration, not only can the capacitor area be increased and the electrostatic capacitance be increased, resulting in higher performance, but also the distance between the contacts of adjacent 2-bit memory cells is small. Since the memory cell region (activation region) is formed so that its width in the short side direction is smaller than the width in the short side direction of the area other than the contact area, the diffusion length in the contact area is further extended. However, it is possible to obtain a highly reliable stacked memory without punch-through between adjacent memory cells.

Furthermore, in the above embodiments, CVD is used as the interlayer insulating film.
In the case of using a BPSG film formed on top of 5i02 by the method, phosphorus in the BPSG film invades the contact portion during various subsequent thermal processes, further deepening the diffusion layer. However, according to the present invention, these 15 are relaxed.

In the above embodiments, the source/drain regions are of n- type, but it is also effective to make them of n+ type.

Implantation of impurities after forming a contact hole not only lowers the contact resistance, but also, for example, if the contact straddles the field, the field oxide film will be etched and retreated during the contact forming process, so it will not work at the corner of the semiconductor active region. This is also because additional impurity implantation is required after forming the contact hole to prevent the junction from being exposed.

〔Effect of the invention〕

As described above, according to the present invention, in a semiconductor device in which a semiconductor activation region is formed in a semiconductor substrate, the width of the semiconductor activation region in the short side direction is set to be electrically conductive to the semiconductor activation region. Since the contact area is narrower than other areas, even if the diffusion length in the contact area increases or the position of the contact area shifts, the element isolation ability in the contact area will decrease. can be prevented. Therefore, the other substrate activation region widths are:
Element isolation can be made as wide as possible, and high performance and reliability are achieved.

[Brief explanation of the drawing]

Figures 1(a) to 1(C) are diagrams showing a memory cell according to the first embodiment of the present invention, Figures 2 to 3 are manufacturing process diagrams of the same memory cell, and Figure m4(a). 4C to 4C are diagrams showing a memory cell of the second embodiment of the present invention, FIGS. 5 to 6 are manufacturing process diagrams of the same memory cell, and FIGS. b) is a diagram showing a stacked memory cell according to the third embodiment of the present invention, FIG. 7(C,) is a diagram showing a modification of the third embodiment, and FIGS. 8(a) to 8. (C) is the fourth aspect of the present invention.
FIGS. 9 and 10 are diagrams showing a conventional memory. DESCRIPTION OF SYMBOLS 1...Activation region, 2...Contact part, 3...
Gate, 4... Ki1shibashita plate, 101...
P-type silicon substrate, 102... element isolation insulating film, 1
03... Source region, 104a, 104b... Gate electrode, 105... Lower electrode, 106... Upper electrode, 107... Insulating film, 108a, 108b... Contact 109... Insulating film , 110... contact hole, 10... p-type silicon substrate, 11... active region, 12... contact hole, 13... gate, 14... capacitor plate, 15... bit Line, 16a...source, 16b...drain, 17.
...Element isolation film, 18...Interlayer insulating film, 19a...
Polycrystalline silicon layer, 19b... silicon oxide film, 20
. . . Silicon oxide film, 21 . . . Highly doped silicon layer, 40 . . Silicon substrate, 41 . ...Drain region, 44...Word line,
46...Silicon oxide film, 50...Bit line, 50
a... Pad part. Figure 1 (c) Figure 2 ((1) Figure 2 (b) Figure 3 (0)
Figure 3 (b) Figure 5 (b) Figure 6 (b) Figure 7 (G) Figure 7 (b) Figure 8 (G) Figure 8 (b) Figure 8 (C
? 08b Figure 10(b)

Claims (1)

[Claims] In a semiconductor device in which a plurality of semiconductor activation regions are formed by separating the inside of a semiconductor substrate by an element isolation region, the width of the semiconductor activation region in the short side direction is defined as the semiconductor activation region. A semiconductor device characterized in that a contact portion for establishing electrical conduction in a region is formed narrower than other portions. (2) Claim (2) characterized in that the width of the semiconductor active region is formed narrower than the channel width at the contact portion.
1) The semiconductor device described. (3) The semiconductor device according to claim (1), wherein the semiconductor device is applied to a bit line contact of a dynamic RAM. (4) The semiconductor device according to claim (1), wherein the semiconductor device is applied to a lower capacitor contact of a stacked dynamic RAM.