JPH01243570A - High-resistance element - Google Patents

High-resistance element

Info

Publication number
JPH01243570A
JPH01243570A JP7128588A JP7128588A JPH01243570A JP H01243570 A JPH01243570 A JP H01243570A JP 7128588 A JP7128588 A JP 7128588A JP 7128588 A JP7128588 A JP 7128588A JP H01243570 A JPH01243570 A JP H01243570A
Authority
JP
Japan
Prior art keywords
film
psg film
resistance element
resistor
part electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7128588A
Other languages
Japanese (ja)
Inventor
Minoru Yokozawa
横澤 実
Hiroshi Kawaguchi
浩 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7128588A priority Critical patent/JPH01243570A/en
Publication of JPH01243570A publication Critical patent/JPH01243570A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a stable high-resistance element by a method wherein a thin film of a mixture of an oxide of silicon and an oxide of phosphorus or boron is used as a resistor. CONSTITUTION:A gate metal becomes a lower-part electrode 4 of a resistor which is formed in future. A PSG film 3 of a definite mol concentration of P2O2 is formed by an existing CVD method. The PSG film 3 is patterned. During this process, the PSG film 3 between an upper-part electrode 2 and the lower- part electrode 4 becomes a resistor. When the mol concentration of P2O2 in the PSG film 3, a thickness of the PSG film 3 and a pattern size are set as variable factors, a desired resistance can be obtained. By this setup, a stable high-resistance element can be obtained.

Description

【発明の詳細な説明】[Detailed description of the invention]

〔産業上の利用分野1 本発明は半導体集積回路内で用いられる高抵抗素子に関
する。 〔発明の概要] 本発明は、従来半導体集積回路内で絶縁体として用いら
れていた。シリコン酸化物とリンあるいはボロンの酸化
物との混合物薄膜−以下、リンガラス膜(PSGII)
あるいはボロンガラス膜(BSG膜)−の、混合比率を
制御することにより、所望の抵抗の抵抗体として用いる
事を特徴としている。
[Industrial Application Field 1] The present invention relates to a high resistance element used in a semiconductor integrated circuit. [Summary of the Invention] The present invention has conventionally been used as an insulator in semiconductor integrated circuits. Mixture thin film of silicon oxide and phosphorus or boron oxide - hereinafter referred to as phosphorus glass film (PSGII)
Alternatively, by controlling the mixing ratio of a boron glass film (BSG film), it can be used as a resistor with a desired resistance.

【従来の技術】[Conventional technology]

CCMOS−5RAを製造するに際し、一般にメモリセ
ルは4個のMO3型トランジスタと2個の高抵抗素子よ
り構成される。これらは搬纏であり、およそ1.OX5
.Oμm’の大きさを持つ、製造方法としては、半導体
基板の一主面の絶縁膜上に多結晶シリコン膜を堆積し、
フォトエツチングによりパターン加工して形成するのが
一般である。
When manufacturing CCMOS-5RA, a memory cell is generally composed of four MO3 type transistors and two high resistance elements. These are carriers and are approximately 1. OX5
.. As a manufacturing method, a polycrystalline silicon film is deposited on an insulating film on one main surface of a semiconductor substrate, and
It is generally formed by pattern processing using photoetching.

【発明が解決しようとする課Ill 先の多結晶シリコン膜はCVD法を用いて形成されるが
、抵抗率は原料ガスの不純物量により決定され安定性に
欠ける。さらに、この高抵抗素子は、多結晶シリコン膿
故膜中に拡散される水素の −−影響を受は不安定とな
る。このことは、0MO3−3RAMにおいては、主要
特性である消費電流(IDDS)を制御して製造するこ
とが難しいことを示す。そこで、本発明の目的は安定し
た高低抗素子を提供することである。 【課題を解決するための手段] 本発明は、PSG膜あるいはBSGIIを高抵抗素子と
して用いることによりかかる不具合点を解消した。 【実 施 例】 以下、本発明の実施例を示す、先づ既存の方法により、
半導体基板の一主面にMOS型半導体集積回路のゲート
形成であるゲート金属−一般にはドナーまたはアクセプ
タ不純物をドープしたポリシリコンあるいは該ポリシリ
コンと高融点金属との化合物−のパターン加工までを行
なう、ここでゲート金属は、将来形成される抵抗体の下
部電極となる0次に既存のCVD法により、一定のP2
O、モル濃度で、PSG膜を形成する。その後、既存の
フォトエツチングにより該PSG膜をパターン加工する
。さらに、該パターンの上にCVD絶縁膜を形成し、該
PSGIIIの真上の該CVD絶縁膜をフォトエツチン
グにより、コンタクト穴を明ける。その後、将来の抵抗
体の上部電極としての、キャリヤー不純物をドープされ
たポリシリコンあるいはアルミニューム膜を形成し、パ
ターン加工する。このとき、上部電極と下部電極の間の
PSGPI4が抵抗体となる。PSG#のP2O5モル
濃度を4モル%とし、膜厚な1000人とする。さらに
パターンサイズを、2.5X2゜5μm Oとすると、
得られる抵抗は10”Ω(5PA□5v)である、この
様に、P2O5モル濃度、PSG膜厚、パターンサイズ
を変量要因とすることにより、所望の抵抗が得られる。 PSGIIの形成方法において、S、O,のCVD膜に
、!1p*あるいは11B+を選択的にイオン注入し、
熱アニールする方法は容易に推察される。 [発明の効果] 以上の様に、本発明により安定した高抵抗素子が得られ
る。
Problems to be Solved by the Invention Although the polycrystalline silicon film described above is formed using the CVD method, the resistivity is determined by the amount of impurities in the source gas and lacks stability. Furthermore, this high resistance element becomes unstable due to the influence of hydrogen diffused into the polycrystalline silicon impurity film. This indicates that it is difficult to manufacture OMO3-3RAM by controlling its main characteristic, current consumption (IDDS). Therefore, an object of the present invention is to provide a stable high-low resistance element. [Means for Solving the Problems] The present invention solves these problems by using a PSG film or BSGII as a high resistance element. [Example] Hereinafter, an example of the present invention will be described, first by an existing method.
Patterning of gate metal (generally polysilicon doped with donor or acceptor impurities or a compound of polysilicon and a high melting point metal) for forming a gate of a MOS type semiconductor integrated circuit on one main surface of a semiconductor substrate; Here, the gate metal, which will become the lower electrode of the resistor that will be formed in the future, is made with a constant P2 by the existing CVD method of zero order.
A PSG film is formed at a molar concentration of O. Thereafter, the PSG film is patterned using conventional photoetching. Further, a CVD insulating film is formed on the pattern, and a contact hole is formed by photoetching the CVD insulating film directly above the PSGIII. Thereafter, a polysilicon or aluminum film doped with carrier impurities is formed and patterned to serve as the upper electrode of a future resistor. At this time, the PSGPI4 between the upper electrode and the lower electrode becomes a resistor. The P2O5 molar concentration of PSG# is 4 mol%, and the film thickness is 1000. Furthermore, if the pattern size is 2.5×2゜5μm O,
The resistance obtained is 10"Ω (5PA□5v). In this way, the desired resistance can be obtained by using the P2O5 molar concentration, PSG film thickness, and pattern size as variable factors. In the method for forming PSGII, Selective ion implantation of !1p* or 11B+ into the S, O, CVD film,
The thermal annealing method can be easily deduced. [Effects of the Invention] As described above, a stable high resistance element can be obtained by the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、高抵抗素子の断面構造を示す図。 第2図は、PSGIII100O人、パターンサイズ2
.5X2.5um”での、P −Osモル濃度と抵抗の
関係を示す図。 lはパシベーション膜、2は上部電極、3はPSG膜、
4は下部電極、5はフィールド膜、6はシリコン基板、
7は眉間絶縁膜、8は上部電極端子、9は下部電極端子
。 以上 出願人 セイコーエプソン株式会社 第1図 Oユ       今       6      8
Pa Or tlLZ 第2図
FIG. 1 is a diagram showing a cross-sectional structure of a high resistance element. Figure 2 shows PSGIII 100 people, pattern size 2.
.. A diagram showing the relationship between P-Os molar concentration and resistance at 5x2.5um". l is the passivation film, 2 is the upper electrode, 3 is the PSG film,
4 is a lower electrode, 5 is a field film, 6 is a silicon substrate,
7 is an insulating film between the eyebrows, 8 is an upper electrode terminal, and 9 is a lower electrode terminal. Applicant: Seiko Epson Co., Ltd. Figure 1 Oyu Now 6 8
Pa Or tlLZ Figure 2

Claims (1)

【特許請求の範囲】[Claims]  シリコン酸化物と、リンあるいはボロンの酸化物との
混合物薄膜を抵抗体として用いたことを特徴とする高抵
抗素子。
A high resistance element characterized by using a thin film of a mixture of silicon oxide and phosphorus or boron oxide as a resistor.
JP7128588A 1988-03-25 1988-03-25 High-resistance element Pending JPH01243570A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7128588A JPH01243570A (en) 1988-03-25 1988-03-25 High-resistance element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7128588A JPH01243570A (en) 1988-03-25 1988-03-25 High-resistance element

Publications (1)

Publication Number Publication Date
JPH01243570A true JPH01243570A (en) 1989-09-28

Family

ID=13456278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7128588A Pending JPH01243570A (en) 1988-03-25 1988-03-25 High-resistance element

Country Status (1)

Country Link
JP (1) JPH01243570A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10985237B2 (en) 2019-03-15 2021-04-20 Toshiba Memory Corporation Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10985237B2 (en) 2019-03-15 2021-04-20 Toshiba Memory Corporation Semiconductor device
US11574994B2 (en) 2019-03-15 2023-02-07 Kioxia Corporation Semiconductor device

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