JPH01243461A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To equalize the coupling capacitance of word lines and data lines by crossing split word lines in the coupling sections of the split word lines and the word lines and bonding the memory cells of one and the other of the memory cells sharing a drain region with the split word lines, the word lines, in the same number or approximately the same number. CONSTITUTION:One and the other of memory cells sharing a drain region in a MOSFET for selecting addresses are bonded with adjacent split word lines in the same number or approximately the same number by crossing split word lines in the coupling sections of the split word lines DWLa1-DWLas+1, DWLb1-DWLbs as word lines WLa, WLb. Consequently, when the title device is viewed by one split word lines, the word lines WLa, WLb, the change of coupling capacitance is offset, and coupling capacitance among each data line DL and adjacent word lines WLa, WLb is brought to approximately the same electrostatic capacitance. Accordingly, array noises are suppressed, and a reading margin is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a dynamic RAM (random access memory), and in particular to a one-element dynamic memory consisting of an information storage capacitor and an address selection MOSFET. The present invention relates to a technique effective for use in a semiconductor integrated circuit device equipped with a dynamic RAM using cells.

[Conventional technology]

As the memory capacity of dynamic RAM increases,
As the chip size of semiconductor substrates increases, distributed resistance of word lines formed of polycrystalline silicon or the like has become a problem. A method to solve this problem is to divide the word line into appropriate lengths to form divided word lines, and to connect these divided word lines to a word line formed by an aluminum layer with relatively high conductivity. The A1 shunt method, for example, was introduced in February 1983 by
5ESSION-XVI of ISSCC) Academic Journal (Tigest Op Technical Papers), pp. 226-227
It is written on the page.

[Problem to be solved by the invention]

An example of the A1 shunt method is shown in FIG. In the same figure, divided word lines DWLal to DWLas and DWLbl to D
WLba is provided, and these divided word lines are coupled to word lines WLa and WLb arranged in corresponding rows, respectively. Divided word lines DWL a 1 to DWL a
a and DWLbl~]) WLbs includes MOSFs for selecting addresses of a plurality of memory cells arranged in the corresponding row.
The gates of ET are coupled. This dynamic mRAM
Now, by sharing the drain region of the address selection MOSFET in two adjacent memory cells,
We are trying to make the layout more efficient. However, the inventors of the present invention have found that when such A1 shunt method is used, there are the following problems. That is, in order to further increase the capacity of the dynamic RAM and to further increase the integration of the memory array section, it is necessary to reduce the area occupied by the memory cells. However, the reduction in the occupied area of the information storage capacitor is limited in terms of securing its capacitance. Therefore, a method is adopted in which two memory cells that share a drain region are arranged as close as possible to reduce the area occupied by the address selection MOSFET. In this case, since the shared drain region, data, and WDL cannot be directly coupled, as shown in the A-B cross-sectional view of FIG. 6 shown in FIG. Address selection MO located in
A bonding pad Pa is provided for coupling the shared drain region of the SFET and the data mDL. .

Since these bonding pads and divided word lines are formed by overlapping their layout patterns, there is a coupling capacitance C between pad Pa, that is, data NDL, and divided word 1DWLa or DWLb, that is, word line WLa or WLb.
fl or Cf2 is present. These joint parts 1cfl,
The capacitance of Cf2 changes due to mask misalignment between the divided word line and the bonding pad in the data line direction when forming an integrated circuit, and as the mask misalignment becomes large, the capacitance of one coupling capacitance decreases and the capacitance of the other coupling capacitance decreases. The electrostatic capacitance of the coupling capacitance becomes large.

On the other hand, all memory cells coupled to the same divided word line exhibit similar changes. Therefore, as shown in FIG. 6, divided word lines DWLa 1 to DWLa
s and DWL b 1-DWL b a to the words "#WLa and WLb on the same side, and MO for address selection
When one of the memory cells that share the drain region of the SFET is coupled to the same word group, the change in coupling capacitance due to mask misalignment between the bonding pad and the divided word line will remain the same as the coupling between the word line and the data line. This results in a change in capacity.

If the coupling capacitance of one word line becomes larger than a certain level due to this bias in coupling capacitance, the level change of the data line according to the data stored in the memory cell selected by the word line selection operation will be caused by the coupling capacitance. It is transmitted to the selected word line as array noise. As a result, the address selection MOSFET of the unselected memory cell connected to the unselected word line is erroneously put into a weak on state, reducing the read margin and the information product capacity of the memory cell that is erroneously turned on. There is a risk that the storage data may be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM that prevents array noise caused by uneven coupling capacitance between word lines and data lines and improves read margin.

The above and other objects and novel features of this invention include:
It will become clear from this foregoing description and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

By crossing the divided word lines at the joint between the divided word lines and the word lines, the address selection MOSFE
One and the other of the memory cells sharing the drain region of T are connected to the same or almost the same number of adjacent divided word lines.

[For production]

According to the above means, even if the coupling capacitance between the drain coupling pad of one memory cell sharing the drain region of the address selection MOSFET and the divided word line changes due to mask displacement, one divided word line, that is, the word line When viewed as , the changes in coupling capacitance are canceled out, and the coupling capacitance between each data line and the adjacent word line becomes approximately the same electrostatic capacitance. This makes it possible to realize a dynamic RAM that suppresses array noise and improves read margin.

〔Example〕

FIG. 2 shows a dynamic RA to which this invention is applied.
A circuit block diagram of one embodiment of M is shown. Each circuit element in the figure is a well-known CMO8 (complementary MOSFET)
Depending on the integrated circuit manufacturing technology, the integrated circuit is formed on a single semiconductor substrate made of single-crystal P-type silicon, although this is not particularly limited.

N-channel MOSFETs are made of polycrystalline silicon (polysilicon), which is formed on the surface of a semiconductor substrate with a source region, a drain region, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source and drain regions. )
It consists of a gate electrode consisting of: The P-channel MOSFET is formed in the Nu well region formed in the semiconductor substrate. As a result, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOSFETs formed thereon, and the N-type well region constitutes a substrate gate for P-channel MOSFETs formed thereon.

In FIG. 1, the memory array M-ARY has a bit line (folded bit line at two intersections) method, although it is not particularly limited.
m+1 word lines WO~ arranged in the vertical direction of the figure
(m+1)X(n+
1) Consisting of memory cells. Each memory cell is composed of an information storage capacitor C8 and an N-channel address selection MOSFET Qm connected in series, and each signal line of each complementary data line has m +1 fli arranged in the corresponding column. ! The input/output nodes of l memory cells are coupled with a predetermined regularity as shown in the figure. Furthermore, as described later, n+1 divided word lines are connected to each word string, and these divided word lines are further arranged in corresponding rows (n
+ 1 )/(n+1) address selection MOSFET gates of the memory cells are coupled to each other. As a result, each word line has n+
One memory cell is combined.

Each complementary data line constituting the memory array M-ARY is
On the other hand, it is coupled to the corresponding unit circuit USA of the sense amplifier circuit SA via the corresponding precharge MOSFET of the precharge circuit PC. The precharge circuit PC includes an N-channel MOSFETQ7. As represented by Q8, the complementary data line DO/DO or Dn
*n+1 switches MO3 provided between Dn
1'ET. These switches MOSF
The gates of ETQ7 to Q8 are supplied with a precharge tying signal φ that is at a high level in the chip non-selected state.
pe is supplied. This allows each switch MOSFE
T is on when the dynamic RAM is not selected, and shorts the non-inverted signal line and the inverted signal line of each complementary data line that was set to high or low level by the amplification operation of the sense amplifier SA, which will be described later, in the previous memory access. Then, both signal lines are set to a half precharge level that is approximately 1/2 of the power supply voltage Wee.

In such a half precharge method, a half precharge level is formed by simply shorting the high level and low level of both signal lines constituting each complementary data line, so that power consumption can be reduced. In addition, in the amplification operation of the sense amplifier circuit SA, which will be described later, the potential of each complementary data line changes from the half precharge level to the high level or low level in a common mode, so that the read operation can be speeded up and capacitive coupling is reduced. This makes it possible to reduce the noise level generated.

As shown in Figure 2, the unit circuit USA of the sense amplifier circuit SA includes P-channel MOSFETQ3. CMO consisting of Q4 and N-channel MOSFET Q5゜Q6
It is composed of an S latch circuit, and each input/output node is coupled to a corresponding complementary data line DO/DO to Dn-Dn. In addition, although not particularly limited to the above latch circuit,
Power supply voltage Vaa is supplied through a sense amplifier drive circuit consisting of parallel-type P-channel MOSFETs QI and Q2, and parallel-type N-channel MOSFETs Q13 and Q2.
The ground voltage of the circuit is supplied through another sense amplifier drive circuit consisting of 14. These sense amplifier drive circuits are commonly used for a plurality of unit circuits of sense amplifier circuits SA provided corresponding to other columns within the same memory mat. That is, the sources of the P-channel MOSFET and N-channel MOSFET constituting each unit circuit in the same memory mat are commonly connected to the common source iPS or NS, respectively. MOSFETQI and Q13 that constitute the sense amplifier drive circuit are connected to one MOSFET
It is made to have a small conductance compared to SFETs Q2 and Q14.

Complementary timing signals φpal and φpal for activating the sense amplifier SA in the operating state of the dynamic RAM are supplied to the gates of MOSFETs QI and Q13 of the sense amplifier drive circuit, respectively, and the MOS
Complementary timing signals spa2 and i, which are formed slightly behind the complementary timing signals ψpal and φpal, are supplied to the gates of the FETs Q2 and Q14, respectively. As a result, the amplification operation of the sense amplifier SA is performed in two stages. That is, the complementary timing signal φpa
In the first stage where l and φpal are formed, the minute read signal of the selected memory cell applied via the corresponding pair of complementary data lines is controlled by the current limiting action of MOSFETs Q1 and Q13 with relatively small conductance. , are amplified by the corresponding unit circuits of the sense amplifier circuit SA without undergoing any undesired level fluctuations. After the potential difference between the two signal lines of the complementary data line is increased to some extent by the amplification operation of the sense amplifier circuit, the complementary timing pulse φpa2 and the in
is formed and enters the second stage, MOSFETs Q2 and Q14 having relatively large conductance are turned on. The amplification operation of the sense amplifier circuit SA is performed using MOSFE.
This is facilitated by the relatively large current supply capabilities of TQ2 and Q14, and the levels of both signal lines of each complementary data signal are rapidly expanded to high or low levels. By performing the amplification operation of the sense amplifier circuit SA in two stages in this manner, it is possible to read data at high speed while preventing undesired level changes in the complementary data line.

On the other hand, each complementary data line is selectively connected to complementary common data line CD-CD via a corresponding switch MOSFET of column switch C8W.

Column switch C8W is an n + 1 pair of switch MOSFETs Q9 and QI coupled to the corresponding complementary data line.
It is composed of O to Qll and Q12. The other terminals of these switch MOSFETs are commonly coupled to a non-inverted common data line CD or an inverted common data line CD forming a complementary common data line. Thereby, the column switch C8W selectively connects the complementary data lines DO-DO to Dn-Dn and the common complementary data line CD-CD. Two switches MO in each pair forming column switch C8W
The gates of the SFETs are connected in common, and each is supplied with a data line selection signal YO-Yn formed by a column address decoder CDCR.

Column address decoder CDCR receives complementary internal address signal a supplied from column address buffer CADB.
yO-ayi (here, for example, an internal address signal ayO having the same phase as the external address signal AYO and an internal address signal a70 having the opposite phase are collectively expressed as a complementary internal address signal ayo. The same applies hereinafter) and performs timing control. According to the data line selection timing signal φy supplied from the circuit TC, the data line selection signals YO to Yn are formed and supplied to the column switch C8W.

Column address buffer CADB is connected to external terminals AO to A.
Y address signals AYO-AYi supplied via i, form complementary internal address signals ayO-ayl, and supply them to column address decoder CDCR. In the dynamic RAM of this embodiment, the Y address signals AYO to AYi for specifying column addresses and the X address signals AXO to AXi for specifying row addresses are as follows:
A so-called address multiplex method is used in which the X address signals AXO to A1 are supplied in a time-divided manner by the same external terminals AO to A1, and the X address signals AXO to AXI also outputs the Y address signal AY in synchronization with the falling of the column address strobe signal CAS.
O-AYi is supplied respectively. For this reason, the column address buffer 7CADB is activated by the timing signal φ&e generated by detecting the fall of the column address strobe signal CAS by the timing control circuit TC, and is activated by the Y address supplied to the external terminals AO to A1. It takes in signals AYO-AYI and holds them, and also forms complementary internal address signals ayO-a71 and supplies them to column address decoder CDH.

On the other hand, the gates of the address selection MOSFETs Qm of the memory cells arranged in the same row of the memory array M-ARY are coupled to the corresponding word lines WO to Wm via the corresponding divided word lines, as will be described later. . word line WO
~Wm are further coupled to a row address decoder, from which one word line designated by the X address signals AXO-AX1 is selected.

Although not particularly limited, the row address decoder has a two-stage configuration, and is configured by a combination of a primary row address decoder RDCRI and a secondary row address decoder RDCR2. The primary row address decoder RDCRI is
Complementary internal address signal aXO and x1 of lower 2 bits
and four word line selection timing signals φx00 to φxll (not shown) synchronized with the timing signal φX supplied from the timing control circuit TC.
form. These word line selection timing signals are
Complementary internal address signals ax2 to ax excluding the lower 2 bits
Secondary row address decoder RDCR2 that decodes l
By combining with the common selection signal formed by the word operation selection signal (WO
~Wm) is formed.

By configuring the row address system selection circuit in two stages as described above, it is possible to match the layout pitch (spacing) of the unit circuits of the secondary row address decoder RDCR2 with the layout pitch of the word lines. The layout can be made efficient.

The row address buffer RADB receives a row address signal supplied from the address multiplexer AMX,
While holding it, the complementary internal address signal 5xO
~axl is formed into a primary four address decoder RDC
RI and secondary are supplied to the address decoder RDCR2.

By the way, the dynamic RAM of this embodiment is provided with an automatic write mode for reading and rewriting data stored in memory cells within a predetermined cycle.
In this automatic 7-receive mode, a 7-receive address column REFC is provided for specifying the word line to which the 7-receive is to be performed. The address multiplexer AMX is supplied with X address signals AXO to AX1 supplied via external terminals AO-AI and a refresh address counter REFC in accordance with a timing signal ψref supplied from a timing control circuit TC. 7
It selects address signals exo-cxl for writing and transmits them to row address buffer RADB as row address signals. That is, in a normal memory access mode in which the timing signal ψref is at a low level, X address signals AXO to AXi supplied from an external device via external terminals AO to A1 are selected, and the timing signal φr is selected.
In the automatic refresher mode in which ef is at a high level, the refresher island address signal CXO to ext, which is also output from the address counter REFC for refreshing, is selected.

Since the X address signals AXO to AXI are supplied in synchronization with the fall of the row address strobe signal RAS, which is supplied as a control signal from the outside, the timing control circuit TC allows the row address buffer RADB to take in the row address signal. This is performed in accordance with a timing signal φar generated by detecting the fall of the row address strobe signal RAS.

In FIG. 2, the input terminal of the main amplifier MA is coupled to the complementary common data line CD-CD, and the output terminal of the data cover 7R is coupled to the complementary common data line CD-CD.

Main amplifier MA further amplifies the binary read signal transmitted from the selected complementary data line via complementary common data line CD-CD, and transmits it to data output buffer DOB. The data output buffer DOB is a dynamic type R
In the read operation mode of AM, the timing signal φr supplied from the timing control circuit TC causes the AM to operate, and the output signal of the main amplifier MA is sent to the output terminal D.
Output to an external device from out. Dynamic RA
In the non-selected state of M and in the write operation mode, the output of the data output buffer DOB is in a high impedance state.

The data manual buffer DIR is a dynamic RAM
In the committed operation mode, the timing control circuit T
It is put into an operating state by a timing signal φW supplied from C, and write data supplied from an external device via an input terminal Din is made into a complementary write signal and transmitted to a complementary common data line CD-CD. Dynamic W RA
In the non-selected state of M and in the read operation mode, the output of the data input buffer DIB is in a high impedance state.

The refresh address counter REFC counts the timing signal -0 supplied from the timing control circuit TC in the automatic refresh mode of the dynamic RAM, and specifies the address of the seven refresher word lines.

The timing control circuit TC forms the above-mentioned various timing signals based on the row address strobe signal RAS, column address strobe signal CAS, and multi-item enable signal WE supplied as control signals from the outside, and supplies them to each circuit.

FIG. 1 shows a layout diagram of an embodiment of the dynamic RAM memory array M-ARY shown in FIG. In order to prevent confusion, a part of mesori array M-ARY, complementary data lines DL and DL, and address selection MO
Divided word lines DWL a 1 to DWL a to which two memory cells sharing the drain region of SFET are coupled
s, DWLb1 to DWLbs and the layout of adjacent word lines WLa to WLb to which these divided word lines are coupled are exemplarily shown.

In FIG. 1, each memory cell is composed of an information storage capacitor C3 and an address selection MOSFET whose gate region is the corresponding divided word line.

FIG. 6 shows a sectional view taken along the line AB in FIG. WX1 in order to more specifically explain the structure of the memory cell shown in FIG. Before explaining the layout of FIG. 1, the outline of the structure of the memory cell will be explained with reference to FIG.

In FIG. 7, the memory cells are not particularly limited, but are
It is formed on a semiconductor substrate SUB made of single-crystal P-type silicon. In addition, in two adjacent memory cells,
The drain region of the address selection MO3FET is shared. On the semiconductor substrate SUB, there are two N+ regions for forming source regions S of two address selection MOSFETs, and an N+ region for forming a drain region shared by the two address selection MOSFETs. provided. A semiconductor substrate S including these N+ regions
A relatively thick field insulating film FI and a relatively thin gate insulating film GI are provided over UB. The field insulation %FI and the gate insulation film GI are, for example, silicon oxide films S10! formed by. Other memory cell pairs in contact with each other are separated by this field insulating film FI.

In addition, polycrystalline silicon (
Cell plate C formed by polysilicon) psi
P is provided. By applying an appropriate positive voltage to this cell layer CP, a channel is induced on the semiconductor substrate SUB sandwiching the cell layer CP, and between this channel and the cell layer CP there is a gate insulating film G.
An information storage capacitor (, s) is formed with I as a dielectric.

Between the two source regions S and the shared drain region formed on the semiconductor substrate SUB, divided words 1DWLal and DWLbl are provided with an insulating film in between. These divided word lines are formed of polycrystalline silicon pS1 and silicide SIC such as silicon molybdenum (Movie) having a higher conductivity than polycrystalline silicon pS1, although not particularly limited thereto.

Since the dynamic RAM of this embodiment has a large storage capacity and is highly integrated, the size of the memory cell is reduced by reducing the shared drain region. Therefore, there is less alignment margin for coupling the data line DL formed by the drain region and the aluminum layer, making direct coupling difficult. Therefore, the bonding pad Pa is provided so as to overlap the pattern of the divided words DWLal and ])WLbl.

Although not particularly limited, the coupling pad Pa is formed of polycrystalline silicon pSl, and its lower end is coupled to the shared drain region. Data line DL formed of an aluminum layer is coupled to the shared drain region via this coupling pad P&.

Next, according to FIG. 1, the dynamic type RA of this embodiment
The AI shunt method of M will be explained.

In FIG. 1, the topmost memory cell is coupled to divided word lines DWLal and DWLbl, and also to non-inverted data #DL. A memory cell formed immediately below this memory cell and shifted by 1/2 pitch is coupled to another divided word block (not shown) and is also coupled to inverted data #DL.

In the dynamic RAM of this embodiment, although not particularly limited, n+1 divided word lines represented by divided words dDWLal to DWLaa+1 and DWL b 1 to DWL b s are provided.
(n+1)/2(n+1) memory cells are coupled to DWLa-1 and DWLa-1, and (n+1)/(n+1) memory cells are coupled to other divided word lines other than these divided word lines. Each is combined. Each divided word line is
In the part marked with ○ in Figure 1, word &! WLa or W
It is coupled to Lb. In addition, the divided word MDWL in FIG.
As represented by bl, each divided word line is connected to the opposite divided word, 1DW, below the connection with the word line.
Intersects with Lal or DWLa2, etc.

Therefore, for example, in the case of the divided word line DWLbl, the right side (n+1)/2 of the memory cells sharing the drain region above the joint with the word line WLb
(n+1) memory cells are coupled, and below the coupling portion with word line WLb, the left (n+1)/2 (n
+1) memory cells are combined. Divided word line D
WLal is connected to the (n+1)/2(n+1) memory cells closest to Tonosho among the memory cells sharing the drain region, and divided word 1JDWLas+1 is connected to the lowest memory cells among the memory cells sharing the drain region. On the cloth side (
n+1 )/2 (n+1) memory cells are coupled. As a result, divided word lines DWLal and DWL
Each divided word line except ai+1 has (n+1)/2(n+1) memory cells arranged on the left and right sides of the memory cells sharing the drain region, that is, a total of (n+1)
+1)/(n+1) memory cells are combined. Each word line also has (n+1)/
Two memory cells each, ie, a total of (n+1) memory cells are coupled.

From these facts, the dynamic RAM of this embodiment
Then, even if a mask shift occurs in the data line direction during the manufacturing process and the coupling capacitance between the coupling pad Pa of each memory cell, that is, the data line and the divided word line changes, the difference between the entire one divided word line and Changes in coupling i between data lines cancel out. In other words, when the coupling pad Pa shown in FIG. 7 shifts tk' due to mask misalignment, if the coupling capacitance for one divided word line increases in the portion of two memory cells that share a drain region, the coupling pad Pa shown in FIG. On the contrary, the coupling capacitance to the divided word lines becomes smaller. As described above, the same number of memory cells on the left and right sides of the memory cells sharing the drain region are coupled to each divided word line. Therefore, changes in coupling capacitance between the data line and word line due to mask displacement are canceled out. This equalizes the coupling capacitance between each word line and data line, and
Word lines that would have extremely large coupling capacitance due to mask misalignment are eliminated.

As described above, in the dynamic RAM of this embodiment, the divided word lines intersect at the junction between the divided word lines and the word lines, and the same number of memory cells on one side and the other side of the memory cells sharing the drain region cross over the divided word lines. line and thus the word line. Therefore, changes in the coupling capacitance between the word line and the data line due to mask displacement are canceled out, and the coupling capacitance between the word line and the data line is equalized. Therefore, a level change of the data line according to the stored data of the memory cell coupled to the selected word line is induced in the unselected word line, so that the address selection MO5FET of the unselected memory cell is brought into a rapidly on state. This can be prevented, and the read margin as a dynamic RAM can be improved.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) The divided word lines are crossed at the joint between the divided word lines and the word line, and the same or almost the same number of memory cells sharing the drain region are connected to the divided word line, that is, the word line. By doing this, it is possible to offset the change in the coupling capacitance between the word line and the data line due to mask misalignment, equalize the coupling capacitance between the word line and the data line, and also make it possible to equalize the coupling capacitance between the word line and the data line. This has the effect of eliminating word lines.

(2) According to the above item (1), the play noise induced in the unselected word line due to the level change of the data line according to the stored data of the memory cell coupled to the selected word line is suppressed, and the unselected word line is thereby suppressed. The effect is that malfunction of the address selection MOSFET of the memory cell can be prevented.

(3) Layout is performed using the junction between divided word lines and word lines, so no space is required for crossing, so the above (1) can be achieved without increasing the chip size.
The effects of paragraphs and (2) can be obtained.

(4) Items (1) to (3) above provide the effect of realizing a highly integrated, large-capacity dynamic RAM with improved read operation margin.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, each divided word line is connected to a corresponding word line at approximately the center, but as shown in FIG. 4, each divided word line is connected to a corresponding word line at the top or bottom of the divided word line. You can also set it to 5. In addition, as shown in FIG. 5, the divided word lines are not crossed, and only one of the memory cells sharing the drain region is coupled to each divided word line, and among the memory cells sharing the drain region to each word line, the divided word lines are not crossed. It is also possible to equalize the coupling capacitance of each word line by coupling the same number of divided word lines with memory cells on each side. Alternatively, the coupling may be performed not only on the memory cell array, but also on the region for the above-mentioned coupling provided between the memory cell arrays by appropriately dividing the memory cell array. In this case, a field insulating film is formed on the main surface of the semiconductor substrate corresponding to the region for coupling.

Thereby, it is possible to prevent defects caused by etching or the like for forming connection holes for the above-mentioned bonding. The divided word lines shown in FIG. 4 may be made using only polycrystalline silicon, and the materials used for the word lines and other parts are not limited to the example shown in this figure. Various embodiments can be adopted, such as the specific circuit block configuration and control signal combinations of the dynamic RAM shown in FIG.

In the above explanation, the invention made by the present inventor was mainly applied to a dynamic RAM using a single-element type memory cell, which is the background field of application of the invention, but the invention is not limited thereto. Instead, it can be applied to various other dynamic RAMs using similar memory cells and various digital devices incorporating such dynamic RAMs. The present invention provides at least one
The present invention can be applied to a dynamic RAM employing an A1 shunt method using an element type dynamic memory cell and a semiconductor integrated circuit device incorporating such a dynamic RAM.

[Brief explanation of the drawing]

FIG. 1 shows a dynamic RA that shows one embodiment of the present invention.
FIG. 3 is a layout diagram showing a memory array of M. FIG. 2 is a circuit block diagram showing an embodiment of a dynamic RAM to which the present invention is applied. FIG. 3, FIG. 4, and FIG. 5 are layout diagrams showing memory play of a dynamic RAM showing a modification of the embodiment of the present invention. FIG. 6 is a layout diagram showing an example of a memory array in a conventional dynamic RAM. FIG. 7 is a sectional view taken along line AB in the memory array of the dynamic RAM shown in FIGS. 5 and 1. FIG. Cs = information storage capacitor, DWL a 1-DW
Lai+1. DWLb l to DWLb s... divided word line, WLa, wLb-word line, D L-... data line. M-ARY...Memory array, PC...Precharge circuit, SA...Sense amplifier circuit, C8W...Column switch, RDCRI...Primary row address decoder, RDCR2...Secondary row address decoder, C
DCR...Column address decoder, RADB...
Row address buffer, AMX...address multiplexer, CADB-...column address buffer, M
A...Main amplifier, DOB...Data output buffer, DIR-...Data driver 7a, vcpG-
...Cell plate voltage generation circuit, REFC...Refresh breath address counter, TC...Timing control circuit. USA: Sense amplifier unit circuit, Ca: Capacitor for information storage, Qm: MOSFE for address transparent selection
TSQl~Q4...P channel MOSFET. Q5~Q14...N channel MOS FET. SUB...Semiconductor substrate, S-...Source region, D...
・Drain region, CP...Cell plate, P a...
・Coupling pad, FI...Field insulating film, GI・
...Gate insulating film, Cfl, Cf2-...Coupling capacitance.

Claims (1)

[Claims] 1. A plurality of data lines arranged in parallel, a plurality of word lines orthogonal to the data lines and each arranged in parallel, and at the intersection of the data lines and the word lines. a pair of memory cells arranged in a lattice pattern, each consisting of an information storage capacitor and an address selection MOSFET and coupled to adjacent word lines; arranged parallel to and separated from the word lines, and arranged in corresponding rows; M for selecting some addresses of multiple memory cells
A semiconductor integrated circuit device comprising a plurality of divided word lines to which gates of OSFETs are coupled and each divided word line is coupled to a corresponding word line. 2. Claim 1, characterized in that, with respect to the two adjacent word lines, the memory cells arranged on one side and the memory cells arranged on the other side are connected in the same number or almost the same number. semiconductor integrated circuit devices. 3. The divided word lines intersect at the joints with the word lines, so that the memory cells arranged on one side of the two adjacent word lines and the memory cells arranged on the other side are 2. The semiconductor integrated circuit device according to claim 1, wherein the same number or substantially the same number of word lines are connected to two adjacent word lines. 4. The semiconductor integrated circuit device according to claim 1, wherein the word line is formed of an aluminum layer. 5. The semiconductor integrated circuit device according to claim 1, wherein the divided word line is formed of a polycrystalline silicon layer. 6. The semiconductor integrated circuit device according to claim 1, wherein the divided word lines are formed of a silicide layer. 7. The semiconductor integrated circuit device according to claim 1, wherein the divided word line is formed of a two-layer film consisting of a polycrystalline silicon layer and a silicide layer. 8. The semiconductor integrated circuit device according to claim 1, wherein the coupling portion between the word line and the divided word line is located on the memory cell or the memory cell array. 9. The semiconductor integrated circuit device according to claim 8, wherein a coupling portion between the word line and the divided word line is located between the memory cell arrays.